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Messages from 131475

Article: 131475
Subject: Re: Newbie: Testbench question
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Tue, 22 Apr 2008 16:05:47 +0100
Links: << >>  << T >>  << A >>
> Hello, thanks for responding to my post. Sorry for me confusing
> everyone. Let's say I have a large design that has lots of inputs and
> outputs and let's say I'm only interested in a simulation consisting
> of only a few inputs and outputs. When I run ModelSim it will add in
> all the inputs/output of the module I am simulating, thus adding in
> all of the inputs and outputs of my design into the waveform window. I
> was hoping I could configure something so when the simulation finishes
> it would display the signals I'm interested in. Is that possible? I'll
> also try the other newsgroup and see if anyone has a solution.


How are you running Modelsim?

When I run it up, load a project/simulation then open the wave window there
are no signals in it.

I've got a 'standard' naming convention so I can easily find and load the
*.do file that loads the signals associated with a particular testbench.
These are then saved in the /Modesim sub directory of the project in
question.



Nial. 



Article: 131476
Subject: Re: Newbie: Testbench question
From: Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid>
Date: Tue, 22 Apr 2008 17:09:05 +0200
Links: << >>  << T >>  << A >>
In comp.arch.fpga,
jjlindula@hotmail.com <jjlindula@hotmail.com> wrote:
> On Apr 22, 2:13 am, "HT-Lab" <han...@ht-lab.com> wrote:
>> <jjlind...@hotmail.com> wrote in message
>>
>> news:7c110d97-7eaa-440e-a661-225a0fd05de2@f36g2000hsa.googlegroups.com...
>>
>> ..snip
>>
>> > );
>> > Here only a few signals would be stimulated and few signals would
>> > appear in the ModelSim simulation window. Is there a way to do this?
>>
>> I probably don't understand you question but you can simply drag and drop
>> the signals of interest from the Objects window onto the Waveform window. If
>> you want to do this from a script than look up the "add wave" command in the
>> reference manual.
>>
>
> Hello, thanks for responding to my post. Sorry for me confusing
> everyone. Let's say I have a large design that has lots of inputs and
> outputs and let's say I'm only interested in a simulation consisting
> of only a few inputs and outputs. When I run ModelSim it will add in
> all the inputs/output of the module I am simulating, thus adding in
> all of the inputs and outputs of my design into the waveform window. I
> was hoping I could configure something so when the simulation finishes
> it would display the signals I'm interested in. Is that possible? I'll
> also try the other newsgroup and see if anyone has a solution.

I don't believe modelsim automatically adds signals to the wave window,
it also does not automatically run a simulation.
How do you start modelsim? Your environment may start modelsim with a
scriptfile (.do) and it may have generated a default for this script
that adds all your IO to the wave window and runs the simulation to
completion.

If you can find that script, you can probably modify it to suit your
needs.

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Out of sig error

Article: 131477
Subject: Re: Newbie: Testbench question
From: Philip Potter <pgp@doc.ic.ac.uk>
Date: Tue, 22 Apr 2008 16:22:23 +0100
Links: << >>  << T >>  << A >>
Stef wrote:
> In comp.arch.fpga,
> jjlindula@hotmail.com <jjlindula@hotmail.com> wrote:
>> Hello, thanks for responding to my post. Sorry for me confusing
>> everyone. Let's say I have a large design that has lots of inputs and
>> outputs and let's say I'm only interested in a simulation consisting
>> of only a few inputs and outputs. When I run ModelSim it will add in
>> all the inputs/output of the module I am simulating, thus adding in
>> all of the inputs and outputs of my design into the waveform window. I
>> was hoping I could configure something so when the simulation finishes
>> it would display the signals I'm interested in. Is that possible? I'll
>> also try the other newsgroup and see if anyone has a solution.
> 
> I don't believe modelsim automatically adds signals to the wave window,
> it also does not automatically run a simulation.
> How do you start modelsim? Your environment may start modelsim with a
> scriptfile (.do) and it may have generated a default for this script
> that adds all your IO to the wave window and runs the simulation to
> completion.
> 
> If you can find that script, you can probably modify it to suit your
> needs.
> 
Alternatively, you can just delete the signals you don't want from the 
wave window after they've been added.

Article: 131478
Subject: Need a few Xilinx Spartan FPGAs
From: Jon Elson <elson@pico-systems.com>
Date: Tue, 22 Apr 2008 10:50:45 -0500
Links: << >>  << T >>  << A >>
Hello,

Does anyone have a few XCS30 -3TQ144C FPGAs around, or know a
distributor who will sell in small quantity?  I need about a 
dozen to finish off the last boards using that chip.

I've just about finished the conversion to the Spartan 2E
but need to use up these last blank boards first.

Thanks in advance for any pointers.  (Yes, Digi-key will gladly
sell me a minimum of 60 for $2600!)

Jon

Article: 131479
Subject: Re: How to independently program the embedded PowerPC in a Virtex?
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Tue, 22 Apr 2008 09:13:35 -0700
Links: << >>  << T >>  << A >>
Denkedran Joe wrote:
> Hi,
> 
> I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd like to 
> ask for a way to program the embedded PowerPC independently from booting the 
> whole FPGA via the Xilinx Platform Flash. Is there a way to account for 
> that, maybe be designing an additional Flash device in the BS chain? Is it 
> even possible to run the PowerPC even though the FPGA is not programmed?
> 
> Regards
> Joe 
> 
> 

I'm curious.

Assuming that you could run a program on the Virtex-II Pro PowerPC using 
data stored in caches, but not connected to anything else in the device 
as you haven't programmed a design into the FPGA what exactly would you 
do with it?

Ed McGettigan
--
Xilinx Inc

Article: 131480
Subject: Re: How to independently program the embedded PowerPC in a Virtex?
From: Tim Wescott <tim@seemywebsite.com>
Date: Tue, 22 Apr 2008 11:43:48 -0500
Links: << >>  << T >>  << A >>
On Tue, 22 Apr 2008 08:24:27 +0200, Denkedran Joe wrote:

> Hi,
> 
> I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd
> like to ask for a way to program the embedded PowerPC independently from
> booting the whole FPGA via the Xilinx Platform Flash. Is there a way to
> account for that, maybe be designing an additional Flash device in the
> BS chain? Is it even possible to run the PowerPC even though the FPGA is
> not programmed?
> 
> Regards
> Joe

The processor pretty much has to run out of memory blocks in the FPGA, 
that happen to be initialized to a particular pattern from the flash, 
right?  So find a way to load up your program into the pertinent memory!  
There's a gazillion different ways to do this, depending on what you're 
trying to do.  Here's some:

* Use an itty bitty serial download program that accepts Motorola hex 
files
* Use an external parallel-access flash part and run straight out of that 
(this is slow, and uses lots of pins, but it's easy).
* Use an extra serial flash device that's _not_ in the BS chain, that you 
can bit-bang from the processor to load memory.
* Use an external NAND flash part (with lots of on-board memory to read 
it).

IIRC the PowerPC core floats in the Xilinx part until you connect it - 
there's no dedicated pins to get to the outside world.  So you're out of 
luck until you program the FPGA.  I think the Atmel FPSlic parts 
connected the processor straight to the outside world, but they're not 
nearly as powerful, and they were kind of a flash in the pan -- I don't 
know how they're doing or how well they're supported now.

-- 
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html

Article: 131481
Subject: Re: synchronous reset problems on FPGA
From: Andy Peters <google@latke.net>
Date: Tue, 22 Apr 2008 09:55:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 21, 2:34 am, Lars <noreply.lar...@gmail.com> wrote:

> There is an obvious answer that nobody seems to have mentioned: Use
> the "LOCKED" signal from the DCM as reset to the logic that is clocked
> by the clock from the DCM. I am not quite sure about the numbers, but
> there ought to be at least one clock edge from the DCM before that
> goes active. If you need more clock edges, delay the "LOCKED" signal
> in a shift register (one SLR16 will give you 16 clock cycles delay
> from just one LUT).

Yep, the DCM locked output does the trick!

-a

Article: 131482
Subject: Xilinx is cancelling the Virtex-E XCV1000E-FG860
From: Alan Nishioka <alan@nishioka.com>
Date: Tue, 22 Apr 2008 12:11:11 -0700
Links: << >>  << T >>  << A >>
Xilinx is canceling the Virtex-E XCV1000E-FG860.

We are currently shipping a product that uses 13 of these chips on 4 
different boards.

Does anyone have any ideas on how to deal with this?

One possibility is to rev the boards to use the XCV1000E-FG900, making 
minimal changes to the boards around the fpga.

Complete re-design of the boards for this old system is out of the 
question.  Stockpiling a bunch of parts won't work because we don't know 
what future quantities will be and the parts are very expensive.

Alan Nishioka
alan@nishioka.com

Article: 131483
Subject: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
From: austin <austin@xilinx.com>
Date: Tue, 22 Apr 2008 13:57:49 -0700
Links: << >>  << T >>  << A >>


Alan,

What is your present volume?

Austin

Article: 131484
Subject: Re: DCM configuration in Virtex-4 FPGA
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 22 Apr 2008 16:59:19 -0400
Links: << >>  << T >>  << A >>
<mspiegels@gmail.com> wrote in message 
news:ba79fdd6-bd77-4b2c-a1a8-b2253055a564@x19g2000prg.googlegroups.com...
>
> The only problem is that i have no idee which pins belong to the
> DCM...and don't know how to connect the DCM's clock outputs to the
> DIFF CLK output-pins in order to measure them.
> So if anybody could tell me which bank and pin-number belongs to the
> DCM(s) i would be very happy :)
>

There are no pins belonging to DCMs. There are pins dedicated as clock 
inputs though. Usually pin assignments are handled in the project's UCF 
file. For your differential output you need to instantiate a differential 
driver in your HDL code and assign the pins in the UCF.. Driving clock out 
of the chip is better done with a DDR register in IOB, but this is another 
issue, probably not important for you at this point.


/Mikhail





Article: 131485
Subject: FPGA Verilog state machine lock up
From: NN <neena.nambiar@gmail.com>
Date: Tue, 22 Apr 2008 14:08:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,

I am using Verilog to program a Xilinx FPGA. The program is basically
a state machine with at least 32 states. There is an internal counter
that counts and allows the state machine to move from one state to the
next. This program simulates well both pre and post synthesis and goes
through all the states continuously. Once it is loaded into the FPGA
it gets stuck up in one state. The solution I realised was to
increment the counter value at the state where it is stuck when the
state machine transitions to the next state.  There is enough time
between states as it is. I am not sure why this is happening. I will
appreciate if I can get some tips on this issue.

Thanks
Neena

Article: 131486
Subject: Re: DCM configuration in Virtex-4 FPGA
From: austin <austin@xilinx.com>
Date: Tue, 22 Apr 2008 14:32:42 -0700
Links: << >>  << T >>  << A >>
MM,

You decide where to put the pins.

Input clocks to the DCM should come from the global clock IO pins (those
IBUFG routes are optimized for 0 delay).

Output clocks should go to a BUFG where they can get used by the things
that need them.

If you wish to observe a clock, route the BUFG to a IOB, set the IOB to
be a DDR, set the top DFF D input to '1', and the bottom DFF D input to
a '0'.

This preserves the duty cycle to within a few tens of ps, and you may
then see exactly what your clock is doing.

Using a differential output standard, and measuring the output
differentially will allow you to see the jitter on the internal BUFG,
excluding any ground or Vcc bounce (as the differential output and
differential measurement ignores common mode changes!).

The CLOCK_FB (feedback clock) to the DCM should always come from the
source which you are trying to align to create 0 skew: ie. the output
BUFG itself, or if that output is sent off-chip, another global clock
input pins (IBUFG)-- 0 skew is created at the point where the clock is
delivered off-chip..

Austin

MM wrote:
> <mspiegels@gmail.com> wrote in message 
> news:ba79fdd6-bd77-4b2c-a1a8-b2253055a564@x19g2000prg.googlegroups.com...
>> The only problem is that i have no idee which pins belong to the
>> DCM...and don't know how to connect the DCM's clock outputs to the
>> DIFF CLK output-pins in order to measure them.
>> So if anybody could tell me which bank and pin-number belongs to the
>> DCM(s) i would be very happy :)
>>
> 
> There are no pins belonging to DCMs. There are pins dedicated as clock 
> inputs though. Usually pin assignments are handled in the project's UCF 
> file. For your differential output you need to instantiate a differential 
> driver in your HDL code and assign the pins in the UCF.. Driving clock out 
> of the chip is better done with a DDR register in IOB, but this is another 
> issue, probably not important for you at this point.
> 
> 
> /Mikhail
> 
> 
> 
> 

Article: 131487
Subject: Re: FPGA Verilog state machine lock up
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 22 Apr 2008 14:47:08 -0700
Links: << >>  << T >>  << A >>
NN wrote:

> Once it is loaded into the FPGA
> it gets stuck up in one state. 

Maybe one of the inputs is not synchronized to the fpga clock.

        -- Mike Treseler

Article: 131488
Subject: Can somebody help about Period Timing Constraints
From: songrise@gmail.com
Date: Tue, 22 Apr 2008 15:58:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,

I don't understand is there any the relationship between the value of
period constraints and my input clock?

For my system, Board input clock is 50MHz, system works at 500MHz.
When there is no timing constraints: Chipscope result is not right:
some signals should be all zero while they show certain pulses, which
are shorter than normal. Although the chipscope output becomes right
when I add 60 ns period timing constraints, but i don't know why this
happens, what does the 60ns means? is it too long a time for the
system?  if i add 20ns, it won't pass the implementation. By the way,
there are 160X8bits registers being used in the system. and the device
is Virtex-5, XC5VLX110T,

1, When there is no timing constraints:( Chipscope result is not
right: some signals should be all zero while they show certain pulses,
which are shorter than normal.)
Timing errors: 0  Score: 0
Constraints cover 2171 paths, 0 nets, and 695 connections
Design statistics:
   Minimum period:   4.138ns   (Maximum frequency: 241.663MHz)
   Maximum path delay from/to any node:   4.138ns

2, When i add 20 ns period timing constraints, error occurs as:  Pack:
1653 - At least one timing constraint is impossible to meet because
component delays alone exceed the
constraint.  A physical timing constraint summary will appear in the
map report.  This summary will show a MINIMUM  net delay for the
paths.  For more information about the Timing Analyzer, consult the
Xilinx Timing Analyzer Reference manual.  For more information on
TRCE, consult the Xilinx Development System Reference Guide "TRACE"
chapter.


3, When i add 60 ns period timing constraits, there will be no problem
from Chipscope,

Timing errors: 0  Score: 0
Constraints cover 38571 paths, 0 nets, and 4430 connections
Design statistics:
   Minimum period:   6.175ns   (Maximum frequency: 161.943MHz)
   Maximum path delay from/to any node:   6.175ns
   Minimum input required time before clock:   3.585ns
   Minimum output required time after clock:   4.935ns

Thank you all.

Article: 131489
Subject: Re: counterfeit Xilinx ?
From: -jg <Jim.Granville@gmail.com>
Date: Tue, 22 Apr 2008 17:46:14 -0700 (PDT)
Links: << >>  << T >>  << A >>


Jon Elson wrote:
> But, I have no other examples of Spartan chips which DON'T have
> the Spartan(tm) marking right below the Xilinx(tm) logo.  That
> was one of the things that made me curious, although I don't
> know why a counterfeiter would miss something that obvious.


This in the news is topical to this thread

"SIA launches fight against fake chips"
http://www.eetasia.com/ART_8800518744_480200_NT_b37a60ac.HTM
" the SIA is fighting on several fronts, including China where huge
stores of fake goods operate freely.

The fake chips are often rebranded parts claiming greater performance
than they actually have to earn the sellers a fast profit. "

-jg

Article: 131490
Subject: Re: Turning off the DLL to run DDR2 at very low frequency
From: adubinsky457@gmail.com
Date: Tue, 22 Apr 2008 20:19:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 21, 4:36=A0pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
> adubinsky...@gmail.com wrote:
> > Hi,
>
> > There's been a few discussions about this the last couple years, but
> > it seems nothing ended with firm conclusions. What I would like to do
> > is to run DDR2 at 25MHz (DDR50). I understand that to do this I have
> > to turn off the DLL (which can't work at below 125MHz) and that this
> > should work but is not supported. My question is, what happens then?
>
> > Ie: How do the DQS signals behave during read? Do they turn off,
> > become random, are synchronized with the clock? Is it safe to just
> > read the data a quarter cycle after the clock edge, or is it more
> > complicated than that? I haven't designed an sdram core before, but
> > I'm going to have to do this for this project and have many other,
> > more general questions. If someone knows some good reading material,
> > please let me know.
>
> > Aleksandr Dubinsky
>
> You won't find any firm conclusions. =A0As you've probably found out, the
> datasheets make no statements one way or another about usage when the
> DLL is disabled. =A0I did some experiments with this for a project that
> was later aborted. =A0As I recall, I ran DDR (type 1, I think) at 75MHz or=

> so, disabling the DLL. =A0As I recall it worked fine. =A0The main differen=
ce
> just seems to be that you don't have a guaranteed difference between the
> clock and DQS. =A0If your design doesn't depend on this, then it should
> work. =A0I think most designs rely on a narrow window where they expect
> DQS to show up, because the clock speed and copper lengths are fixed.
> But if you have a design that is flexible enough to allow for any sort
> of delay, it should work OK. =A0This type of flexibility is difficult,
> though. =A0There is ambiguity in the DQS edge, because you might not know
> which edge it is. =A0My design required writing data to the DRAM and then
> reading it back to determine which DQS edge I was seeing. =A0As you know,
> though, disabling the DLL carries no guarantees and performance may
> differ between brands.
>
> You could always have a design which runs the IOBs at high speeds
> (125MHz) but then connects to a memory controller running at a lower
> rate. =A0I.e., the effective speed would be about the same as a slower
> single-clock design because you would have gaps between the bursts. =A0But=

> you'd need asynchronous FIFOs. =A0-Kevin


"The main difference just seems to be that you don't have a guaranteed
difference between the clock and DQS."

It sounds like you're saying that I still have to track and
synchronize to the DQS and that it acts a bit unpredictably, at least
at 75MHz.

"My design required writing data to the DRAM and then reading it back
to determine which DQS edge I was seeing."

You mean your controller was constantly re-calibrating?

"You could always have a design which runs the IOBs at high speeds
(125MHz) but then connects to a memory controller running at a lower
rate."

My reasons for running at 25MHz is signal quality on the bus.

- Alex

Article: 131491
Subject: the order in which some switches are turned on
From: laura <laura.brandusan@gmail.com>
Date: Tue, 22 Apr 2008 22:21:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,


I have an array of N switches . Initially all are OFF.


Somebody turns them ON in some order. It is possible that more
switches are turned ON in the same moment.


I need a device which shows me the order in which the switches were
turned ON. For instance the device should give me: 4,3,1,5,2 (this is
the order in which the switches were turned ON).


The way in which the output is shown in not important. It must be
simple to read (by a human, computer, etc).


It is important that the device is able to handle the turned ON (in
the same moment) of the multiple switches.


thanks,
Laura


Article: 131492
Subject: Re: opb_intc + PowerPC
From: axalay <axalay@gmail.com>
Date: Tue, 22 Apr 2008 23:05:25 -0700 (PDT)
Links: << >>  << T >>  << A >>

> Give us a clue ... what error?
>
> If the PC ends up at the "unhandled exception" handler address, check that your
> interrupt vector table is on a 64K boundary. Only the top 16 bits of the
> interrupt vector table address is actually used in the PPC. So if your table
> isn't on a boundary, the PPC doesn't vector to where you think it does.
>
> - Brian

Hello Brian.
This project is compile without error.
When I generate interrupt-my programm is hang.
I plase breakpoint in all interrupt handler functions, but program is
not jump at that breakpoints.
Size of my memory is 64K.

Article: 131493
Subject: Re: the order in which some switches are turned on
From: backhus <nix@nirgends.xyz>
Date: Wed, 23 Apr 2008 08:09:14 +0200
Links: << >>  << T >>  << A >>
Hi Laura,
FPGAs can do what you want, though it might be simpler do solve with a 
microcontroller.

The tricky thing is to define "in the same moment" more technically.
If the switches are operated manually it is virtually impossible to have 
two switches changing their state "in the same moment", even if they are 
mechanically coupled. The mechanical parts have their tolerances and 
that leads to some micro-nano-whatsoever seconds of difference. The 
question is: How precise do you want to detect the states of the 
switches and determine changes. Furthermore, even if you choose a low 
time resolution the asynchronous incoming events of 2 switches may 
happen around the moment of sampling the states of the switches. So you 
  get two events instead of the expected/desired single one.

The rest is a simple act of storing, and transmitting/displaying the 
information. That's just depends on your hardware.

In general: Your requirements are too loose. Be more specific.
What means "must be simple to read" A bunch of lamps would do it,
but then:  "by a human, computer, etc"
Humans and computers barely read the same things easily (e.g printout 
vs. RS232). And who is etc? ET's-Companion? :-)

Anyway, wether you choose FPGAs or microcontroller to solve the problem 
you have to make a decision about the way the device shall interact with 
the rest of the world, and then just do it. (Which means write some code 
to describe the hardware or program a processor or both )

Have a nice synthesis
    Eilert


laura schrieb:
> Hi all,
> 
> 
> I have an array of N switches . Initially all are OFF.
> 
> 
> Somebody turns them ON in some order. It is possible that more
> switches are turned ON in the same moment.
> 
> 
> I need a device which shows me the order in which the switches were
> turned ON. For instance the device should give me: 4,3,1,5,2 (this is
> the order in which the switches were turned ON).
> 
> 
> The way in which the output is shown in not important. It must be
> simple to read (by a human, computer, etc).
> 
> 
> It is important that the device is able to handle the turned ON (in
> the same moment) of the multiple switches.
> 
> 
> thanks,
> Laura
> 

Article: 131494
Subject: Re: Turning off the DLL to run DDR2 at very low frequency
From: mng <michael.jh.ng@gmail.com>
Date: Wed, 23 Apr 2008 00:16:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Apr 21, 12:15 pm, adubinsky...@gmail.com wrote:
> Hi,
>
> There's been a few discussions about this the last couple years, but
> it seems nothing ended with firm conclusions. What I would like to do
> is to run DDR2 at 25MHz (DDR50). I understand that to do this I have
> to turn off the DLL (which can't work at below 125MHz) and that this
> should work but is not supported. My question is, what happens then?
>
> Ie: How do the DQS signals behave during read? Do they turn off,
> become random, are synchronized with the clock? Is it safe to just
> read the data a quarter cycle after the clock edge, or is it more
> complicated than that? I haven't designed an sdram core before, but
> I'm going to have to do this for this project and have many other,
> more general questions. If someone knows some good reading material,
> please let me know.
>
> Aleksandr Dubinsky

You might just want to build a prototype and scope it out. I'm also
interested in running without the DLL, so I intend to build a test
board in the next few months.

Article: 131495
Subject: 10.1 EDK - How can I create a user library in SDK?
From: andrew.nesterov@softhome.net
Date: Wed, 23 Apr 2008 00:48:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
Dear experts,

I may need to build a few user libraries for PPC and MBZ targets, the
libraries would be hardware independent, just computational modules.

I've read this link http://www.xilinx.com/support/answers/29926.htm
Does the solution means that I have to manually edit the project's
makefile to "make" it compile and archive a library .a file?
Essentially the same way as in the EDK 9.2?

If yes, why Xilinx didn't add such a useful project type into XPS? I
quite realize that an FPGA design is more complicated than just a
software design for a fixed h/w platform, then why make it even more
complex?

Thanks so much,

Andrew

<andrew_dot_nesterov_at_techemail_dot_com>

Article: 131496
Subject: Re: Verilog state machines, latches, syntax and a bet!
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Wed, 23 Apr 2008 08:31:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2008-04-23, ee_ether <xjjzdv402@sneakemail.com> wrote:
> Hi,
>
> A colleague and I are having a friendly debate on coding state
> machines in Verilog, targeting synthesis for FPGAs.  Comments are very
> appreciated.  I am NOT trying to start a holy war here regarding
> syntax style (one process vs. two process, etc).
>
> Crux of the matter:  Do you need to define values for outputs of your
> state machine in EVERY state, or do you only need to define values for
> outputs in states where you want the output to update/change?


In a process activated by a clock edge it is not necessary to specify
the output value in every branch. It is possible to create synchronous
logic anyway. The following example will show a flip-flop with a load
enable for example.

always @(posedge clk) begin
    if (ce) q <= d;   // Flip flop with enable signal
    //else q <= q;    // This is automatically implied
end

However, if you have a combinational circuit I guess you could see
the construction like this:

always @* begin
    if (ce) q = d;
    // else q = q;   // This is also automatically implied
end

The problem is that q = q would build a combinational loop and the
synthesizer will probably implement this as a latch.



(In reality I guess there might be some simulation issues. I guess
that a simulator is not even going to update q with the value of q
if the else case is not present. Actually, I'm not sure that it will
update q anyway, even if the else case is present as it is just going
to be updated with the same value. A quick experiment indicates that
at least ModelSim doesn't update the variable in this case at least.)

/Andreas

Article: 131497
Subject: Verilog state machines, latches, syntax and a bet!
From: ee_ether <xjjzdv402@sneakemail.com>
Date: Wed, 23 Apr 2008 02:33:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

A colleague and I are having a friendly debate on coding state
machines in Verilog, targeting synthesis for FPGAs.  Comments are very
appreciated.  I am NOT trying to start a holy war here regarding
syntax style (one process vs. two process, etc).

Crux of the matter:  Do you need to define values for outputs of your
state machine in EVERY state, or do you only need to define values for
outputs in states where you want the output to update/change?

Skip to the chase:  At end of message is a Verilog state machine that
does NOT define outputs in all states.  Is this acceptable Verilog or
unacceptable (targeting FPGA)? If not, how would you re-write it?  If
yes, what are the implications?  When you write a SM in Verilog can
you "abbreviate" your output logic and let the synthesizer infer
storage registers for flags assuming you don't define output condition
for all states?

For the code below, the synthesizer (Altera Quartus II v7.1) produces
DFF with MUXes in front ; no latches synthesized.  The register is fed
back its value when NOT in the states where value is updated.  This is
gleaned from using RTL Viewer in Quartus II.  I am curious what ISE
10x would do with this Verilog too...

Colleague:  Verilog/RTL is supposed to provide a reasonable
abstraction, so if you have a state machine where you are updating a
flag (i.e. set the bit/flag in one state, clear it in some other), you
only need to define the output in those states where the bit will be
set or cleared.  The synthesizer will then produce a register and only
update the value(register) in the correct state.  Coding values of ALL
outputs in ALL states would be too tedious and negates advantage of
RTL.

My perspective is : You must define output in every state otherwise
the synthesizer will produce a latch, or some other kind of unwanted
feedback vs. decoding the output based off state registers (and
possibly any other asynchronous inputs).  When I wrote VHDL I would
always define output of SM (mealy or moore) and it would result in
unpleasant to read RTL but synthesized to what I want.  FWIW, I prefer
to combine output statements and next-state logic in one process since
I can follow the logic more easily; if I want a set/clear type flag
then I define SET_FLAG and CLEAR_FLAG signals and they are driven in
every state; a clocked process is used to check SET and CLEAR to
synchronously toggle output (flag).


cpu_lw_*, ackb are all outputs and outputs are not always defined in
all states (hence the debate).

-----------------------------------------------------------------------------------------------------------------------------------------------

//State Machine
always @ (posedge CLK or negedge negreset)
begin
	if(!negreset)
	begin
		ackb <= 1'b1;
		cpu_lw_read <= 1'b0;
		cpu_hw_read <= 1'b0;
		cpu_lw_write <= 1'b0;
		cpu_hw_write <= 1'b0;
		state <= 0;
	end

	else
	begin
	case (state)
	0:
	begin
		if (!csb)
		begin
			case (rd_wr_sel)
			2'b00:	state <= 2;
			2'b01:	state <= 3;
			2'b10:
			begin
				cpu_lw_read <= 1'b1;
				dataout_sel <= 1'b1;
				state <= 4;
			end
			2'b11:
			begin
				cpu_hw_read <= 1'b1;
				dataout_sel <= 1'b1;
				state <= 4;
			end
			endcase
		end
		else
			state <= 0;
	end

	2:
	begin
		if(!dsb)
		begin
			cpu_lw_write <= 1'b1;
			state <= 4;
		end
		else
		begin
			state <= 2;
		end
	end

	3:
	begin
		if(!dsb)
		begin
			cpu_hw_write <= 1'b1;
			state <= 4;
		end
		else
		begin
			state <= 3;
		end
	end

	4:
	begin
		if(ready)
		begin
			ackb <= 1'b0;
			state <= 5;
		end

		else if (csb)
		begin
			cpu_lw_read <= 1'b0;
			cpu_hw_read <= 1'b0;
			cpu_lw_write <= 1'b0;
			cpu_hw_write <= 1'b0;
			state <= 0;
		end

		else
		begin
			state <= 4;
		end

	end

	5:
	begin
		if(csb)
		begin
			ackb <= 1'b1;
			cpu_lw_read <= 1'b0;
			cpu_hw_read <= 1'b0;
			cpu_lw_write <= 1'b0;
			cpu_hw_write <= 1'b0;
			state <= 0;
		end
		else
		begin
			state <= 5;
		end
	end
	endcase
end

Article: 131498
Subject: Re: opb_intc + PowerPC
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 23 Apr 2008 11:55:59 +0100
Links: << >>  << T >>  << A >>
On Tue, 22 Apr 2008 23:05:25 -0700 (PDT), axalay <axalay@gmail.com> wrote:

>
>> Give us a clue ... what error?
>>
>> If the PC ends up at the "unhandled exception" handler address, check that your
>> interrupt vector table is on a 64K boundary. Only the top 16 bits of the
>> interrupt vector table address is actually used in the PPC. So if your table
>> isn't on a boundary, the PPC doesn't vector to where you think it does.
>>
>> - Brian
>
>Hello Brian.
>This project is compile without error.
>When I generate interrupt-my programm is hang.
>I plase breakpoint in all interrupt handler functions, but program is
>not jump at that breakpoints.
>Size of my memory is 64K.

Check the base address of your interrupt vector table.
- Brian


Article: 131499
Subject: FPGA comeback
From: "RealInfo" <therightinfo@yahoo.com>
Date: Wed, 23 Apr 2008 13:11:33 +0200
Links: << >>  << T >>  << A >>
Hi

I want to get into FPGA design after long time I was out of it.

I did some work with ALTERRA long ago .

I mainly did VHDL models for asic .

I want to buy some FPGA board and to do some projects on it with VHDL
to get into that field again .

My question is which board and which FPGA vendor is reccomanded according to 
your
experience.

Thanks in advance
ec. 





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