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On Apr 4, 2:22=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > Maybe you should give us some information on how to proceed if we are stuc= k > with exeed devices with significant value, and want to sell them. Hi Morten, I am an independent distributor, but not in the typical fashion. We inventory in the neighborhood of $100 million of components that have been purchased through reputable OEM's. We work very closely with our contracted accounts that we have SMI and VMI programs in place. I would like to take this offline and discuss a solution that will benefit you and also keep product in proper channels. I sincerely feel that I can help with your excess material and most long lead time components you may need. I look forward to hearing from you and getting a better understanding of your situation. One Altera part I have an immediate order for is a EP2S130F1508C3N. I thank you in advance for taking the time to give me a quick call. Best regards, Jon E. Hansen Strategic Sales Pyramid Technologies Inc. jon@pyramidemail.com www.pyramidtechnologiesinc.com (949)864-7745 Direct (888)288-8913 Ext. 205 (949)636-1416 Cell (949)864-1869 Fax CERTIFIED ISO 9001:2000 PRIVILEGED AND CONFIDENTIAL The information contained in this E-mail and/or attachments may contain legally privileged, or otherwise confidential information intended only for the use of the individual(s) named above. If you, the reader of this message, are not the intended recipient, you are hereby notified that you may not further disseminate, distribute, disclose, copy or forward this message or any of the content herein. If you have received this E-mail in error, please notify the sender immediately and delete the original.Article: 131026
Hello, I need a PCI Express application and I could find a vendor that sells PCI Express cards and add in my design to the FPGA or I could design my own PCI Express card from the ground up. I decided to buy an evaluation card from PLDA and see if I could get things going from their design. I am new to the PCI Express bus protocol and wanted to find a vendor that would make working with PCIe very easy. Does anyone have experience with PLDA? Or, perhaps could recommend another company that is Altera based. I visited Altera's web site and they have a PCIe evaluation card and have thought about using their product because of their excellent support. If anyone would like to share their comments please do. thanks, joeArticle: 131027
jjlindula@hotmail.com <jjlindula@hotmail.com> wrote: >Hello, I need a PCI Express application and I could find a vendor that >sells PCI Express cards and add in my design to the FPGA or I could >design my own PCI Express card from the ground up. I decided to buy an >evaluation card from PLDA and see if I could get things going from >their design. I am new to the PCI Express bus protocol and wanted to >find a vendor that would make working with PCIe very easy. Does anyone >have experience with PLDA? Or, perhaps could recommend another company >that is Altera based. I visited Altera's web site and they have a PCIe >evaluation card and have thought about using their product because of >their excellent support. Check with: enterpoint.co.uk digilent.comArticle: 131028
Hi All This application I am looking at requires 17 tera bytes of multiplication per second. Which in an FPGA means 40K FPGAs. What I want to know is how many 32x32 Mults can you fit into an ASIC today Standard Cell or Custom ASIC. Also what kind of speeds can I get. Bye vipulArticle: 131029
"austin" <austin@xilinx.com> wrote in message news:ftg9a5$p2n1@cnn.xsj.xilinx.com... > At sea level, > > 93% of particles from the cosmic ray shower are neutrons, and 7% are > protons (see JEDEC89A). > > There are 12.9 per square cm, every hour, passing through everything > (for New York City, up to 25X more on mountain tops, 300X at 40K feet, > less at the equator, 10X at the poles...). > > There are also electrons, muons, pions, and a host of more exotic stuff, > but hose either don' matter (do not affect anything), or they are > absorbed quickly, or decay (even a lone neutron decays in 11 minutes!). > Aha, thanks! Now I think I get most of it. It would seem that the cosmic rays, which are charged particles, hurtle into the earth from all directions. They are made of protons mainly, with some alpha and beta particles. The earth's magnetic field means that there are more at the poles than at the equator. The cosmic rays are charged and so interact with the atmosphere a lot, and so very few reach the earth's surface. However, these energetic collisions in the atmosphere produce showers of neutrons. These uncharged particles don't interact with the atmosphere nearly as much as the cosmic rays, so can reach the surface more easily. Ok, here's another question. As the uncharged neutrons don't interact with much, indeed you say they can go through 10 metres of concrete, I can't see why the highly interactive remaining protons aren't the real danger, even though they only comprise 7% of the total, not the 93% neutrons? Maybe none of the original protons reach the surface, but the 7% protons are produced by secondary neutron collisions? Sorry to bombard you with questions! Regards, Syms.Article: 131030
austin wrote: > > So, like I said, that is the dumbest PR I have read. It gets the first > prize for ignorance about soft error effects. Expecting quality in a PR document seems to be the triumph of hope over expereince? These thing start in the depths of a company, we assume largely accurate. Then, that companies Media liason/managers work on it. Then the PR firm 'works' on it and finally the publishing media's editors have a go. Like chinese whispers, any semblence to the original, is pure coincidence! ;) -jgArticle: 131031
Antti wrote: <snip> > > quit simple > > if you want to deliver a BITFILE only and allow the client to > change the software but not the FPGA bit file itself. > > this is VERY simple with Xilinx tools > and IMPOSSIBLE with Altera tools Sounds like simple common sense - what is it that prevents Altera from offering this ? - and why did they miss this obvious flow ? -jgArticle: 131032
Symon wrote: > "austin" <austin@xilinx.com> wrote in message > news:ftg25m$p2m2@cnn.xsj.xilinx.com... > >>Intel has also been working very quietly on this, with much less press. >> > > Hi Austin, > I wondered what were your thoughts on their patent where "The cosmic ray > detector [built into the device] is therefore designed to spot when rays > have caused interference and then tell the chip to repeat the command." ? I > guess in an FPGA it could trigger a readback to ensure the device was still > correctly configured and/or issue a user logic reset. > Cheers, Syms. > > Boy, I saw that text, too, and really wondered about how reliable such a procedure would be. If the state of flip-flops or dynamic memories are altered, repeating the previous instruction operation would be worthless. There is SO much more area in high-end CPUs devoted to memory and much less to logic functions, I would expect memory corruption to be the most probable fault. JonArticle: 131033
austin wrote: > Symon, > > Well, that employee should be fired: that is the stupidest thing I have > ever read. > > It isn't even science -- detecting neutrons! Pure BS! A neutron is an > uncharged particle, that goes through 10 meters of concrete before it > gets stopped. Detecting one is just......stupid.....idiotic..... > > (breathe in, breathe out.) > Right, having worked with a nutron detector array, detecting them is REALLY hard, and not something easily done on a chip. However, most neutrons pass through chips easily with no interaction, and so can be ignored. What you have to detect is if the neutron was CAPTURED, and deposited energy in (or very near) the active circuitry. That will release some energy (could be charged particles, could be Gamma rays) that could affect the active circuitry. The gammas could be detected from a distance, but they can be quite directional and local, so detecting them could be tough, too. > Their PR folks are probably going nuts on this one! > > Was that April 1 dateline? > Really! Just detecting a neutron or Alpha hit could be difficult, although detecting a cosmic ray shower is a lot easier, as the shower of charged particles greatly increases your probability of detection on a small detector device (probably just a diode). But, then, the REAL problem is how to CORRECT any malfunction that may have ocurred. Reducing the probability of corruption, as Austin descibes Xilinx has done, seems the most reliable and provable scheme. Proving you can correct corruption from a hit anywhere on a chip, while running ANY program, at any time, seems like fantasy. JonArticle: 131034
"VIPS" <thevipulsinha@gmail.com> wrote in message news:37d9abbf-eb08-490b-b176-40c4c9b07a26@k13g2000hse.googlegroups.com... > Hi All > > This application I am looking at requires 17 tera bytes of > multiplication per second. Which in an FPGA means 40K FPGAs. What I > want to know is how many 32x32 Mults can you fit into an ASIC today > Standard Cell or Custom ASIC. Also what kind of speeds can I get. > Assuming that you mean 17 10^12 multipliers? With a 90nm process you can get quite a few in a standard cell ASIC. But without further explanation, I would say that speed per multiplier will be dreadfull: you won't be able to get that much data on and off a single chip (I/O limitations). So you may stick to an FPGA as well (saves you time and risk, read on). As for your FPGA count: you need 3 DSP48 blocks on a Xilinx device or 1 32x32 multiplier on an Altera device. The DSP48s go up to 550MHz, for the Altera part, I don't know. But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there are more than 100 of these in the larger V5 SX(T) devices (too lasy to look up the exact number), you will end up with quite a bit less than 1000 FPGAs. Still, you need to look at your I/O, power, algorithm, costs, etc. to get the whole picture. Regards, Alvin.Article: 131035
Symon wrote: > > Ok, here's another question. As the uncharged neutrons don't interact with > much, indeed you say they can go through 10 metres of concrete, I can't see > why the highly interactive remaining protons aren't the real danger, even > though they only comprise 7% of the total, not the 93% neutrons? Maybe none > of the original protons reach the surface, but the 7% protons are produced > by secondary neutron collisions? The protons interact VERY strongly, due to the charge. As most electronics is housed in something, the housing usually stops the protons, although there will be Gamma radiation when they hit, and that can penetrate the housing. If you put a bare photodiode outside on a dark night and reverse-biased it, you could pick up these interactions easily with an oscilloscope. With a little digging into the physics, you could discriminate alpha hits from protons, etc. Of course, cosmic ray showers deliver so much "stuff" that you'd just see big pulses without being able to pick out the fundamental particles. Oh, one other aspect is "stopping distance". Very energetic charged particles zing through stuff with minimal energy deposited into the material, until enough energy has been shed, then they interact and stop suddenly. So, the very high energy primary particles are not much trouble, it is when they either lose energy by travelling through something or create secondary particles that the energy is low enough to create ions. So, the protons are not likely to ever make it into the silicon directly. Secondary Alphas and lots of Gammas will be bouncing around, and those could deliver energy to the chip. JonArticle: 131036
Alvin Andries wrote: > But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there are > more than 100 of these in the larger V5 SX(T) devices (too lasy to look up > the exact number), you will end up with quite a bit less than 1000 FPGAs. Approx 1000 in the SX240, so approx 100 FPGAs. A big project!Article: 131037
"Tim (one of many)" <tim@nooospam.roockyloogic.com> wrote in message news:ftghqh$31k$1$8302bc10@news.demon.co.uk... > Alvin Andries wrote: >> But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since there >> are >> more than 100 of these in the larger V5 SX(T) devices (too lasy to look >> up >> the exact number), you will end up with quite a bit less than 1000 FPGAs. > > Approx 1000 in the SX240, so approx 100 FPGAs. A big project! > Perhaps use the money it costs for all those FPGAs to pay off someone who already knows the encryption key? Just a thought, Syms.Article: 131038
Symon, The cosmic rays are ions: iron, gold, xenon, carbon, basically anything and everything. Yes, there are lots of protons, but they do not have enough energy to cause problems. More light ions (like carbon), fewer heavy ions (like gold). But, iron, with too few electrons, traveling at 90% the speed of light, now there is a particle! When one of these "heavy ions" strike the upper atmosphere, say a nitrogen molecule, all hell breaks loose and you get all sorts of products (Even CERN has nothing on a cosmic ray--high energy physics used mountain top sites before the cyclotron!). Since neutrons have no charge, and go right through most things, (as most mass is empty space), the neutrons predominate at the earth's surface. Beam neutrons at a block of iron, or aluminum or copper, and you will get radioactive iron, aluminum, or copper (excess neutrons will eventually be released if they have created an unstable isotope). This is why lead on the surface is more radioactive that lead at the bottom of the sea. The ions got directed by the earth's magnetic field, but once the ion strikes, the neutrons are unaffected by the fields. The direction is predominately "up" as the flux falls off away from "up" (towards the sky) as the neutrons are absorbed by the atmosphere at oblique angles. No neutrons come from "down" unless you are standing on lead, uranium, or in the basement in Minnesota (Radon). The neutron hits the silicon lattice. The silicon "spallates" (spilts the atom) and releases an alpha particle ( a helium atom, minus the electrons: two protons, two neutrons). The alpha particle has charge, and it upsets the source drain region (due to deposited charge, actually leaves a trail of 'holes' and electrons which quickly recombine, in less than 30 ps). The neutron may also just "ping" the silicon lattice, and cause the silicon dioxide molecule to be dislocated from the lattice, or just vibrate. In either case, charge is also released. A good history lesson (and some physics): http://www.research.ibm.com/journal/rd40-1.html specifically: http://www.research.ibm.com/journal/rd/401/tang.html If you can stomach the physics.... AustinArticle: 131039
Antti wrote: > Hi > > I have been think and part time working towards a goal to make useable > and useful serialized processor. The idea is that it should be > > 1) VERY small when implemented in any modern FPGA (less 25% of > smallest device, 1 BRAM) > 2) be supported by high level compiler (C ?) > 3) execute code in-place from either serial flash (Winbond quad speed > SPI memory delivers 320 mbit/s!) or from file on sd-card Re Quad Serial memory devices, and execute in place : I see SST have just released a Quad device as well. $1.16/10K for 16MBit Good news, and bad news : Good news: 80MHz nibble rate. They also added 8 & 16 bit address modes, to the default 24 bit. Bad News: These short-jump modes _are_ signed relative, BUT they do NOT cross page boundaries. (ie Just like the 8048...) So, the idea falls short of being usable in relocatable code. Pity, as a memory-opcode jump is a good way to save some bandwidth Why make something signed relative, but then have it page-wrap ? - was this a bug, maybe they intended it to work properly, but found an oops, and changed the data to match the silicon ? -jgArticle: 131040
Antti <Antti.Lukats@googlemail.com> writes: > good god... how can it be that you dont understand... I do understand the difference between the two. I've used both tools. > the ELF to BIT merge is much simpler than the cdb_mif update I know that it's simpler. But when you have the RTL source there is no practical difference. At least it's not for me. It only takes a couple seconds to run the merge in each case. But if you have lost the source (like the OP) or will not give some 3rd party the Quartus project file then quartus_cdb will not help you. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 131041
On Apr 8, 5:33 pm, Petter Gustad <newsmailco...@gustad.com> wrote: > I know that it's simpler. But when you have the RTL source there is no > practical difference. At least it's not for me. It only takes a couple > seconds to run the merge in each case. > > But if you have lost the source (like the OP) or will not give some > 3rd party the Quartus project file then quartus_cdb will not help you. *If* you have RTL source, and *if* you have it in the right place. I've tried to explain this to Altera reps several times, and they just don't get it that their tool is much less capable than Xilinx's in this area. It's effectively like saying that you have to have design documents for your entire PC on hand if you want to install an updated BIOS... There are some hints out there that it may not be too hard to reverse engineerArticle: 131042
Tim (one of many) wrote: > Alvin Andries wrote: > >> But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since >> there are >> more than 100 of these in the larger V5 SX(T) devices (too lasy to >> look up >> the exact number), you will end up with quite a bit less than 1000 FPGAs. > > > Approx 1000 in the SX240, so approx 100 FPGAs. A big project! > But not totally outrageous. I've recently completed a beamforming antenna design for installation in an aircraft that uses one Virtex 4SX55 for each antenna element. There are 240 antenna elements, thus 240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the FPGA is a 10 channel tuner, downconverter, and beam steering.Article: 131043
Jim Granville <no.spam@designtools.maps.co.nz> wrote: > Antti wrote: > <snip> > > > > quit simple > > > > if you want to deliver a BITFILE only and allow the client to > > change the software but not the FPGA bit file itself. > > > > this is VERY simple with Xilinx tools > > and IMPOSSIBLE with Altera tools > Sounds like simple common sense - what is it that prevents > Altera from offering this ? - and why did they miss > this obvious flow ? B.t.w two questions: - can anybody give an example commandline for a real world DATA2MEM example? - can any FPGA family BRAM be written by JTAG directly without upsetting the rest of the FPGA configuration? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 131044
Ray Andraka <ray@andraka.com> wrote: > Tim (one of many) wrote: > > Alvin Andries wrote: > > > >> But: 3 * (17 10^12 / 550 10^6) = +/- 92800 DSP48 resources. Since > >> there are > >> more than 100 of these in the larger V5 SX(T) devices (too lasy to > >> look up > >> the exact number), you will end up with quite a bit less than 1000 FPGAs. > > > > > > Approx 1000 in the SX240, so approx 100 FPGAs. A big project! > > > But not totally outrageous. I've recently completed a beamforming > antenna design for installation in an aircraft that uses one Virtex > 4SX55 for each antenna element. There are 240 antenna elements, thus > 240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the > FPGA is a 10 channel tuner, downconverter, and beam steering. Aren't you supposed to shoot everybody you tell about the project? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 131045
Hello, I have a project where i have to implement a ring oscillator (3 not gates) using an altera DE2. But i am confronted to several problems. The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that quartus has optmised 'a little too much' since i want to see the delay. Is there any way to disable the optimisation ? I have read and show on option 'wire keep_wire', but i did not manage to make it work ... Or maybe it is another problem. Thanks for your time, and helpArticle: 131046
On Apr 8, 3:11=A0pm, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > Ray Andraka <r...@andraka.com> wrote: > > Tim (one of many) wrote: > > > Alvin Andries wrote: > > > >> But: 3 * (17 10^12 / 550 10^6) =3D +/- 92800 DSP48 resources. Since > > >> there are > > >> more than 100 of these in the larger V5 SX(T) devices (too lasy to > > >> look up > > >> the exact number), you will end up with quite a bit less than 1000 FP= GAs. > > > > Approx 1000 in the SX240, so approx 100 FPGAs. A big project! > > > But not totally outrageous. =A0I've recently completed a beamforming > > antenna design for installation in an aircraft that uses one Virtex > > 4SX55 for each antenna element. =A0There are 240 antenna elements, thus > > 240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the > > FPGA is a 10 channel tuner, downconverter, and beam steering. > > Aren't you supposed to shoot everybody you tell about the project? > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-darm= stadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Slightly off-topic: Here is a civilian research application at CERN, where 120 Virtex 4FX devices "digest" and pre-process a thousand data streams of 2.5 Gbps each. I was peripherally involved, and I helped write the press release... http://biz.yahoo.com/prnews/080404/aqf063.html?.v=3D35 I even got to walk around in the tunnel. Peter Alfke, XilinxArticle: 131047
Franck Y <franck110@gmail.com> wrote: > Hello, > I have a project where i have to implement a ring oscillator (3 not > gates) using an altera DE2. > But i am confronted to several problems. > The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that > quartus has optmised 'a little too much' since i want to see the > delay. > Is there any way to disable the optimisation ? I have read and show on > option 'wire keep_wire', but i did not manage to make it work ... Or > maybe it is another problem. What "voltage p-p" is 128.2 mV? Is this something you observe at an output? What frequency? What output standard? Aren't you overdriving the outputs by far? Shouldn't you run with a much longer chain? Don't the gate in the short chain get overloaded? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 131048
Uwe Bonnes wrote: > Ray Andraka <ray@andraka.com> wrote: >>But not totally outrageous. I've recently completed a beamforming >>antenna design for installation in an aircraft that uses one Virtex >>4SX55 for each antenna element. There are 240 antenna elements, thus >>240 V4SX55's in the system. Each Antenna is sampled at 500 MHz, and the >>FPGA is a 10 channel tuner, downconverter, and beam steering. > > > Aren't you supposed to shoot everybody you tell about the project? Why ? I'm sure this is for a crop-duster, right ? ;) -jgArticle: 131049
Franck Y wrote: > Hello, > > I have a project where i have to implement a ring oscillator (3 not > gates) using an altera DE2. > But i am confronted to several problems. > The voltage p-p is 128.2 mV and the Vavg is 3.308 V which seems that > quartus has optmised 'a little too much' since i want to see the > delay. > > Is there any way to disable the optimisation ? I have read and show on > option 'wire keep_wire', but i did not manage to make it work ... Or > maybe it is another problem. > > Thanks for your time, and help Try a longer chain, 3 seems very short, unless they are pin-buffers, and you should ideally use alternate NOT and NOR gates with a reset drive, in a ring oscillator. -jg
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