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I have an idea simular or not to your mind..(but I still thinking....hope you are now starting ..your project). my project is that FILE COMPRESSION (zip or other) read files from SD card, then compress it, and write a new zipped file back to SD card. it will not include the PC to do it. On Jun 11, 9:50=A0am, Charles Xavier <skelo...@gmail.com> wrote: > As you all know, downloading files from usenet leaves you with two > sets of files.. The rar files from what you're downloading and the > par2 files for incomplete file repair. > > If anyone has attempted to download anything in the 8GB range, you'll > find that well.. if you're missing enough parts of the file, the par2 > recovery can be a painful, painful process taking up to three hours in > some cases. > > I'm sick of it. > > So, here's the idea. Use a FPGA to do the reed-solomon decoding to > accelerate the PAR2 repair/recovery process. The system should utilize > a USB connection to pipe data directly from the disk to the FPGA that > will do the offboard processing of the data. The data transfer should > be controlled by an application on the computer. > > Second Problem.. > > The XBOX 360 doesn't play x.264 and all the good movies are in x.264. > Converting from x.264 to h.264 could be done offboard on an FPGA > because it takes for-ever to complete on my system (8 hours). This > should have the same premise as the previous issue, minus using a x. > 264 decoding core and possibly directly converting it to h.264 or > doing a decompression-recompression.. > > SPECS: The development system i'm using is the XILINX ML-505 board > with the Virtex 5 chip. This is a open-source project being done for > fun and learning btw. > > Suggestions / Comments / Complaints?Article: 133051
On Jun 15, 5:33 pm, "arko" <a...@winnet.com> wrote: > I've seen messages from regular posters saying that they > run Modelsim/XE Starter Edition in Linux. This evidently > works for the node-locked 'disk-id' based licenses. > > But if you have a full license, on a USB-dongle or other > physical key, will Modelsim/XE still work under WINE? Will since WINE doesn't support the Windows USB interface yet, I would say no to that. If the device is a parallel port, it's possible that it could be used over the parallel port, so long as it doesn't require ECP, since that requires root privileges and running WINE as root is a big no-no. -- MikeArticle: 133052
Charles Xavier wrote: > Responding to this type of feedback is the real waste of time. "Suggestions / Comments / Complaints?"Article: 133053
RealInfo wrote: > It comes with the WARP cpld design software for cyperess cplds . Future Electronics CY3120R62CDArticle: 133054
fl wrote: > Hi, > I want to use Xilinx DA FIR logic core (Ver 9.0) to generate many FIR > blocks. The wordwidth of Dout is defined as the following: > > > DOUT[R-1:0]: > FILTER OUTPUT SAMPLE R-bit-wide output sample bus for the FIR, > half-band and interpolated filters. R depends on the filter parameters > (data > precision, coefficient precision, number of taps and coefficient > optimization > selection) and is always supplied as a full-precision output port to > avoid any > potential for overflow. > > > The width of DOUT(R) is out of my control for the many different FIR > coefficient sets. > > In my project, I would like to have the same output wordwidth of the > many DA FIR blocks. Does anyone have some good idea to reach that > goal? Thanks a lot. Typically, because of multiply-accumulation, you end up with more internal precision than you want to output from the filter. So you just need to take these outputs and round or truncate them to the wordwidth you wish. Incidentally, I'd question the use of distributed arithmetic. It doesn't make much sense in the newer architectures. I'd use the DSP48s and the fir compiler instead of the DA fir. -KevinArticle: 133055
On Jun 16, 10:49 am, Mike Treseler <mike_trese...@comcast.net> wrote: > RealInfo wrote: > > It comes with the WARP cpld design software for cyperess cplds . > > Future Electronics CY3120R62CD Mike: The Future Electronics web site reports that part # as non-existant. There was a 6.3 release (CY3120R63), but that search turns up empty also. To the OP: Cypress no longer makes CPLDs. Unless you are supporting an old design (like the CPLD on the FX2 Eval card :) the Warp package is only useful for SPLDs. Warp runs "just fine" on Windows 2000, it should work on XP as well. It has a good uninstall, so just go ahead and try it. G.Article: 133056
1>is TXCOMSTART/TXCMOTYPE useful? My SATA controller includes OOB generate/detect circuit.During simulation,The V5 SATA GTP works well even if TXCOMSTART/TXCMOTYPE tied ground.I only input TILE0_TXDATA0_IN[15:0],TILE0_TXCHARISK0_IN[1:0] two tx signals .It can finish OOB negotiation with SATA device BFM.But,in real ML555 board, does it should be tied ground or connect logic? 2>TX buffer or TX phase alignment ? Inside ISE10.1.1,the default SATA GTP configuration is TX buffer,no previous TX phase alignment.which better? 3>why not cominit sequence response from SATA DISK at ML555? after sending COMRESET sequence, why not COMINIT sequence response from SATA DISK? Btw,the simulation result is ok.And that,i cann't detect any valid signal from tile0_rxlossofsync0_i[0].Article: 133057
Bytheway How good is that book, is it a good way to learn VHDL for programmable logic in general ? Thanks EC "ghelbig" <ghelbig@lycos.com> ??? ??????:493281cd-f7a2-4139-a6d2-981b086dfb43@s21g2000prm.googlegroups.com... > On Jun 16, 10:49 am, Mike Treseler <mike_trese...@comcast.net> wrote: >> RealInfo wrote: >> > It comes with the WARP cpld design software for cyperess cplds . >> >> Future Electronics CY3120R62CD > > Mike: > > The Future Electronics web site reports that part # as non-existant. > There was a 6.3 release (CY3120R63), but that search turns up empty > also. > > To the OP: > > Cypress no longer makes CPLDs. Unless you are supporting an old > design (like the CPLD on the FX2 Eval card :) the Warp package is only > useful for SPLDs. > > Warp runs "just fine" on Windows 2000, it should work on XP as well. > It has a good uninstall, so just go ahead and try it. > > G.Article: 133058
I am using a XAUI core in my design for a PCIe board with a Xilinx Virtex - 5 LX110t FPGA. The board specifications require the GTP dual tiles of XAUI to be constrained to locations X0Y0 and X0Y7 which are far from each other on the FPGA. Due to this, the design does not meet timing. The user-guide for the rocketio transceivers suggests modification of channel bonding attributes of the GTP Dual tiles to meet timing. To try this out, the default channel bonding level for the 4 GTP tiles (2 GTP duals) was changed to 3,2,1,0 with 3 as the master tile. This design works fine in simulation, but does not meet timing. The timing error as seen on timing analyzer was due to the rxchanbondo signal. The channel bond level was further changed to 5,4,1,0 with 5 as the master. Two pipeline stages were added for the rxchanbondo signal (between the tiles 4 and 1). This design meets timing, but does not work in simulation. All these changes were made to the rocketio_wrapper.v file in the XAUI core generated using coregen. I feel that the wiring between the tiles in the rocketio_wrapper.v file needs to be modified to hook-up all the signals that may have been disturbed due to the addition of the two pipeline stages. Unfortunately I do not have a lot of experience working with rocketio transceivers and their channel bonding attributes which puts me in a state of bother while analyzing what signals need to be modified/ reassigned/patched between the gtp tiles. I would appreciate any suggestions from anybody who has had experience working with XAUI, rocketio's and their channel bonding attributes. Thanks for your help in advanceArticle: 133059
explore wrote: > I am using a XAUI core in my design for a PCIe board with a Xilinx > Virtex - 5 LX110t FPGA. The board specifications require the GTP dual > tiles of XAUI to be constrained to locations X0Y0 and X0Y7 which are > far from each other on the FPGA. Due to this, the design does not meet > timing. The user-guide for the rocketio transceivers suggests > modification of channel bonding attributes of the GTP Dual tiles to > meet timing. To try this out, the default channel bonding level for > the 4 GTP tiles (2 GTP duals) was changed to 3,2,1,0 with 3 as the > master tile. This design works fine in simulation, but does not meet > timing. The timing error as seen on timing analyzer was due to the > rxchanbondo signal. > > The channel bond level was further changed to 5,4,1,0 with 5 as the > master. Two pipeline stages were added for the rxchanbondo signal > (between the tiles 4 and 1). This design meets timing, but does not > work in simulation. All these changes were made to the > rocketio_wrapper.v file in the XAUI core generated using coregen. > > I feel that the wiring between the tiles in the rocketio_wrapper.v > file needs to be modified to hook-up all the signals that may have > been disturbed due to the addition of the two pipeline stages. > Unfortunately I do not have a lot of experience working with rocketio > transceivers and their channel bonding attributes which puts me in a > state of bother while analyzing what signals need to be modified/ > reassigned/patched between the gtp tiles. > > I would appreciate any suggestions from anybody who has had experience > working with XAUI, rocketio's and their channel bonding attributes. > > Thanks for your help in advance Why are the GTP_DUAL sites constrained to X0Y0 and X0Y7, these are the worst possible locations to choose from. If the board hasn't gone through layout yet, can you change these to be adjacent locations? Ed McGettigan -- Xilinx Inc.Article: 133060
Thanks for your response. Unfortunately the board was not designed by us. This is an AVNET PCIe board that we happened to purchase a while ago. We hadn't put in the XAUI core until recently. Now we are forced to use the same GTP locations specified in the AVNET user guide. We were suggested by Xilinx support that we can use the flexibility of channel bonding available with rocketio's to try and make timing and this is the reason we are still hopeful of finding a solution to it. They also told us that some people were successful in making changes to the channel bonding in AURORA cores and the design to meet timing when they had a similar problem. As I mentioned earlier, the design meets timing when the tiles have channel bonding levels of 5,4,1,0 with 2 pipeline stages for rxchanbond signals, but I do not get to see it work in simulation. Would like your suggestion/ inputs on this. Thanks for your time once again. --Chethan On Jun 16, 7:31=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > explore wrote: > > I am using a XAUI core in my design for a PCIe board with a Xilinx > > Virtex - 5 LX110t FPGA. The board specifications require the GTP dual > > tiles of XAUI to be constrained to locations X0Y0 and X0Y7 which are > > far from each other on the FPGA. Due to this, the design does not meet > > timing. The user-guide for the rocketio transceivers suggests > > modification of channel bonding attributes of the GTP Dual tiles to > > meet timing. To try this out, the default channel bonding level for > > the 4 GTP tiles (2 GTP duals) was changed to 3,2,1,0 with 3 as the > > master tile. This design works fine in simulation, but does not meet > > timing. The timing error as seen on timing analyzer was due to the > > rxchanbondo signal. > > > The channel bond level was further changed to 5,4,1,0 with 5 as the > > master. Two pipeline stages were added for the rxchanbondo signal > > (between the tiles 4 and 1). This design meets timing, but does not > > work in simulation. All these changes were made to the > > rocketio_wrapper.v file in the XAUI core generated using coregen. > > > I feel that the wiring between the tiles in the rocketio_wrapper.v > > file needs to be modified to hook-up all the signals that may have > > been disturbed due to the addition of the two pipeline stages. > > Unfortunately I do not have a lot of experience working with rocketio > > transceivers and their channel bonding attributes which puts me in a > > state of bother while analyzing what signals need to be modified/ > > reassigned/patched between the gtp tiles. > > > I would appreciate any suggestions from anybody who has had experience > > working with XAUI, rocketio's and their channel bonding attributes. > > > Thanks for your help in advance > > Why are the GTP_DUAL sites constrained to X0Y0 and X0Y7, these are the > worst possible locations to choose from. =A0If the board hasn't gone > through layout yet, can you change these to be adjacent locations? > > Ed McGettigan > -- > Xilinx Inc.- Hide quoted text - > > - Show quoted text -Article: 133061
explore wrote: > Thanks for your response. Unfortunately the board was not designed > by us. This is an AVNET PCIe board that we happened to purchase a > while ago. We hadn't put in the XAUI core until recently. Now we are > forced to use the same GTP locations specified in the AVNET user > guide. We were suggested by Xilinx support that we can use the > flexibility of channel bonding available with rocketio's to try and > make timing and this is the reason we are still hopeful of finding a > solution to it. They also told us that some people were successful in > making changes to the channel bonding in AURORA cores and the design > to meet timing when they had a similar problem. As I mentioned > earlier, the design meets timing when the tiles have channel bonding > levels of 5,4,1,0 with 2 pipeline stages for rxchanbond signals, but I > do not get to see it work in simulation. Would like your suggestion/ > inputs on this. > > Thanks for your time once again. > > --Chethan > > > On Jun 16, 7:31 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: >> explore wrote: >>> I am using a XAUI core in my design for a PCIe board with a Xilinx >>> Virtex - 5 LX110t FPGA. The board specifications require the GTP dual >>> tiles of XAUI to be constrained to locations X0Y0 and X0Y7 which are >>> far from each other on the FPGA. Due to this, the design does not meet >>> timing. The user-guide for the rocketio transceivers suggests >>> modification of channel bonding attributes of the GTP Dual tiles to >>> meet timing. To try this out, the default channel bonding level for >>> the 4 GTP tiles (2 GTP duals) was changed to 3,2,1,0 with 3 as the >>> master tile. This design works fine in simulation, but does not meet >>> timing. The timing error as seen on timing analyzer was due to the >>> rxchanbondo signal. >>> The channel bond level was further changed to 5,4,1,0 with 5 as the >>> master. Two pipeline stages were added for the rxchanbondo signal >>> (between the tiles 4 and 1). This design meets timing, but does not >>> work in simulation. All these changes were made to the >>> rocketio_wrapper.v file in the XAUI core generated using coregen. >>> I feel that the wiring between the tiles in the rocketio_wrapper.v >>> file needs to be modified to hook-up all the signals that may have >>> been disturbed due to the addition of the two pipeline stages. >>> Unfortunately I do not have a lot of experience working with rocketio >>> transceivers and their channel bonding attributes which puts me in a >>> state of bother while analyzing what signals need to be modified/ >>> reassigned/patched between the gtp tiles. >>> I would appreciate any suggestions from anybody who has had experience >>> working with XAUI, rocketio's and their channel bonding attributes. >>> Thanks for your help in advance >> Why are the GTP_DUAL sites constrained to X0Y0 and X0Y7, these are the >> worst possible locations to choose from. If the board hasn't gone >> through layout yet, can you change these to be adjacent locations? >> >> Ed McGettigan >> -- >> Xilinx Inc. > Ok, I understand now. I hope that when you take the design forward to your own platform that you clean this up and don't follow this design. I was not familiar with this particular board, but I was able to determine that you are using the Avnet AES-XLX-V5LXT-PCIE110-G board and after getting the schematics it does show that the XAUI/CX4 interface that you are trying to use is split across the device using X0Y0 and X0Y7. There are a couple of issues with this board design, but I will address your channel bond timing issue first. You can make this timing work, but you have to insert additional registers in the RXCHBONDO[2:0] to RXCHBONDI[2:0] path. These ports use the faster 10-bit RXUSRCLK clock that will be running at at 312.5MHz in your application. My guess is that you will need at least 2 register stages to get across the device at this frequency and you made need three as the clock-to-out on RXCHBONDO and the setup into RXCHBONDI are long with respect to a 312.5 MHz clock. You should place absolute placement LOC attributes on these registers to ensure that MAP doesn't pack the stages into the same slice and you get the spread that you need. After you have the timing working you will then need to set the correct CHAN_BOND_LEVEL value for each lane based on the number of stages that you used. This is describe in the GTP User Guide (UG196) Configurable Channel Bonding section. In addition to channel bonding issue you also have two other issues with this board that impact your XAUI design. 1) You need to use two REFCLK sources, one for each GTP_DUAL. The board supports it, but you will likely need to update the XAUI source to add the second set of inputs to one of the GTP_DUALs. 2) The P/N nets are swapped for some of the pairs. The schematic indicates that you need to set the TXPOLARITY0 and RXPOLARITY0 on X0Y7 and TXPOLARITY1 on X0Y0 to 1 (default is 0). Good luck. Ed McGettigan -- Xilinx Inc.Article: 133062
Hi all, We are using Rocket IO on Virtex 2 pro and we are facing some problems. 1- What is the user frequency clock ? TXUSRCLK or TXUSRCLK2 ? We want to use in half mode rate, REFCLK = 75 MHz, TXUSRCLK = 37,5 MHz and TXUSERCLK2=75 MHz. 2- The output of the RIO seems to be TXUSERCLK (RECVRXCLK). It is working in parallel bypass mode but not in serial bypass. So, if the user clock is TXUSRCLK2 then we can only send 1.7 Gbps at the input od the RIO and have 3.2 GHz in serial link. We bypass the 8B/10B encoder/decoder and we don't disable the Comma alignment. THXArticle: 133063
Hai, I am a final year M.tech student.Its my final sem project.. regards, faza On Jun 16, 8:24=A0pm, "Mike Lewis" <some...@micrsoft.com> wrote: > "faza" <fazulu.v...@gmail.com> wrote in message > > news:53fad5d8-9989-4089-82be-cf57588c9b34@u36g2000prf.googlegroups.com... > Hai, > > I am facing problem while synthesis of Fixed point data type.I cannot > change the synthesis tool.Is there any method which can convert fixed > point to integer =A0before hand and perform computation and convert back > to fixed point without affecting the precision.? > > In my FIR filter design i will sample the input and perform > computation,produce result with control signal and then i will sample > the next data..ultimately i will waiting for the o/p control signal > before sampling the data..now my question is how this logic will be > implemented as hardware..do i need to store my input samples in ROM or > i should depend on the software to do this? > > pls clarify. > > regards, > faz > > Dude .. give us some background .. > > Are you a student? What year? Is this a project or an assignment? > > MikeArticle: 133064
hello. i use EDK 9.1, and have a XUP Virtex 2 pro development board with me, device: XCV2P30. In Base System Builder, in the boards drop down meni, i donot find this board listed. what do i do? further, where do i download it from? Please reply asap, as i have to start working with it immediately.... thanks in advance vikramArticle: 133065
Hi,
I had the book and the WARP-Compiler running years ago.
It was nice then, because it was the only vhdl synthesis system
available affordable for students etc. at that time.
What annoyed me even then, was that the synthesis was very restrictive
about the coding style. So code portability was almost impossible.
Also, for learning VHDL there are better tools available now for free.
(e.g. Xilinx Webpack and Modelsim Starter Versions)
There are a lot of good books for VHDL available. Search this group for
infos. The Cypress book is just not up to date anymore.
Have a nice synthesis
Eilert
RealInfo schrieb:
> Bytheway
> How good is that book, is it a good way to learn VHDL for programmable logic
> in general ?
>
> Thanks
> EC
>
>
> "ghelbig" <ghelbig@lycos.com> ???
> ??????:493281cd-f7a2-4139-a6d2-981b086dfb43@s21g2000prm.googlegroups.com...
>> On Jun 16, 10:49 am, Mike Treseler <mike_trese...@comcast.net> wrote:
>>> RealInfo wrote:
>>>> It comes with the WARP cpld design software for cyperess cplds .
>>> Future Electronics CY3120R62CD
>> Mike:
>>
>> The Future Electronics web site reports that part # as non-existant.
>> There was a 6.3 release (CY3120R63), but that search turns up empty
>> also.
>>
>> To the OP:
>>
>> Cypress no longer makes CPLDs. Unless you are supporting an old
>> design (like the CPLD on the FX2 Eval card :) the Warp package is only
>> useful for SPLDs.
>>
>> Warp runs "just fine" on Windows 2000, it should work on XP as well.
>> It has a good uninstall, so just go ahead and try it.
>>
>> G.
>
>
Article: 133066faza wrote: > I am facing problem while synthesis of Fixed point data type.I cannot > change the synthesis tool.Is there any method which can convert fixed > point to integer before hand and perform computation and convert back > to fixed point without affecting the precision.? I presume you mean fixed point with the binary point not immediately to the right of the least significant bit, sometimes called scaled fixed point. Adding such numbers with the same scale factor is the same as adding integers. Multiplying follows the rules you learned in 3rd grade, the digits (bits) after the binary point of the product is the sum of the bits after the binary points of the to operands. Multiply should give you a double length product, select the appropriate bits. (snip) -- glenArticle: 133067
Hi Rob, surely higher clocks speed up everything, but since you are working at the physical limit, maybe it is also useful to rethink your problem. You need a lot of operations done in a specified time slice. The higher your clock the more operations can be done, true. But there are also other methods to increase the number of operations within a defined time slice. How about massive parallel operation? Is it possible to rearrange your algorithms to make better use of the ressources? Can you implement additional operation elements working in parallel? May it be possible to use more than one FPGA? How about your Datarates at the inputs and output. Are they also in the multi gigabit range? Or significantly lower? In the second case, have you considered using a DSP clocked at some GHz. (Combined with the FPGA maybe...) And if the problem is more in the area of signal detection/generation than algorithmic. Have you ever thought about using multiple phase shifted clocks? Four 500 MHz clocks at 0-90-180-270 degrees give you a resulting 2GHz resolution. Needs some cunning design but can help a lot. Have a nice synthesis Eilert Rob Gaddi schrieb: > Hey all -- > > So I've got a design, the very vaguest outlines of which are beginning > to gel. But one of the things that's becoming apparent is that it would > benefit from real clock rates somewhere between the obscene and the > unthinkable. > > Throwing lots of money at the problem seems to get me to 500 MHz, yet > more can get me up to 550 MHz, but I could get a lot of other things to > run much more smoothly if I could get clock rates out into the 650 MHz > ballpark. That's for BRAMS and multipliers/DSP slices, not just the flops. > > So I get to thinking about how the clock rate specs get figured out, and > how they have to accomodate the slow silicon at the maximum operating > temperatures. And that thought leads around in circles for a while, and > ultimately leads to the following appalling question: > > Anyone know anything about using Peltier modules, refrigerant pumping > systems, or the like, to cheat up the speed of an FPGA? Is it even > feasible to try to get a 20-30% overclock just from the joys of lower > temperatures? Or do I just suck it up and deal with the rated clock > speeds? >Article: 133068
hello as i mentioned earlier, i'm a beginner with fpgas. in fact, this is the first time i'm configuring an fpga.... I am using the XUP Virtex2Pro Development board, device : XCV2P30, with EDK 9.1i I also have the Platform USB 2 cable (A-B) which i came to know, can be used to configure the fpga.... I wanted to know the procedure to configure the fpga... using EDK? or iMPACT? Please help out asap.... Thanks in advance... VikramArticle: 133069
Dear all, I am working on a project where I need to store datas on the Flash memory of my FPGA board. I would like to do it with the USB interface but it is much more complicated than I could thought. I don't have any experience on USB management but in my "dream" I would like to be able to connect an USB flash drive to the FPGA, and be able to then copy 2 files on the usb flash drive to the flash memory of the FPGA Board. I have begin to read about the Cypress CY7C68013A-100AC which is the controller provided with my FPGA board, but I could not really understand how I can make my plan working. Since my flash memory is interface by the FPGA, I assume I have to code something in the FPGA. But in an other hand, the management of the USB seems to be done by configurating the 8051 inside the controller. In fact, I don't really know how to interface the USB to the flash memory of the Board. I also assume the "file management" of the Flash USB drive should be manage by the USB controller, but how command it by the FPGA ... Here are my problems, and you can maybe see that I am a little bit lost. If some people could help me in this, I would be very grateful :) XArticle: 133070
> If some people could help me in this, I would be very grateful :) Have a look at the FTDI vinculum, it takes most of the work out of accessing USB sticks. NialArticle: 133071
This is a multi-part message in MIME format. ------=_NextPart_000_0022_01C8D08F.435BF5A0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Many thanks for the people took time to answer. EC "backhus" <nix@nirgends.xyz> =D7=9B=D7=AA=D7=91 = =D7=91=D7=94=D7=95=D7=93=D7=A2=D7=94:g37nns$oqp$1@news.hs-bremen.de... > Hi, > I had the book and the WARP-Compiler running years ago. > It was nice then, because it was the only vhdl synthesis system=20 > available affordable for students etc. at that time. >=20 > What annoyed me even then, was that the synthesis was very restrictive = > about the coding style. So code portability was almost impossible. >=20 > Also, for learning VHDL there are better tools available now for free. = > (e.g. Xilinx Webpack and Modelsim Starter Versions) > There are a lot of good books for VHDL available. Search this group = for=20 > infos. The Cypress book is just not up to date anymore. >=20 > Have a nice synthesis > Eilert >=20 >=20 >=20 > RealInfo schrieb: >> Bytheway >> How good is that book, is it a good way to learn VHDL for = programmable logic=20 >> in general ? >>=20 >> Thanks >> EC >>=20 >>=20 >> "ghelbig" <ghelbig@lycos.com> ???=20 >> = ??????:493281cd-f7a2-4139-a6d2-981b086dfb43@s21g2000prm.googlegroups.com.= .. >>> On Jun 16, 10:49 am, Mike Treseler <mike_trese...@comcast.net> = wrote: >>>> RealInfo wrote: >>>>> It comes with the WARP cpld design software for cyperess cplds . >>>> Future Electronics CY3120R62CD >>> Mike: >>> >>> The Future Electronics web site reports that part # as non-existant. >>> There was a 6.3 release (CY3120R63), but that search turns up empty >>> also. >>> >>> To the OP: >>> >>> Cypress no longer makes CPLDs. Unless you are supporting an old >>> design (like the CPLD on the FX2 Eval card :) the Warp package is = only >>> useful for SPLDs. >>> >>> Warp runs "just fine" on Windows 2000, it should work on XP as well. >>> It has a good uninstall, so just go ahead and try it. >>> >>> G.=20 >>=20 >> ------=_NextPart_000_0022_01C8D08F.435BF5A0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =EF=BB=BF<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; charset=3Dutf-8"> <META content=3D"MSHTML 6.00.2900.2180" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY> <DIV><FONT size=3D2><STRONG>Many thanks for the people took time to=20 answer.</STRONG></FONT></DIV> <DIV><FONT size=3D2><STRONG></STRONG></FONT> </DIV> <DIV><FONT size=3D2><STRONG>EC</STRONG></FONT></DIV> <DIV><FONT size=3D2></FONT> </DIV> <DIV><FONT size=3D2></FONT> </DIV> <DIV><FONT size=3D2>"backhus" <</FONT><A = href=3D"mailto:nix@nirgends.xyz"><FONT=20 size=3D2>nix@nirgends.xyz</FONT></A><FONT size=3D2>> = =D7=9B=D7=AA=D7=91=20 =D7=91=D7=94=D7=95=D7=93=D7=A2=D7=94:g37nns$oqp$1@news.hs-bremen.de...</F= ONT></DIV><FONT size=3D2>>=20 Hi,<BR>> I had the book and the WARP-Compiler running years = ago.<BR>> It=20 was nice then, because it was the only vhdl synthesis system <BR>> = available=20 affordable for students etc. at that time.<BR>> <BR>> What annoyed = me even=20 then, was that the synthesis was very restrictive <BR>> about the = coding=20 style. So code portability was almost impossible.<BR>> <BR>> Also, = for=20 learning VHDL there are better tools available now for free. <BR>> = (e.g.=20 Xilinx Webpack and Modelsim Starter Versions)<BR>> There are a lot of = good=20 books for VHDL available. Search this group for <BR>> infos. The = Cypress book=20 is just not up to date anymore.<BR>> <BR>> Have a nice=20 synthesis<BR>> Eilert<BR>> <BR>> <BR>> = <BR>>=20 RealInfo schrieb:<BR>>> Bytheway<BR>>> How good is that = book, is it=20 a good way to learn VHDL for programmable logic <BR>>> in general=20 ?<BR>>> <BR>>> Thanks<BR>>> EC<BR>>> = <BR>>>=20 <BR>>> "ghelbig" <</FONT><A = href=3D"mailto:ghelbig@lycos.com"><FONT=20 size=3D2>ghelbig@lycos.com</FONT></A><FONT size=3D2>> ??? = <BR>>>=20 ??????:493281cd-f7a2-4139-a6d2-981b086dfb43@s21g2000prm.googlegroups.com.= ..<BR>>>>=20 On Jun 16, 10:49 am, Mike Treseler <</FONT><A=20 href=3D"mailto:mike_trese...@comcast.net"><FONT=20 size=3D2>mike_trese...@comcast.net</FONT></A><FONT size=3D2>>=20 wrote:<BR>>>>> RealInfo wrote:<BR>>>>>> It = comes with=20 the WARP cpld design software for cyperess cplds .<BR>>>>> = Future=20 Electronics CY3120R62CD<BR>>>> = Mike:<BR>>>><BR>>>>=20 The Future Electronics web site reports that part # as=20 non-existant.<BR>>>> There was a 6.3 release (CY3120R63), but = that=20 search turns up empty<BR>>>> = also.<BR>>>><BR>>>> To=20 the OP:<BR>>>><BR>>>> Cypress no longer makes = CPLDs. =20 Unless you are supporting an old<BR>>>> design (like the CPLD = on the=20 FX2 Eval card :) the Warp package is only<BR>>>> useful for=20 SPLDs.<BR>>>><BR>>>> Warp runs "just fine" on Windows = 2000, it=20 should work on XP as well.<BR>>>> It has a good uninstall, so = just go=20 ahead and try it.<BR>>>><BR>>>> G. <BR>>>=20 <BR>>></FONT></BODY></HTML> ------=_NextPart_000_0022_01C8D08F.435BF5A0--Article: 133072
My desig directly instantiates Xilinx block ram ramb16_s18_s18, in order to verify that those block rams have been integrated correctly in the design, I'm using the block ram verilog file from ISE unisim directory to validate my design in simulation, but it seems that there are timing issues when I simulate the design in ModelSim. Are those files supposed to be run correctly in simulation? or they're just for FPGAs. Thanks, JackArticle: 133073
Hi I need little help about ISE MIG tool. I have a couple baic questions and if someone can answer me I would be very greatfull. First thing I wanted to ask is: "does MIG gives me oportunity to define data bits aslo. I meant, in the UCF file that is generated at the end I can see only control signals. That is ok, yes? than in my design, I can define constraints about DATA ports as I want. Am I right about this? I also waned to ask one more question. I can reserve pin that I don't want to be used by MIG, but how can I be sure that pins that it has chosed are same every time I generate this core. For example . I want that all NETs are from BANK 1. I put these Bank0 Bank2 adn Bank3 as reserved. But how can I be sure that all Nets are shosen on the same way every time. Can I reserve all pins beisde the ones I want to be used by MIG (reserve also some bits from bank 1). IS it OK. But still I have problems if I am not sure that the pins are reserved the same time (IF I conect ddr and fpga on the pcb I can't change it time to time). and the last I have some strange problem that I didn't get from the begging. I reserve all banks except the bank 1. When I want to chose pins and when I chech check box indicaitng data pins in bank 1 I get this message. "MIG doesn't suport data signals that are from multiple sides limit your selection for Data signals for only one side". This confuse me totaly. Should I check All pins that are going to be used by mig to be on one side? Am I right? I am greatfull for any kind of help. Thanks to everybody. ZoranArticle: 133074
I think that those files can be used in simulation regulary. Just check to see did you included all libraries. What kind of isue you are getting? Greetings Zoran On Jun 17, 4:10=A0pm, "jack.harv...@googlemail.com" <jack.harv...@googlemail.com> wrote: > My desig directly instantiates Xilinx block ram ramb16_s18_s18, in > order to verify that those block rams have been integrated correctly > in the design, I'm using the block ram verilog file from ISE unisim > directory to validate my design in simulation, but it seems that there > are timing issues when I simulate the design in ModelSim. Are those > files supposed to be run correctly in simulation? or they're just for > FPGAs. > > Thanks, > Jack
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