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The last FIR I implemented, I scaled the data and coefficients so that they were all in range: -1 <= number < +1 Note lack of equality in upper bound, therefore need trap for -1 * -1 case. It worked well enough. P.S. If you don't like hard work, go into marketing...Article: 133101
Hi, I have one question about Memory Interface Generator. This problem I can't solve for a period of time so I decided to ask help. The thing is this. I generate my Mig core from the project. THis process pass ok. But when I want to implement my design I have problems. First thing that bugs me is this. When I start implementation of design I am gettign messages that my core is not recogneze (that my xco file is not included or vhd or something), but this is inposible because Istart core generator form my project and it is loaded automaticly. Anyway, bacause of this ISE ask me to redesign my core so I have to do this that I can go to the next step. When I finish this, imlementation process continiues and after while I get this error ":NgdBuild:604 - logical block 'u_moj_mig' with type 'moj_mig' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'moj_mig' is not supported in target 'spartan3a'." I want to add those files to the project but ISE tell me that ngc file is already in the project (strange). Has nayone ever worked with this MIG core I need any kind of help advice anythig.. Thanks in forward for your help ZoranArticle: 133102
Hey, Just wondering if anyone knows the command to stop module declarations of black boxes being written out to the verilog netlist precision generates for post-synthesis simulation. At the moment i'm having to trawl through my post synthesis netlist and delete the empty module declarations. It's annoying and lengthy (as there are many). There must be some attribute i can set to false or a command to halt precision writing out these empty module declarations I just cant seem to find it in the documentation. Any help would be amazing. Cheers, Rob.Article: 133103
On 18 Jun., 14:38, rickman <gnu...@gmail.com> wrote: > On Jun 18, 7:57 am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > > > > You simulation model should match the behaviour of your hardware, > > otherwise it is useless. > > Modern FPGAs initialize all registers upon poweron. You models should > > reflect that. > > Just initialize the signales at declaration and you are done. > > > In many ASIC libraries and some older FPGAs the initial values of > > registers are random. 'X' is the > > perfect representation for that. You definitely want the 'X's in your > > simulation in that case because > > it is the only way to make sure that your circuit works correctly even > > with random start values. > > Your circuitry must be design so that all flip-flop eventually obtain > > defined states. > > > Kolja Sulimma > > You have just argued against yourself. =A0You have told him to > initialize registers in the declaration, then you say you want Xs to > represent arbitrary initialization. =A0 Did you actually read my post? I explained two cases: Hardware that starts with defined values, and hardware that starts with random values. Of course you model those differently. The OP did not mention the target technology so I had to explain both cases. > =A0If you really want to model the hardware, you need to *never* initiali= ze registers > in the declaration, but rather initialize them in an async reset > portion of the process. =A0Then any that you miss show up as Xs and any > that you properly initialize should be synthesized that way. That is true for most ASIC libraries, but not for Xilinx FPGAs. (I don't know much about Altera). Xilinx explicitely discourages the use of asynchronous resets on is flip-flops. http://www.xilinx.com/support/documentation/white_papers/wp231.pdf Page 3: "Avoid asynchronous reset because it prevents packing of registers into dedicated resources and affects performance, utilization, and tool optimizations." http://toolbox.xilinx.com/docsan/xilinx10/books/docs/sim/sim.pdf Page 67: "All architectures support an asynchronous reset for those registers and latches. Even though this capability exists, Xilinx does not recommend that you code for it. Using asynchronous resets may result in: =95 More difficult timing analysis =95 Less optimal optimization by the synthesis tool" All DFFs are initialized at configuration time. If not specified otherwise in the HDL code they are initialized to '0'. The simulation model should be consistent with this hardware behaviour. Kolja SulimmaArticle: 133104
On 18 Jun., 14:48, Rob <BertyBoos...@googlemail.com> wrote: > This is exactly the problem, i'd rather not give certain registers > init values, especially in the data path, as firstly it is unnecessary > for the actual hardware implementation But you can't prevent it in a modern FPGA. Why should you explicitely build a model that does not reflect the actual behaviour of the hardware? > and secondly because in > simulation seeing a vector of 'X's indicates that this bus hasn't yet > been assigned a proper value. The problem comes when that data bus is > driving a process that says something like "if data_bus = 0 then...". > I can usually avoid this with clock enables, but sometimes it isn't > convenient to have a clock enable signal with the data. So you are replacing the free initialization of the registers by extra clock enable hardware for what reason exactly? Kolja SulimmaArticle: 133105
On Wed, 18 Jun 2008 04:57:04 -0700 (PDT), Kolja Sulimma <ksulimma@googlemail.com> wrote: >In many ASIC libraries and some older FPGAs the initial values of >registers are random. 'X' is the >perfect representation for that. You definitely want the 'X's in your >simulation in that case because >it is the only way to make sure that your circuit works correctly even >with random start values. >Your circuitry must be design so that all flip-flop eventually obtain >defined states. > I completely agree with this : you want to see that any initial "X"es are cleared to valid values in a few cycles after reset, BY THE LOGIC ITSELF and not a spurious "clean" function. The disadvantage is that I typically have to live with pages of warnings from the first 200ns or so (until all "X"es are purged from the pipeline) followed by a clean simulation. There are options in some libraries (numeric_std for one) in Modelsim to suppress these warnings; but this carries the risk of suppressing real information. So I don't think that's a good idea either. I just ignore them... (actually I pay a LITTLE attention to reducing their number, but it's not important) ... but wouldn't it be nice to tell the simulator to suppress these errors for the first XXX ns, then report them. I expect a simple TCL script would do it... suppress Numeric_Std invalid value warnings; run 250 ns; enable Numeric_Std invalid value warnings; run; but haven't taken the time to learn enough TCL to try (my testbenches are entirely VHDL and that keeps me busy enough!). - BrianArticle: 133106
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message
news:bt4i541q56gf2ukbbgbtvahq6nrlt0jo31@4ax.com...
> On Wed, 18 Jun 2008 04:57:04 -0700 (PDT), Kolja Sulimma
..
> There are options in some libraries (numeric_std for one) in Modelsim to
> suppress these warnings; but this carries the risk of suppressing real
> information. So I don't think that's a good idea either.
>
> I just ignore them... (actually I pay a LITTLE attention to reducing
> their number, but it's not important) ... but wouldn't it be nice to
> tell the simulator to suppress these errors for the first XXX ns, then
> report them.
>
> I expect a simple TCL script would do it...
>
> suppress Numeric_Std invalid value warnings;
> run 250 ns;
> enable Numeric_Std invalid value warnings;
> run;
Close,
set StdArithNoWarnings 1
set NumericStdNoWarnings 0
run 0 ns;
set StdArithNoWarnings 0
set NumericStdNoWarnings 0
run ....
or if you want to suppress the warnings until reset is negated you can use
something like this:
when -label enable_StdWarn {reset_s == '1'} {echo "Enable StdArithWarnings"
; set StdArithNoWarnings 0 ;}
Hans
www.ht-lab.com
>
> but haven't taken the time to learn enough TCL to try
> (my testbenches are entirely VHDL and that keeps me busy enough!).
>
> - Brian
>
Article: 133107http://www.xilinx.com/ise/logic_design_prod/webpack.htm RTWP*, Austin * try 'reading the web pages'Article: 133108
On Jun 18, 8:48=A0am, Rob <BertyBoos...@googlemail.com> wrote: > On Jun 18, 1:38 pm, rickman <gnu...@gmail.com> wrote: > > > > > > > On Jun 18, 7:57 am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > > > You simulation model should match the behaviour of your hardware, > > > otherwise it is useless. > > > Modern FPGAs initialize all registers upon poweron. You models should > > > reflect that. > > > Just initialize the signales at declaration and you are done. > > > > In many ASIC libraries and some older FPGAs the initial values of > > > registers are random. 'X' is the > > > perfect representation for that. You definitely want the 'X's in your > > > simulation in that case because > > > it is the only way to make sure that your circuit works correctly eve= n > > > with random start values. > > > Your circuitry must be design so that all flip-flop eventually obtain > > > defined states. > > > > Kolja Sulimma > > > You have just argued against yourself. =A0You have told him to > > initialize registers in the declaration, then you say you want Xs to > > represent arbitrary initialization. =A0This arbitrary initialization is > > what the X is intended to represent, an unknown state. =A0If you really > > want to model the hardware, you need to *never* initialize registers > > in the declaration, but rather initialize them in an async reset > > portion of the process. =A0Then any that you miss show up as Xs and any > > that you properly initialize should be synthesized that way. > > > Rick > > This is exactly the problem, i'd rather not give certain registers > init values, especially in the data path, as firstly it is unnecessary > for the actual hardware implementation and secondly because in > simulation seeing a vector of 'X's indicates that this bus hasn't yet > been assigned a proper value. The problem comes when that data bus is > driving a process that says something like "if data_bus =3D 0 then...". > I can usually avoid this with clock enables, but sometimes it isn't > convenient to have a clock enable signal with the data.- Hide quoted text= - > > - Show quoted text - First off, these are only simulation warnings, not errors. Not that warnings should be simply ignored, but just keep that in mind. Second, the warnings presumably go away rather quickly after running the simulation as things all get properly initialized so it shouldn't be a big problem. Your functional sim and testbench should be checking for proper functional behaviour hitting asserts whenver something isn't as expected. If your testbenching skills are not quite at that level, then you may need to peruse the warnings a bit closer at least once...and then work on learning the incredible power of assertions to create self checking test benches. Finally, if none of the above seems satisfactory, then realize that there are other data types besides std_logic/std_logic_vector, namely bit/bit_vector that can be used which have absolutely no knowledge of unknowns. Your 'clean' function then can simply be viewed as a conversion function that converts std_logic/std_logic_vector into bit/ bit_vectors. =46rom a synthesis perspective, the construct "if sig =3D 'U' then ..." will be ignored...but will also (usually) generate a warning that you can't compare things to metalogic values. So now you've traded a simulation warning for a synthesis warning so there is really no net value being added by this new function you've created. What's worse is that now you should peruse the synthesis warning very closely to see what is it actually doing when it hits the statement that compares the signal to 'U'. Some plausible examples might be: 1. Does it assume that 'U' is '0'? (In general, this would be bad, in a specific instance it might be OK) 2. Does it assume that the whole if statement is false (This would probably be good). 3. Does this behaviour remain the same over different tools and different versions of tools? (This would be bad as well...but, if the particular tool you use currently does #2, then you could get the false hope that this cleaning works causing you later on to miss the synthesis warning that reflects #1 down the road at some time and that's when you'll get bitten by the cleaner). You can work around all of this by then band-aiding some more by making the cleaning only occur during simulation but that is just making your synthesized code diverge from your functional simulation model...which in my book is the worst of all worlds. Bottom line is I'd recommend against 'clean'. Kevin JenningsArticle: 133109
"HT-Lab" <hans64@ht-lab.com> wrote in message news:5P86k.6335$aE7.5929@newsfe16.ams2... > > "Brian Drummond" <brian_drummond@btconnect.com> wrote in message > news:bt4i541q56gf2ukbbgbtvahq6nrlt0jo31@4ax.com... >> On Wed, 18 Jun 2008 04:57:04 -0700 (PDT), Kolja Sulimma > .. >> There are options in some libraries (numeric_std for one) in Modelsim to >> suppress these warnings; but this carries the risk of suppressing real >> information. So I don't think that's a good idea either. >> >> I just ignore them... (actually I pay a LITTLE attention to reducing >> their number, but it's not important) ... but wouldn't it be nice to >> tell the simulator to suppress these errors for the first XXX ns, then >> report them. >> >> I expect a simple TCL script would do it... >> >> suppress Numeric_Std invalid value warnings; >> run 250 ns; >> enable Numeric_Std invalid value warnings; >> run; > > Close, > > set StdArithNoWarnings 1 > set NumericStdNoWarnings 0 > run 0 ns; > set StdArithNoWarnings 0 > set NumericStdNoWarnings 0 > run .... Doh! set StdArithNoWarnings 1 set NumericStdNoWarnings 1 run 0 ns; set StdArithNoWarnings 0 set NumericStdNoWarnings 0 run .... Hans www.ht-lab.comArticle: 133110
On 18 Jun., 16:29, "HT-Lab" <han...@ht-lab.com> wrote: > Doh! > > set StdArithNoWarnings 1 > set NumericStdNoWarnings 1 LOL. How about: set NumericStdNoWarning 'X' KoljaArticle: 133111
If i use fixed to integer conversion using left shift operation...I am not sure i may be thrown with compilation error as the maximum long int i can is 2^32 only.. so if i have such a long 0.99999999999999999998888888888888777777777 iit is impossible to have such a big int converted value.. so pls suggest for using fixed point binary,,, On Jun 18, 6:25=A0pm, "RCIngham" <robert.ing...@gmail.com> wrote: > The last FIR I implemented, I scaled the data and coefficients so that th= ey > were all in range: > =A0-1 <=3D number < +1 > Note lack of equality in upper bound, therefore need trap for -1 * -1 > case. > > It worked well enough. > > P.S. If you don't like hard work, go into marketing...Article: 133112
On Jun 18, 10:45=A0am, faza <fazulu.v...@gmail.com> wrote: > If i use fixed to integer conversion using left shift operation...I am > not sure i may be thrown with compilation error as the maximum long > int i can is 2^32 only.. > > so if i have such a long 0.99999999999999999998888888888888777777777 > > iit is impossible to have such a big int converted value.. > > so pls suggest for using fixed point binary,,, > > On Jun 18, 6:25=A0pm, "RCIngham" <robert.ing...@gmail.com> wrote: > > > > > The last FIR I implemented, I scaled the data and coefficients so that = they > > were all in range: > > =A0-1 <=3D number < +1 > > Note lack of equality in upper bound, therefore need trap for -1 * -1 > > case. > > > It worked well enough. > > > P.S. If you don't like hard work, go into marketing...- Hide quoted tex= t - > > - Show quoted text - Read my reply to your original posting....the fixed point library code already exists and does what you need with whatever precision you require. KJArticle: 133113
Hello, I am using a Xilinx Spartan-3 FPGA (XC3S200-4), and I am having
difficulty mapping the Digital Clock Manager (DCM) output onto my
clock net using a global buffer.
My intent is to take my external clock, input it into the DCM, and use
the double frequency output, X2, to run my internal logic. I used the
Xilinx Wizard to generate code for the DCM, and I have am instance of
that DCM in my VHDL file. The Wizard does map the X2 output to a
Global Buffer, BUFG, but when I assign that output to my clock net, it
looks like it is on a local routing line.
Should I assign my clock net to another BUFG? This looks like a waste
of resources. I should only have to use one Global Buffer for the X2
output. I have attached my VHDL code below. Thanks for the help.
Here is the instantiation in my code:
Inst_dcm_x2: dcm_x2 PORT MAP (
CLKIN_IN => clock, -- This is my external clock
in
RST_IN => rst_bar,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
CLK2X_OUT => clk, -- I am trying to map the
CLK2X_OUT to clk
LOCKED_OUT => dcm_locked
);
Here is the VHDL code the wizard generated:
entity dcm_x2 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
CLK2X_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end dcm_x2;
architecture BEHAVIORAL of dcm_x2 is
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal CLK2X_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
CLK2X_BUFG_INST : BUFG
port map (I=>CLK2X_BUF,
O=>CLK2X_OUT); -- CLK2X_OUT is already
assigned to a BUFG, how do I map this to 'clk'
DCM_INST : DCM
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 25.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"8080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>CLK2X_BUF,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
Article: 133114On Jun 17, 7:41=A0am, Zorjak <Zor...@gmail.com> wrote: > Hi > > I need little help about ISE MIG tool. I have a couple baic questions > and if someone can answer me I would be very greatfull. > First thing I wanted to ask is: "does MIG gives me oportunity to > define data bits aslo. I meant, in the UCF file that is generated at > the end I can see only control signals. That is ok, yes? than in my > design, =A0I can define constraints about DATA ports as I want. Am =A0I > right about this? > > I also waned to ask one more question. > I can reserve pin that I don't want to be used by MIG, but how can I > be sure that pins that it has chosed are same every time I generate > this core. For example . I want that all NETs are from BANK 1. I put > these Bank0 Bank2 adn Bank3 as reserved. But how can I be sure that > all Nets are shosen on the same way every time. Can I reserve all pins > beisde the ones I want to be used by MIG (reserve also some bits from > bank 1). IS it OK. But still I have problems if I am not sure that the > pins are reserved the same time (IF I conect ddr and fpga on the pcb > I can't change it time to time). > > and the last I have some strange problem that I didn't get from the > begging. I reserve all banks except the bank 1. When I want to chose > pins and when I chech check box indicaitng data pins in bank 1 I get > this message. > > =A0"MIG doesn't suport data signals that are from multiple sides limit > your selection for Data signals for only one side". This confuse me > totaly. Should I check All pins that are going to be used by mig to be > on one side? Am I right? > > I am greatfull for any kind of help. Thanks to everybody. > Zoran I have used MIG2.0, and it definitiely assigned LOC constraints to all pins, including data bits. It doesn't change pin assignments when you re-generate the core, unless you change something in the wizard, like data width or bank selections. I remember some sort of graphical deal in the wizard for bank selection, and of course you want to stay on one side of the die, to avoid long route delays. There was no need to reserve pins. I hope you are reading the User's Guide. BarryArticle: 133115
"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message news:8e8331f2-d305-40db-8b97-fd0c2c8ba02d@x35g2000hsb.googlegroups.com... > On 18 Jun., 16:29, "HT-Lab" <han...@ht-lab.com> wrote: > >> Doh! >> >> set StdArithNoWarnings 1 >> set NumericStdNoWarnings 1 > > LOL. > How about: > set NumericStdNoWarning 'X' If you give that command than Modelsim will automatically un-install, delete your license file and block any emails to support@..... Of course this only works in version 6.3, 4.7 to 6.2 simply deletes your partition table. Version 6.4 (expected soon) will also send an email to your boss to get you fired, Hans www.ht-lab.com > > KoljaArticle: 133116
On Jun 17, 10:13=A0am, jon <j...@pyramidemail.com> wrote: > I have 240 extra pieces of the Altera EP2C20F484C6N and we will not be > able to use. Parts are new in original factory sealed packaging. > Please let me know if you can use. I should be able to supply below > factory direct pricing. Please let me know if you are interested in > any quantity at all. > > Regards, > Jon E. Hansen > (949)864-7745 I also have 34 pieces of the Stratix II GX, the part number is EP2SGX90FF1508C3N. Please call me if you are using these. Best Regards, Jon E. Hansen (949)864-7745Article: 133117
> So you are replacing the free initialization of the registers by extra > clock enable hardware for what reason exactly? You misunderstand. I'm not adding clock enables to bodge around this problem, the data is ordinarily accompanied by a clock enable signal by design. It's where it isn't that I get problems. Well, I'm pretty convinced that a clean function is a horrible hack never to be spoken of again. Thanks for your helpful comments. One issue not covered is where a part of the design doesn't receive data until a way into simulation and therefore turning off warnings for the first few hundred ns doesn't fix things. I suppose that sometimes you just can't avoid plugging a 'x' vector into some arithmetic function, and there doesn't seem to be a magical fix for all scenarios. maybe if you could attach an attribute to an offending signal(s) if you've had a good look and decided you don't care about warnings on this part of the design....Article: 133118
Hi,
In the document of FIR Complier v3.2, it talks about coefficient
padding. I have several questions about that topic.
It gives an example:
MAC0 l m n p
MAC1 h i j k
MAC2 d e f g
MAC3 0 a b c
It said that this kind of 0 padding will cause phase shift with the
normal non-symmetric structure.
It then gave two examples in Figure 28 using interpolation.
Interpolate by 2
a, c, e, g, h, f, d, b-----
|--------
b, d, f, h, g, e, c, a-----
For this example, I don't know why they use interpolate 2 sturcture.
The simple "a, b, c, d, e, f, g, h" has the same complexity.
For the second example, how to use the coefficients in the FIR
structure?
Even Sym: a+b, c+d, e+f, g+h, h+g, f+e, d+c, b+a.
Even Sym: b-a, d-c, f-e, h-g, g-h, e-f, c-d, a-b.
(negative sym)
Could you explain it to me? Thanks a lot.
Article: 133119By the way, it's a Xilinx FPGA design using XST and Modelsim.Article: 133120
Beantown wrote: > Hello, I am using a Xilinx Spartan-3 FPGA (XC3S200-4), and I am having > difficulty mapping the Digital Clock Manager (DCM) output onto my > clock net using a global buffer. > > My intent is to take my external clock, input it into the DCM, and use > the double frequency output, X2, to run my internal logic. I used the > Xilinx Wizard to generate code for the DCM, and I have am instance of > that DCM in my VHDL file. The Wizard does map the X2 output to a > Global Buffer, BUFG, but when I assign that output to my clock net, it > looks like it is on a local routing line. > > Should I assign my clock net to another BUFG? This looks like a waste > of resources. I should only have to use one Global Buffer for the X2 > output. I have attached my VHDL code below. Thanks for the help. <snip code> What makes you think the clock is local routing? You should be able to use FPGA Editor to see the DCM and BUFG instances and the associated clocks. If you see the clock jumping off the global net, perhaps there's a mixup with the appropriate device half or quadrant that the BUFG drives versus the location of the driven logic. Good luck, - John_HArticle: 133121
The cypress controller you mentioned (68013a) is a nice peripheral controller, but it is unfortunately not a host. Cypress does have a range of easy to use host chips, but this is not one of them (and last I checked none of them were high speed). Connecting a flash drive (which is also a 'peripheral' or 'device') requires a host interface. The cypress chip, however could be easily used to download files from a PC or other portable host. The easiest way to interface the 68013a to a host is simply to configure it in Slave FIFO mode, such that you merely monitor the levels of the various endpoints, and read off the data. The endpoints as well as the operating state are configured by the onboard microcontroller. The configuration can be done via an external EEPROM if your board has one, or by downloading over USB and 'renumerating'. We use this chip as a cheap interface for a monitoring application, just by filling up the fifos as we receive the data. Hope this helps.Article: 133122
"austin" <austin@xilinx.com> wrote in message news:g3b5pt$sra1@cnn.xsj.xilinx.com... > http://www.xilinx.com/ise/logic_design_prod/webpack.htm > > RTWP*, > > Austin > > * try 'reading the web pages' RTFM would have been appropriate, here, but I understand that your position mandates some self control. 8} Bob -- == NOTE: I automatically delete all Google Group posts due to uncontrolled SPAM ==Article: 133123
On Jun 18, 10:01 am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 18 Jun., 14:38, rickman <gnu...@gmail.com> wrote: > > > > > On Jun 18, 7:57 am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > > > > You simulation model should match the behaviour of your hardware, > > > otherwise it is useless. > > > Modern FPGAs initialize all registers upon poweron. You models should > > > reflect that. > > > Just initialize the signales at declaration and you are done. > > > > In many ASIC libraries and some older FPGAs the initial values of > > > registers are random. 'X' is the > > > perfect representation for that. You definitely want the 'X's in your > > > simulation in that case because > > > it is the only way to make sure that your circuit works correctly eve= n > > > with random start values. > > > Your circuitry must be design so that all flip-flop eventually obtain > > > defined states. > > > > Kolja Sulimma > > > You have just argued against yourself. You have told him to > > initialize registers in the declaration, then you say you want Xs to > > represent arbitrary initialization. > > Did you actually read my post? I explained two cases: Hardware that > starts with defined values, and hardware that starts with random > values. Of course you model those differently. > The OP did not mention the target technology so I had to explain both > cases. Yes, I did read your post. It discusses two separate cases and does not show that you fully understand what is going on in the part vs. the simulation. If you don't want to discuss it, please read no more. But if you are interested in what I have to say read further. > > If you really want to model the hardware, you need to *never* initiali= ze registers > > in the declaration, but rather initialize them in an async reset > > portion of the process. Then any that you miss show up as Xs and any > > that you properly initialize should be synthesized that way. > > That is true for most ASIC libraries, but not for Xilinx FPGAs. (I > don't know much about Altera). Xilinx explicitely discourages the use > of asynchronous resets on is flip-flops.http://www.xilinx.com/support/doc= umentation/white_papers/wp231.pdf > Page 3: "Avoid asynchronous reset because it prevents packing of > registers into dedicated resources and affects performance, > utilization, and tool optimizations." Xilinx may tell you not to use async resets, but the GSR, which is the signal that you are referring to when you wrote, "Modern FPGAs initialize all registers upon poweron", is an ***asynchronous*** reset/ set. So in FPGAs you can't avoid using it, unless there is a trick to totally disable it that I have not heard of. My point was that you described two separate cases as if either one is valid. But that is not correct. The only valid case is one that matches your hardware. ASICs may not need the async reset for some self synchronizing circuits or for data path. Data path will typically sort itself out once valid data enters. But a self synchronizing circuit will never sort itself out in simulation even if it does in the real chip. So it is better to initialize those circuits as well so that the simulation will match the hardware. > http://toolbox.xilinx.com/docsan/xilinx10/books/docs/sim/sim.pdf > Page 67: > "All architectures support an asynchronous > reset for those registers and latches. Even though this capability > exists, Xilinx does not recommend that you code for it. Using > asynchronous resets may result in: > =95 More difficult timing analysis > =95 Less optimal optimization by the synthesis tool" > > All DFFs are initialized at configuration time. If not specified > otherwise in the HDL code they are initialized to '0'. The simulation > model should be consistent with this hardware behaviour. Specifying an initial condition in the declaration is not a match to the hardware. The GSR signal is released asynchronously and should not be used to provide an initial condition for logic that can be disrupted by different FFs being released on different clock cycles. I always generate a reset from an arbitrary signal, preferably an external reset. The software will assign this net to the user input to the GSR function and as long as the prop delay is not slower than your clock, it will function correctly. The above note from Xilinx is not referring to the use of the GSR function, it is referring to arbitrary signals being used as async sets and resets. RickArticle: 133124
On Jun 18, 10:04 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 18 Jun 2008 04:57:04 -0700 (PDT), Kolja Sulimma > > <ksuli...@googlemail.com> wrote: > >In many ASIC libraries and some older FPGAs the initial values of > >registers are random. 'X' is the > >perfect representation for that. You definitely want the 'X's in your > >simulation in that case because > >it is the only way to make sure that your circuit works correctly even > >with random start values. > >Your circuitry must be design so that all flip-flop eventually obtain > >defined states. > > I completely agree with this : you want to see that any initial "X"es > are cleared to valid values in a few cycles after reset, BY THE LOGIC > ITSELF and not a spurious "clean" function. There are applications that will work correctly in hardware without an initial condition, but never reach a valid state in simulation without it. In those cases I find it easier to add an initialization to the hardware to make the simulation match the hardware. An xxample is a free running divide by 2 clock generator. It will start up in a 1 or a 0 state. It does not matter. But the simualtor will never resolve the 'X' starting state. Some state machines can start in any state and find their way to a valid state, by design. This is hard to verify in simulation. It typically requires starting the FSM in every possible state. But letting it start in an all 'X' state will typically leave it in an all 'X' state forever. > The disadvantage is that I typically have to live with pages of warnings > from the first 200ns or so (until all "X"es are purged from the > pipeline) followed by a clean simulation. > > There are options in some libraries (numeric_std for one) in Modelsim to > suppress these warnings; but this carries the risk of suppressing real > information. So I don't think that's a good idea either. > > I just ignore them... (actually I pay a LITTLE attention to reducing > their number, but it's not important) ... but wouldn't it be nice to > tell the simulator to suppress these errors for the first XXX ns, then > report them. > > I expect a simple TCL script would do it... > > suppress Numeric_Std invalid value warnings; > run 250 ns; > enable Numeric_Std invalid value warnings; > run; > > but haven't taken the time to learn enough TCL to try > (my testbenches are entirely VHDL and that keeps me busy enough!). Is it important to not use an initial condition controlled by a global reset? In FPGAs this is typically free, or almost free to use it properly. In ASICs I guess it is a different matter. Rick
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