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On Wed, 18 Jun 2008 18:01:59 -0700, SynopsysFPGAexpress wrote: > As commodity PC hardware and prouctivity applications deline in price, > EDA tools are as (relatively) expensive as ever, necessitating yet > another discussion of "Which simulator is right for me?" I've done some benchmarking on Verilog simulators. Here are the times for running our regression suite on one of our cores. I ran the test suite on Cadence NCSim on CentOS5, Mentor's Questa on both CentOS5 and XP, and Altera's Modelsim on CentOS5. The system is a 3GHz Core2 with 8G of DDR. NC is the fastest but Questa on CentOS5 is close. Questa on XP is much slower then it is on Linux. The Altera ModelSim is dog slow which is to be expected, I'm sure that Mentor has deliberately crippled it. NC, Linux 0:06:34 Questa, Linux 0:07:15 Questa, XP 0:18:14 Altera ModelSim, Linux 1:00:13Article: 133201
"General Schvantzkopf" <schvantzkopf@yahoo.com> wrote in message news:iIqdncpPC63KCsbVnZ2dnUVZ_jKdnZ2d@comcast.com... > On Wed, 18 Jun 2008 18:01:59 -0700, SynopsysFPGAexpress wrote: > >> As commodity PC hardware and prouctivity applications deline in price, >> EDA tools are as (relatively) expensive as ever, necessitating yet >> another discussion of "Which simulator is right for me?" > > I've done some benchmarking on Verilog simulators. Lies, damn lies and benchmarks :-) > Here are the times for > running our regression suite on one of our cores. > I ran the test suite on > Cadence NCSim on CentOS5, Mentor's Questa on both CentOS5 and XP, and > Altera's Modelsim on CentOS5. Benchmarking is very difficult and not only requires multiple designs and knowing the environment inside out you also need to know what the simulator is doing to your code. Verilog has the advantage(?) that you can tweak the simulator to improve performance however, this might break some simulations. (Un)fortunately this is not possible with VHDL which is far more stricter in what you can do with the compiler. Using one core without mentioning how you measured it, simulator/compiler settings, versions etc is not much use IMHO. > The system is a 3GHz Core2 with 8G of DDR. > NC is the fastest but Questa on CentOS5 is close. Questa on XP is much > slower then it is on Linux. I found the same. > The Altera ModelSim is dog slow which is to > be expected, I'm sure that Mentor has deliberately crippled it. This is fully documented. I believe the OEM versions are about 40% of PE, however, the problem is that after a certain number of lines it grinds to a halt and becomes completely useless. Hans www.ht-lab.com > > NC, Linux 0:06:34 > Questa, Linux 0:07:15 > Questa, XP 0:18:14 > Altera ModelSim, Linux 1:00:13Article: 133202
On Jun 19, 5:42=A0pm, jhal...@TheWorld.com (Joseph H Allen) wrote: > In article <20080619124737.4526b...@wolfenstein.jpl.nasa.gov>, > Jason Zheng =A0<Xin.Zh...@jpl.nasa.gov> wrote: > > >Invoke vsim with -do "log -r *; run -all; quit -f" and -wlf > >"mydump.wlf", and you'll get similar results (just in a different > >format). In my experience ncsim is faster than Modelsim, and of course > >it carries a higher price tag. > > This didn't work, but I eventually figured it out: > > Start with an empty directory except for some verilog files you want to > simulate: > > # Create work directory > vlib work > > # Compile verilog files (vcom for vhdl) > vlog tb.v > vlog dut.v > > # Simulate > vsim -do "log -r *; run -all; quit -f" work.tb > > =A0 =A0- this creates a vsim.wlf file with everything in it just > =A0 =A0 =A0as you say. > > Now try to view the waveform. =A0If I try: > > vsim -wlf vsim.wlf work.tb -do "view wave; add wave *" > > This brings up modelsim GUI and opens the waveform viewer window. =A0All = of > signals are in the viewer, and they're all empty. > > But this does work: > > vsim -view vsim.wlf -do "view wave; add wave *" > > but it won't work after you have done the previous vsim -wlf command, vsi= m > -wlf does something to the .wlf file or sets something in an initializati= on > file somewhere. =A0I had to re-run the simulation before "vsim -view ..."= for > it to work. > The "-wlf XXXX.wlf" option renames the output file to 'XXXX.wlf'. So if you run your sim and then run the command with the -view option, it'll work fine. If you run 'vsim -wlf vsim.wlf work.tb -do "view wave; add wave *"', it erases your previous vsim.wlf and opens a new one with that name. That's why the waveform opens with no data. I'll typically add the signals I want to log to a .do file instead of logging all of the signals in a design. The more signals you log, the slower ModelSIM runs. > > I notice that when the GUI is open, I can't also run a simulation on the > command line because there is only one license. > Yea, but if you have the GUI open already, why not just run the sim in the GUI?Article: 133203
Hi , i would like to know which kind of memory that Xilinx use for the encryption key storage ( virtex 5 ) , is it an asic ? Also , is it possible to know the features of the dercrypter ( type , speed ) . Decryption is realised by the PowerPC ? DSP ? i couldn't find information in Xilinx doc . thank youArticle: 133204
On Jun 19, 12:02=A0am, Zorjak <Zor...@gmail.com> wrote: > Thnak you for your answer barry. you were right aobut data pins. > Actually I haven't read the ucf file till the end. I've just seen the > control bits where are assigned and I didn't even asumed that data > pins can be asigned latter in the file. I asumed that there are going > to be on the sme place in the file. But OK. It took me a little time > to see this but =A0Ihave found some new things. > Thank you for your answer. > > Have you maybe ever had a problem when you define your MIG core to use > it in the ISE project. I have some stupid proablems that ISE don't > want to recognize this core althoug I've included xco file in it (I > generate the core from the ISE enviroment so all files should be > included automaticly). I just want to test this core. I'have jsut made > one vhd file copying parts from vvho file that was generated but no. I > have problems that ISE says that it can't find my core. I have to > rebuid it, and after that many strange things happen. Which is the > worst the error that I am getting is not always the sma.e Sometimes > ISE ask from me to include all vhd files generated from MIG core > generator. ANd when I do this I get 200 warings saying taht sam parts > can't be instated. Strenge. > I post one more topic here about this problem to explain this. > > If you had similar problems, please tell me more about them > Thank you very much for all your help > Zoran > > On Jun 18, 5:16=A0pm, Barry <barry...@gmail.com> wrote: > > > > > On Jun 17, 7:41=A0am, Zorjak <Zor...@gmail.com> wrote: > > > > Hi > > > > I need little help about ISE MIG tool. I have a couple baic questions > > > and if someone can answer me I would be very greatfull. > > > First thing I wanted to ask is: "does MIG gives me oportunity to > > > define data bits aslo. I meant, in the UCF file that is generated at > > > the end I can see only control signals. That is ok, yes? than in my > > > design, =A0I can define constraints about DATA ports as I want. Am = =A0I > > > right about this? > > > > I also waned to ask one more question. > > > I can reserve pin that I don't want to be used by MIG, but how can I > > > be sure that pins that it has chosed are same every time I generate > > > this core. For example . I want that all NETs are from BANK 1. I put > > > these Bank0 Bank2 adn Bank3 as reserved. But how can I be sure that > > > all Nets are shosen on the same way every time. Can I reserve all pin= s > > > beisde the ones I want to be used by MIG (reserve also some bits from > > > bank 1). IS it OK. But still I have problems if I am not sure that th= e > > > pins are reserved the same time (IF I conect ddr and fpga on the pcb > > > I can't change it time to time). > > > > and the last I have some strange problem that I didn't get from the > > > begging. I reserve all banks except the bank 1. When I want to chose > > > pins and when I chech check box indicaitng data pins in bank 1 I get > > > this message. > > > > =A0"MIG doesn't suport data signals that are from multiple sides limi= t > > > your selection for Data signals for only one side". This confuse me > > > totaly. Should I check All pins that are going to be used by mig to b= e > > > on one side? Am I right? > > > > I am greatfull for any kind of help. Thanks to everybody. > > > Zoran > > > I have used MIG2.0, and it definitiely assigned LOC constraints to all > > pins, including data bits. =A0It doesn't change pin assignments when yo= u > > re-generate the core, unless you change something in the wizard, like > > data width or bank selections. =A0I remember some sort of graphical dea= l > > in the wizard for bank selection, and of course you want to stay on > > one side of the die, to avoid long route delays. =A0There was no need t= o > > reserve pins. =A0I hope you are reading the User's Guide. > > > Barry- Hide quoted text - > > - Show quoted text - Sorry, but I use Synplify rather than XST for synthesis. After running coregen, I copy the ngc file into my project directory. Synplify finds it and hooks up the core. Notice that there are two files named <project_name>.vhd; the larger one is for simulation, and the small one is for synthesis. In one version of coregen, the small one was generated incorrectly, without the empty architecture part. HTHArticle: 133205
On 19 juin, 22:45, rickman <gnu...@gmail.com> wrote: > I use a purely HDL hierarchy. I find that top level schematics or > even low level schematics of large functions tend to end up being more > like a net list than a drawing anyway. You have pins with names X,Y,Z > connected to net R,S,T on page 1. On page 2 you have nets R,S,T > connected to another part with pin names A,B,C. Making it a drawing > doesn't add much in my opinion. Once I gave up hope for schematics > and embraced the HDL world, I found joy in a life of text files and > the infinite advantages they have in the land of version control! I agree that a top level schematic is exactly like a netlist, but the difference to me anyway is that I can quickly grasp how each blocks are connected together. I try to keep most blocks on one large 11x17 page. Here's an example of what I mean: http://www.yousendit.com/transfer.php?action=download&ufid=B152F0A35F44CD17 With a netlist, I have to read the several lines of vhdl code to understand how the blocks are connected and that takes a longer time. Ideally, the vhdl netlist is also accompanied by a block diagram. With the schematics flow, the block diagram comes free. The drawbacks of course are the version control problems associated with schematics files and the lack of a standard file format. To me the version control issues are not a big deal because all the meat is in the vhdl blocks anyway, not the top level. PatrickArticle: 133206
General Schvantzkopf wrote: > The Altera ModelSim is dog slow which is to > be expected, I'm sure that Mentor has deliberately crippled it. > > NC, Linux 0:06:34 > Questa, Linux 0:07:15 > Questa, XP 0:18:14 > Altera ModelSim, Linux 1:00:13 Thanks for taking the time to run the test and for sharing the results. Interesting that speed is roughly proportional to the cost of the license. While the oem version is "dog slow" in this lineup, it is still quite useful for debugging rtl when all the licenses are checked out. -- Mike TreselerArticle: 133207
On Fri, 20 Jun 2008 06:47:17 -0700 (PDT), swissiyoussef@gmail.com wrote: >Hi , > > i would like to know which kind of memory that Xilinx use for the >encryption key storage ( virtex 5 ) , is it an asic ? >Also , is it possible to know the features of the dercrypter ( type , >speed ) . Decryption is realised by the PowerPC ? DSP ? i couldn't >find information in Xilinx doc . This page should answer your questions: http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/configuration.htmArticle: 133208
"Dave" <dave@comteck.com> wrote in message news:f467$485b3676$40b83d5e$25891@COMTECK.COM... > MikeWhy wrote: >> "Dave" <dave@comteck.com> wrote in message >> news:4a422$485b1cf1$40b83d5e$30449@COMTECK.COM... >>> MikeWhy wrote: >>>> >>>> "Dave" <dave@comteck.com> wrote in message >>>> news:f008$485ae84d$40b83d5e$25934@COMTECK.COM... >>>>> >>>>> Availability? Price? >>>> >>>> Nvidia. Google. >>>> >>>> Yes. Cheap. >>> >>> Really? I got _no_ hits on google for the middle speed-range part >>> number. Where did you find it available from? Price? >> >> The C870 is $1300, Nvidia direct or second sourced. The C1060 is slated >> for fall release. >> > > Ahh. The old switcheroo. Jeff wrote about the Tilera TILE64 processor > and I asked about its availability and price. You decided to give > availability and price (sort of) on Nvidia's Tesla GPU card. Explains why I don't mind top-posting as much as others. :) Didn't notice the change in topic. I also didn't find info on the Tilera. Seriously thinking about ordering the C870 here, though.Article: 133209
On Fri, 20 Jun 2008 07:51:58 -0700, Mike Treseler wrote: > General Schvantzkopf wrote: > >> The Altera ModelSim is dog slow which is to be expected, I'm sure that >> Mentor has deliberately crippled it. >> >> NC, Linux 0:06:34 >> Questa, Linux 0:07:15 >> Questa, XP 0:18:14 >> Altera ModelSim, Linux 1:00:13 > > > Thanks for taking the time to run the test and for sharing the results. > Interesting that speed is roughly proportional to the cost of the > license. > > While the oem version is "dog slow" in this lineup, it is still quite > useful for debugging rtl when all the licenses are checked out. > > -- Mike Treseler What should be of most interest to anyone who is looking to buy a serious simulator is the difference between Linux and XP. I ran the same version of Questa on both Linux and XP with the same license. Questa runs three times as fast on Linux as it does on XP. I'm pretty sure that the time difference can be attributed to the performance of the Linux file system (EXT3) vs the XP file system (NTFS). The real purpose of my investigation was to compare various Virtualization tools. I gathered the numbers that I posted before on the native OSes to give me a baseline. I then ran the NC and Questa tests on VMware Server, VMware Workstation and KVM. When using a virtual disk all of the VMs were only 5-10% slower then native, KVM being the fastest. However if I used a host machine directory that was accessed via NFS the performance dropped dramatically, about 2.5X for VMware and 5X for KVM. VMware's shared folders were just as fast as VMware's virtual disk performance i.e. about 10% slower then the native performance. The NFS mounted host directory performance on VMware was about the same as native XP performance which leads me to believe that XP's problem is it's file system.Article: 133210
<meralonurlu@gmail.com> wrote in message news:a7541ca9-3624-417e-9711-136738098832@k37g2000hsf.googlegroups.com... > Xilinx Spartan 3E starter kit. > > process (boff, bon ) > begin > if (boff= '1') then > led <= '0'; > else > if (bon'EVENT AND bon = '1') then > led<='1'; > end if; > end if; > end process; > > generates a D-FF with D connected to Vcc, clk connected to bon, Rst > connected to boff and O connected to led. > This is very Ok. bon turns the led on and boff turns it off. That was > what I wanted but.. > ISE Simulator does not allow me to create a waveform I wish for bon > input on the grounds that it is a clock. How come? Edge sensitivity makes it a clock from the synthesis and simulator point of view. Try enabling async signals in the TBW settings. You'll want to rewrite it as a synchronous process soon enough.Article: 133211
In article <485BC40E.3020008@gmail.com>,
Mike Treseler <mtreseler@gmail.com> wrote:
>General Schvantzkopf wrote:
>
>> The Altera ModelSim is dog slow which is to
>> be expected, I'm sure that Mentor has deliberately crippled it.
>>
>> NC, Linux 0:06:34
>> Questa, Linux 0:07:15
>> Questa, XP 0:18:14
>> Altera ModelSim, Linux 1:00:13
>
>
>Thanks for taking the time to run the test
>and for sharing the results.
>Interesting that speed is roughly proportional
>to the cost of the license.
>
>While the oem version is "dog slow" in this lineup,
>it is still quite useful for debugging rtl
>when all the licenses are checked out.
>
> -- Mike Treseler
It would be interesting to see Icarus in this list. Also Verilator...
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 133212
In article <1radnX8dq9ywT8bVnZ2dnUVZ_sDinZ2d@comcast.com>,
General Schvantzkopf <schvantzkopf@yahoo.com> wrote:
>On Fri, 20 Jun 2008 07:51:58 -0700, Mike Treseler wrote:
>
>> General Schvantzkopf wrote:
>>
>>> The Altera ModelSim is dog slow which is to be expected, I'm sure that
>>> Mentor has deliberately crippled it.
>>>
>>> NC, Linux 0:06:34
>>> Questa, Linux 0:07:15
>>> Questa, XP 0:18:14
>>> Altera ModelSim, Linux 1:00:13
>>
>>
>> Thanks for taking the time to run the test and for sharing the results.
>> Interesting that speed is roughly proportional to the cost of the
>> license.
>>
>> While the oem version is "dog slow" in this lineup, it is still quite
>> useful for debugging rtl when all the licenses are checked out.
>>
>> -- Mike Treseler
>
>What should be of most interest to anyone who is looking to buy a serious
>simulator is the difference between Linux and XP. I ran the same version
>of Questa on both Linux and XP with the same license. Questa runs three
>times as fast on Linux as it does on XP. I'm pretty sure that the time
>difference can be attributed to the performance of the Linux file system
>(EXT3) vs the XP file system (NTFS). The real purpose of my investigation
>was to compare various Virtualization tools. I gathered the numbers that
>I posted before on the native OSes to give me a baseline. I then ran the
>NC and Questa tests on VMware Server, VMware Workstation and KVM. When
>using a virtual disk all of the VMs were only 5-10% slower then native,
>KVM being the fastest. However if I used a host machine directory that
>was accessed via NFS the performance dropped dramatically, about 2.5X for
>VMware and 5X for KVM. VMware's shared folders were just as fast as
>VMware's virtual disk performance i.e. about 10% slower then the native
>performance. The NFS mounted host directory performance on VMware was
>about the same as native XP performance which leads me to believe that
>XP's problem is it's file system.
I wonder if it's core XP or if it's the filesystem itself. There's a
Windows-XP port of EXT2 available. It would be amusing if it was faster than
NTFS.
So was your virus scanner on during the simulation :-)
The answer is to just use Linux.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 133213<andy730215@gmail.com> wrote in message news:133f00df-2331-4cb0-b99d-75d988044592@h1g2000prh.googlegroups.com... > hi all: > I have a question about stratix II .An oscillator must drive a > constant clock frequency to an FPGA pin. The maximum frequency limit > depends on the speed grade of the FPGA. Frequencies of 50 MHz or less > should work for most boards.If my oscillator is less than 50 MHz ,how > to work about this system ? > If about PLL ,I want to know how dose PLL work. > 1. Does PLL function automatically or need manual configure to initial > PLL in the system? > 2. Dose PLL reference anything or any paremeter to lock the frequency? > What is the paremeter? > Thanks in advance. Altera technical answer:- http://www.altera.com/literature/hb/stx2/stratix2_handbook.pdf READ - then - DIGEST I suppose you want your arse wiping as well?Article: 133214
On Fri, 20 Jun 2008 15:53:44 +0000, Joseph H Allen wrote: > In article <485BC40E.3020008@gmail.com>, Mike Treseler > <mtreseler@gmail.com> wrote: >>General Schvantzkopf wrote: >> >>> The Altera ModelSim is dog slow which is to be expected, I'm sure that >>> Mentor has deliberately crippled it. >>> >>> NC, Linux 0:06:34 >>> Questa, Linux 0:07:15 >>> Questa, XP 0:18:14 >>> Altera ModelSim, Linux 1:00:13 >> >> >>Thanks for taking the time to run the test and for sharing the results. >>Interesting that speed is roughly proportional to the cost of the >>license. >> >>While the oem version is "dog slow" in this lineup, it is still quite >>useful for debugging rtl when all the licenses are checked out. >> >> -- Mike Treseler > > It would be interesting to see Icarus in this list. Also Verilator... I haven't been able to get Icarus to work, it's not complete enough to run any of our testbenches. We aren't doing anything fancy, in fact all of our code is strict Verilog 95 it's not even 2001.Article: 133215
On Fri, 20 Jun 2008 10:52:13 -0500 General Schvantzkopf <schvantzkopf@yahoo.com> wrote: > The NFS mounted host directory performance on VMware was > about the same as native XP performance which leads me to believe > that XP's problem is it's file system. That's hardly a convincing proof that all the performance increase is due to file system. In my experience, NFS does slow down ncsim a lot when I turn on the waveform dumping, but without waveform dumping, there is no noticeable performance difference after the design elaboration. I'm not saying filesystem isn't part of it, but for a long simulation with no data logging, 99% of the time the simulator is not doing file I/O. Rather, I believe the following two play a more major role in the speed difference: 1. Context switching. Linux is very very good at this. In a workstation environment where I/O interrupts happen hundreds of times a second, context switching happens everytime the CPU switch to run from one process to the next one. What's good about the Linux kernel is that you can tune a lot of things: the amount of interrupts, how frequently the kernel service them, and how pre-emptible the kernel is. A fine-tuned batch server can very fast. Not so much help from XP. I believe Windows 2000 does have an option to choose between server and desktop mode, but not sure what difference it makes. 2. Memory management. Linux is again very very good at this. Filesystem caching and virtual memory management works hand-in-hand. My 1GB RAM workstation ran 99.9% of time without going to swap partition, whereas in Windows XP, the same workstation constantly sees harddrive thrashing, especially after running a very memory intensive job. -- Faster, faster, you fool, you fool! -- Bill CosbyArticle: 133216
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 General Schvantzkopf wrote: | I haven't been able to get Icarus to work, it's not complete enough to | run any of our testbenches. We aren't doing anything fancy, in fact all | of our code is strict Verilog 95 it's not even 2001. Current snapshots are much improved, and bug reports are welcomed. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.4-svn0 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFIW+XmrPt1Sc2b3ikRAtL9AKCykWIDYFWQkNqwfjcAJUgXewEa0wCgxqwt 6U/NtBgPoBg4Y7aF5Ki6NsY= =YODt -----END PGP SIGNATURE-----Article: 133217
Patrick Dubois wrote: > I really like to create a schematic top level with blocks that are > either more schematics themselves or directly vhdl blocks. I agree with rickman on the notion of a pure HDL hierarchy, but, like you, I also like to see structural views at all levels, including the top. However, I don't like to edit or to maintain graphical sources. I let the quartus rtl viewer draw my schematics based on my synthesis code alone. I can bring it up live to drill down module by module or print out pdfs at any level like this: http://mysite.verizon.net/miketreseler/uart.pdf http://mysite.verizon.net/miketreseler/stack.pdf > The state-machine editor in Active-HDL is another story. To me simple > state machines don't need to be represented by a diagram to be > understood. On the other hand, large ones are hard to represent in a > diagram. So in the end I only write vhdl state machines. Yes, a case statement is easy to write, read, and sim. Drawing curvy arrows and attaching equations is fun once. -- Mike TreselerArticle: 133218
> On Fri, 20 Jun 2008 07:51:58 -0700, Mike Treseler wrote:
>> While the oem version is "dog slow" in this lineup, it is still quite
>> useful for debugging rtl when all the licenses are checked out.
General Schvantzkopf wrote:
> What should be of most interest to anyone who is looking to buy a serious
> simulator is the difference between Linux and XP.
I thought maybe that went without saying.
It is the main reason I maintain an SE license.
Not only is it faster in linux (your numbers look about right to me),
but I can take advantage of the ease of scripting
make and vsim commands to do things like daily
builds and verification from an svn repository.
> I ran the same version
> VMware's shared folders were just as fast as
> VMware's virtual disk performance i.e. about 10% slower then the native
> performance.
Thanks for the VMware info.
I'm still old-school with
two optiplex boxes and a kvm switch.
-- Mike Treseler
Article: 133219On Fri, 20 Jun 2008 10:07:19 -0700, Jason Zheng wrote: > On Fri, 20 Jun 2008 10:52:13 -0500 > General Schvantzkopf <schvantzkopf@yahoo.com> wrote: > >> The NFS mounted host directory performance on VMware was about the same >> as native XP performance which leads me to believe that XP's problem is >> it's file system. > > That's hardly a convincing proof that all the performance increase is > due to file system. In my experience, NFS does slow down ncsim a lot > when I turn on the waveform dumping, but without waveform dumping, there > is no noticeable performance difference after the design elaboration. It's not NFS that's the problem with the VMs it's the virtual IO performance. I looked at the effect of NFS alone by using a directory that was mounted on a second Linux machine that was connected to my test machine via gigabit Ethernet. The degradation of native NC over a true gigabit network was negligible, about the same as running it in a VM with a virtual disk or a shared disk, i.e. about 10%. Using a virtual NIC caused NC to go from about 8:14 to 18:37 and KVM to go from 7:42 to 38:36. Regardless of the source of the IO performance problems, the effect was dramatic which is why I'm assuming that it's disk IO that's XP's problem. However I'm willing to concede that this is just a guess, it could be any number of other factors as many posters have pointed out. My original point was that if you are going to shell out for an expensive simulator like NC, VCS or Questa, you shouldn't cripple it by running on Windows.Article: 133220
On Fri, 20 Jun 2008 10:16:22 -0700, Stephen Williams wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > General Schvantzkopf wrote: > | I haven't been able to get Icarus to work, it's not complete enough to > | run any of our testbenches. We aren't doing anything fancy, in fact > all | of our code is strict Verilog 95 it's not even 2001. > > Current snapshots are much improved, and bug reports are welcomed. > > - -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v2.0.4-svn0 (GNU/Linux) Comment: Using GnuPG with SUSE - > http://enigmail.mozdev.org > > iD8DBQFIW+XmrPt1Sc2b3ikRAtL9AKCykWIDYFWQkNqwfjcAJUgXewEa0wCgxqwt > 6U/NtBgPoBg4Y7aF5Ki6NsY= > =YODt > -----END PGP SIGNATURE----- I used the version that was in the F9 repositories which is 0.9, are the current snapshots significantly better than that one?Article: 133221
On Jun 20, 11:21 am, General Schvantzkopf <schvantzk...@yahoo.com> wrote: > Regardless of the source of the IO performance problems, the > effect was dramatic which is why I'm assuming that it's disk IO that's > XP's problem. However I'm willing to concede that this is just a guess, > it could be any number of other factors as many posters have pointed out. > My original point was that if you are going to shell out for an expensive > simulator like NC, VCS or Questa, you shouldn't cripple it by running on > Windows. My tests indicate that the virtual memory manager in windows causes large simulations to run at 10% of the speed of a Linux/Unix/Solaris box. Which validates your original point. G.Article: 133222
On Jun 19, 2:48 am, Saransh <mehrotrasara...@gmail.com> wrote:
> Hi all,
>
> When I do Generate Netlist in Xilinx 9.2i, I get the following error
> -
>
> -------------------------
> ./synthesis.sh: line 2: $'\r': command not found
> ./synthesis.sh: line 4: $'\r': command not found
> ./synthesis.sh: line 6: $'\r': command not found
> ./synthesis.sh: line 8: $'\r': command not found
>
> ERROR:Xst:1688 - Unknown option for -intstyle switch.
> ./synthesis.sh: line 17: syntax error: unexpected end of file
> make: *** [implementation/system.ngc] Error 2
> Done!
>
> ---------------------------
>
> Could anyone please help me out in this matter.
Hi saransh,
In ISE did u add the files manually or did u create
a script file ..._r is for recursion.(Ex: add wave -r /all) adds all
the waves.It would be gr8 if u can post ur script file , I guess its a
script file error.....
-Mahesh
Article: 133223On Fri, 20 Jun 2008 01:18:19 -0700 (PDT), andy730215@gmail.com wrote: >hi all: > I have a question about stratix II .An oscillator must drive a >constant clock frequency to an FPGA pin. The maximum frequency limit >depends on the speed grade of the FPGA. Frequencies of 50 MHz or less >should work for most boards.If my oscillator is less than 50 MHz ,how >to work about this system ? >If about PLL ,I want to know how dose PLL work. http://www.amazon.com/Phaselock-Techniques-Floyd-M-Gardner/dp/0471430633/ref=sr_1_2?ie=UTF8&s=books&qid=1214009573&sr=1-2 - BrianArticle: 133224
MikeWhy wrote:
> "Dave" <dave@comteck.com> wrote in message
>>
>> Ahh. The old switcheroo. Jeff wrote about the Tilera TILE64
>> processor and I asked about its availability and price. You decided
>> to give availability and price (sort of) on Nvidia's Tesla GPU card.
>
> Explains why I don't mind top-posting as much as others. :) Didn't
> notice the change in topic.
>
> I also didn't find info on the Tilera. Seriously thinking about ordering
> the C870 here, though.
The Nvidia store lists the C870 as "Available for Backorder" so you may
have a wait to get one. The D870 is in stock and is only $5K. ;-)
Dave
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