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Messages from 133450

Article: 133450
Subject: lwip for FPGA
From: chrisdekoh@gmail.com
Date: Mon, 30 Jun 2008 02:20:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
   I am new to using lwip. I am wondering if you can advice me on the
same.
   I need to transfer data from PC to Microblaze microprocessor on a
Xilinx FPGA board and vice versa as fast as possible. i dun need any
error correction or the overheads like full TCP/IP. I am currently
readin this article to understand about socket programming as an
initial start:

http://cscene.unitycode.org/topics/unix/cs2-13.xml.html

   Here are the questions that I have:

1)   I am stuck at the part in the link above which says
   hp=gethostbyname(servername);a
the code above is more for developing applications on PC. I am looking
for lwip drivers to run on the Microblaze (32bit CPU) on the FPGA.

cos i cannot find a similar function in lwip. any idea how to resolve
this? i have tried looking for equiv functions like getnameinfo(),
getaddrinfo() but these functions will work. :(

2) any other useful links to read for regards to this topic? i have
tried looking at
http://www.xilinx.com/ise/embedded/edk91i_docs/lwip_v2_00_a.pdf

what do i need to purchase to let the sockets running on both PC and
FPGA communicate with each other?

possible to advice me on some documents to point me in the right
direction?

thanks
Chris

Article: 133451
Subject: Re: EDK DMA peripherals?
From: Guru <ales.gorkic@email.si>
Date: Mon, 30 Jun 2008 03:35:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 29, 4:28=A0am, Philipp Hachtmann <hac...@hachti.de> wrote:
> Hi,
>
> I am using an EDK-generated PPC subsystem on a ML403.
> I wonder if it would be complicated to create a peripheral that has high
> =A0 speed master access to the SDRAM. I would like to build a shared
> memory frame buffer. Or are there any other good ways to achieve my
> goal? I don't want to use the onboard SRAM. And block ram is too rare
> and not enough..
>
> Regards,
> Philipp :-)

Hi Phillip,

You already have a frame buffer in EDK 10.1 as a plugin to MPMC3
memory controller.
If it does not fit your requirements you can still modify it.
Otherwise you can download the source from opencores.org
Remember that MPMC offers very high bandwidth.

Cheers,

Guru

Article: 133452
Subject: Re: FPGA based database searching
From: "rponsard@gmail.com" <rponsard@gmail.com>
Date: Mon, 30 Jun 2008 04:02:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 27, 7:52=A0pm, Chris Maryan <kmar...@gmail.com> wrote:
> On Jun 27, 11:05=A0am, "Norman Bollmann" <wirdnichtgele...@gmx.net>
> wrote:
>
> > Thank you very much for your feedback, so far!
>
see AMMASS project
there was a demo

> > Oh my.... I'm sorry. That was definitely a spelling mistake: it's suppo=
sed
> > to be "26290144 elements". Sorry 'bout that!
>
> > Regards
>
> > Norman Bollmann
>
> Even with 26M elements to search, as long as they're only 16bits,
> that's still only 65k choices. A hash table based thing as someone
> else pointed out would be a good option.
>
> Can you give some details about the search you need to perform?
>
> Chris


Article: 133453
Subject: Re: FPGA based database searching
From: "rponsard@gmail.com" <rponsard@gmail.com>
Date: Mon, 30 Jun 2008 04:03:40 -0700 (PDT)
Links: << >>  << T >>  << A >>

see AMMASS project
there was a demo
at IP07 grenoble http://www.design-reuse.com/ip07

Article: 133454
Subject: EDK question
From: fmostafa <fatma.abouelella@ugent.be>
Date: Mon, 30 Jun 2008 04:04:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi everybody,

I am using PPC to configure number of  LUTs  using HWICAP, my question
is , Is it possible to generate an interrupt internally according to a
change in  register value , as i want to do  new configuration
depending on this value?

thanks
Fatma

Article: 133455
Subject: Re: arithmetic problem
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Mon, 30 Jun 2008 12:17:32 +0100
Links: << >>  << T >>  << A >>
On Sun, 29 Jun 2008 20:30:30 +0200, Thorsten Kiefer
<webmaster@nillakaes.de> wrote:

>Hi,
>the following code :
>
>library IEEE;
>use IEEE.STD_LOGIC_1164.ALL;
>use IEEE.numeric_std.ALL;
>...
>rnext.addr <= std_logic_vector(unsigned(rreg.addr) + 1);
>...
>
>yields the following error :
>Line 140. Expression in type conversion to std_logic_vector has 3 possible
>definitions in this scope, for example, UNSIGNED and UNSIGNED.
>
>What can I do ?

Declare rnext.addr and rreg.addr as unsigned, and write

rnext.addr <= rreg.addr + 1;

In my experience, if you're fighting the type system, you're probably
working at the wrong level of abstraction.

Addresses usually have the semantics of unsigned numbers (with the
possible exception of bit-twiddling address reordering for FFTs) so why
not use unsigned types directly? 

Only when feeding the address to an external memory do I convert its
type to std_logic_vector. (Where I instantiate internal memories I have
to do the same; I use a wrapper for these to hide the instantiated
component anyway to improve portability; the conversion happens there)

- Brian

Article: 133456
Subject: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
From: timinganalyzer <timinganalyzer@gmail.com>
Date: Mon, 30 Jun 2008 05:50:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 29, 11:36 pm, mahesh <mahesh...@gmail.com> wrote:
> On Jun 29, 5:54 pm, timinganalyzer <timinganaly...@gmail.com> wrote:
>
>
>
> > Hello All,
>
> > A new version beta 0.85 is now available.  The following changes and
> > additions have occurred.
>
> > 1 Quickly add previously used Delays and Constraints from pop-up menu
> > 2 The current state is inverted automatically when adding new pulse if
> > the newstate in the
> >    toolbar is the same as the current state in the signal.
> > 3 Keystroke shortcuts for all the signal state buttons in toolbar.
> > Hover over button to see keystrokes.
> > 4 Signals can now use text values for next state.  This is useful when
> > labels are needed in digital signals.
> > 5 Moving text and edges by mouse drags now use undo and redo
> > 6 Should work with JRE1.5 or newer
>
> > You can download the Free Edition now and read all about the
> > TimingAnalyzer at:
>
> >www.timing-diagrams.com
>
> Hi,
>      I tried to install it on Vista Basic.But facing difficulty in
> installing.I did install the JRE.when I run the timinganalyzer.jar exe
> file It pops me a message saying main class not found exiting !!
>      Could u pls help me in fixing the problem ...ur help will be
> appreciated
>
> Thanks in advance,
> hesh

Can you tell what version of Java you are using?  I have used beta
0.85
with JRE1.5.

If you bring up a dos window,  enter

java -jar TimingAnalyzer.jar

This will report the OS,  Java version,  ....

Thanks,  Dan

Article: 133457
Subject: Re: Standard forms for Karnaugh maps?
From: Andy <jonesandy@comcast.net>
Date: Mon, 30 Jun 2008 06:50:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 28, 3:08 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> KJ wrote:
> > "General Schvantzkopf" <schvantzk...@yahoo.com> wrote in message
> >news:y-2dnZJNvsTS8vvVnZ2dnUVZ_sjinZ2d@comcast.com...
>
> >>On Sat, 28 Jun 2008 09:00:28 +0100, Evan Lavelle wrote:
>
> >>>On Sat, 28 Jun 2008 09:00:03 +1200, Jim Granville
> >>><no.s...@designtools.maps.co.nz> wrote:
>
> > <snip>
>
> >>It's been 30 years since I've used Karnaugh maps, they were useful when
> >>the 7400 was state of the art and every gate counted. In that era logic
> >>was necessarily simple so a tool that could minimize a four input equation
> >>was helpful.
>
> > All very true, but Evan's question was explicitly targetted toward people
> > who USE K-maps ("If you use K-maps, which version do you prefer..." from the
> > original post) and his reasons had to do with verification not design (later
> > post).
>
> To answer that question, the Logic minimisation I use, is that built
> into the tools, which will include the tools version of K-Maps, and
> others as well. ie the REPORT files are closely scrutinised.
>
> It is common to look at the tool output, and recode the source, and
> sometimes we have taken one tools output, and pasted into another
> as source code.
>
> Sometimes, the choices made within the tools surprises, and sometimes it
> disappoints....
>
> Where the tools have a blind spot is in 'node creation' to reduce
> total mapped logic (at the expense of some speed). Understandable,
> as that is a LOT more variables in the air.
>
> Sometimes the designer has to help there.
>
> It's a matter of matching the degrees of freedom, to the tools IQ.
>
> In Xilinx flows, fastest and smallest switches sometimes seem to work
> backwards :)
>
> -jg

I rarely use a K map for "logic minimization". Once I got out of
school (some 22 years ago), about the only thing I used them for was
for state-code assignments in state machines with unsynchronized
inputs (guaranteeing gray-code state transitions on those inputs), and
for P-term minimization when using PALs (choosing state assignments to
minimize branches into states with bits set).  With modern FPGAs in
most cases, if you are designing at the k-map level, you are not
taking maximum advantage of the tools. Specifying design behavior at
higher levels of abstraction often leads to correspondingly higher
levels of optimization. But not always...

Another advantage of using higher levels of abstraction is in
debugging and verification. State transition optimization to avoid an
extra register for input synchronization may have been a good idea
when an entire device had only 8 or 10 registers.  But when extra
registers are so darn cheap in an FPGA, it is foolhardy, and not
nearly as easily verified by inspection as simply burning another
register to synchronize the input.

Andy

From webmaster@nillakaes.de Mon Jun 30 08:34:14 2008
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Message-Id: <4868fcf6$0$25952$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Re: arithmetic problem
Newsgroups: comp.arch.fpga
Date: Mon, 30 Jun 2008 17:34:14 +0200
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> 1) Make absolutely sure that you don't have
>      use ieee.std_logic_arith
>    or
>      use ieee.std_logic_[un]signed
>    in the context clauses.
I don't use them ...

> 
> 2) Just as an experiment (I'm not recommending this for real code)
>    try
> 
>     rnext.addr <= std_logic_vector(
>         unsigned'(unsigned(rreg.addr) + 1)
>         );
rnext.addr <= std_logic_vector(
       unsigned'(unsigned(rreg.addr) + to_unsigned(18,1)
      );
works fine.


Regards Thorsten


Article: 133458
Subject: Re: arithmetic problem
From: Dave <dhschetz@gmail.com>
Date: Mon, 30 Jun 2008 09:06:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 30, 11:34 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote:
> > 1) Make absolutely sure that you don't have
> >      use ieee.std_logic_arith
> >    or
> >      use ieee.std_logic_[un]signed
> >    in the context clauses.
>
> I don't use them ...
>
>
>
> > 2) Just as an experiment (I'm not recommending this for real code)
> >    try
>
> >     rnext.addr <= std_logic_vector(
> >         unsigned'(unsigned(rreg.addr) + 1)
> >         );
>
> rnext.addr <= std_logic_vector(
>        unsigned'(unsigned(rreg.addr) + to_unsigned(18,1)
>       );
> works fine.
>
> Regards Thorsten

Do you mean this:

rnext.addr <= std_logic_vector(
        unsigned'(unsigned(rreg.addr) + to_unsigned(1,18);

to_unsigned(18,1) converts the integer 18 to unsigned which is one bit
wide. I think you meant to convert the integer 1 to an unsigned which
is 18 bits wide.

Also, I don't think you need to cast the result of the addition to
unsigned, since the result of the addition of two unsigneds is going
to be an unsigned. There is no ambiguity there.

Dave


Dave

Article: 133459
Subject: Re: Missing the simplest things - Active HDL - Beginners Questions
From: Dave <dhschetz@gmail.com>
Date: Mon, 30 Jun 2008 09:13:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 28, 1:42 pm, Jim Flanagan <jf...@tampaREMOVEbay.rr.com> wrote:
> Guys..
> I am *brand new* to Aldec Active HDL.  What few
> cpld/pals that I have done have been with CUPL.
>
> I've started using ActiveHDL(Student Ver), writing some easy VHDL
> just to get acquainted with both VHDL and the Aldec tool.
> What I don't understand is the integrated implementation
> portion.  If I were to want to do a Altera design, for example,
> do I need to have the Altera toolset installed in order to
> build the jedec file or does the Aldec tool do that also?
> I guess I am at a loss at the point between designing/simulating the
> project and implementation with ActiveHDL.
>
> Help me see the light.
> Thanks,
> Jim

You still need a separate tool to do the synthesis, whether it's
Synplicity or ISE or Quartus. Then, you still need ISE or Quartus even
if you used Synplicity for the synthesis, to do the final place and
route, and build the file to download into the FPGA (bit or pof file).
Aldec will only do simulations, but it does allow you to launch these
other tools from within its GUI. You don't have to, though, you could
launch them yourself if you find Aldec's design flow confusing.

Dave

Article: 133460
Subject: Re: arithmetic problem
From: Andy <jonesandy@comcast.net>
Date: Mon, 30 Jun 2008 10:17:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 30, 11:06 am, Dave <dhsch...@gmail.com> wrote:
> On Jun 30, 11:34 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote:
>
>
>
> > > 1) Make absolutely sure that you don't have
> > >      use ieee.std_logic_arith
> > >    or
> > >      use ieee.std_logic_[un]signed
> > >    in the context clauses.
>
> > I don't use them ...
>
> > > 2) Just as an experiment (I'm not recommending this for real code)
> > >    try
>
> > >     rnext.addr <= std_logic_vector(
> > >         unsigned'(unsigned(rreg.addr) + 1)
> > >         );
>
> > rnext.addr <= std_logic_vector(
> >        unsigned'(unsigned(rreg.addr) + to_unsigned(18,1)
> >       );
> > works fine.
>
> > Regards Thorsten
>
> Do you mean this:
>
> rnext.addr <= std_logic_vector(
>         unsigned'(unsigned(rreg.addr) + to_unsigned(1,18);
>
> to_unsigned(18,1) converts the integer 18 to unsigned which is one bit
> wide. I think you meant to convert the integer 1 to an unsigned which
> is 18 bits wide.
>
> Also, I don't think you need to cast the result of the addition to
> unsigned, since the result of the addition of two unsigneds is going
> to be an unsigned. There is no ambiguity there.
>
> Dave
>
> Dave

You also need not convert the integer to unsigned. Numeric_std "+" is
already defined for unsigned and natural operands (returning
unsigned).

next.addr <= std_logic_vector(unsigned(rreg.addr) + 1);

Andy

Article: 133461
Subject: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
From: mahesh <mahesh.ma@gmail.com>
Date: Mon, 30 Jun 2008 10:21:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 30, 5:50 am, timinganalyzer <timinganaly...@gmail.com> wrote:
> On Jun 29, 11:36 pm, mahesh <mahesh...@gmail.com> wrote:
>
>
>
> > On Jun 29, 5:54 pm, timinganalyzer <timinganaly...@gmail.com> wrote:
>
> > > Hello All,
>
> > > A new version beta 0.85 is now available.  The following changes and
> > > additions have occurred.
>
> > > 1 Quickly add previously used Delays and Constraints from pop-up menu
> > > 2 The current state is inverted automatically when adding new pulse if
> > > the newstate in the
> > >    toolbar is the same as the current state in the signal.
> > > 3 Keystroke shortcuts for all the signal state buttons in toolbar.
> > > Hover over button to see keystrokes.
> > > 4 Signals can now use text values for next state.  This is useful when
> > > labels are needed in digital signals.
> > > 5 Moving text and edges by mouse drags now use undo and redo
> > > 6 Should work with JRE1.5 or newer
>
> > > You can download the Free Edition now and read all about the
> > > TimingAnalyzer at:
>
> > >www.timing-diagrams.com
>
> > Hi,
> >      I tried to install it on Vista Basic.But facing difficulty in
> > installing.I did install the JRE.when I run the timinganalyzer.jar exe
> > file It pops me a message saying main class not found exiting !!
> >      Could u pls help me in fixing the problem ...ur help will be
> > appreciated
>
> > Thanks in advance,
> > hesh
>
> Can you tell what version of Java you are using?  I have used beta
> 0.85
> with JRE1.5.
>
> If you bring up a dos window,  enter
>
> java -jar TimingAnalyzer.jar
>
> This will report the OS,  Java version,  ....
>
> Thanks,  Dan

Hi ,

       I installed java version 1.6.0_06.but unable to run the
analyzer...pls do gimme ur inputs...

Thanks in advance,
hesh




Article: 133462
Subject: Re: arithmetic problem
From: Dave <dhschetz@gmail.com>
Date: Mon, 30 Jun 2008 11:00:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 30, 1:17 pm, Andy <jonesa...@comcast.net> wrote:
> On Jun 30, 11:06 am, Dave <dhsch...@gmail.com> wrote:
>
>
>
> > On Jun 30, 11:34 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote:
>
> > > > 1) Make absolutely sure that you don't have
> > > >      use ieee.std_logic_arith
> > > >    or
> > > >      use ieee.std_logic_[un]signed
> > > >    in the context clauses.
>
> > > I don't use them ...
>
> > > > 2) Just as an experiment (I'm not recommending this for real code)
> > > >    try
>
> > > >     rnext.addr <= std_logic_vector(
> > > >         unsigned'(unsigned(rreg.addr) + 1)
> > > >         );
>
> > > rnext.addr <= std_logic_vector(
> > >        unsigned'(unsigned(rreg.addr) + to_unsigned(18,1)
> > >       );
> > > works fine.
>
> > > Regards Thorsten
>
> > Do you mean this:
>
> > rnext.addr <= std_logic_vector(
> >         unsigned'(unsigned(rreg.addr) + to_unsigned(1,18);
>
> > to_unsigned(18,1) converts the integer 18 to unsigned which is one bit
> > wide. I think you meant to convert the integer 1 to an unsigned which
> > is 18 bits wide.
>
> > Also, I don't think you need to cast the result of the addition to
> > unsigned, since the result of the addition of two unsigneds is going
> > to be an unsigned. There is no ambiguity there.
>
> > Dave
>
> > Dave
>
> You also need not convert the integer to unsigned. Numeric_std "+" is
> already defined for unsigned and natural operands (returning
> unsigned).
>
> next.addr <= std_logic_vector(unsigned(rreg.addr) + 1);
>
> Andy

Even though Andy's suggestion is the same as in the original post,
he's right. This problem shouldn't be happening if you're using
numeric_std, and not using std_logic_arith, std_logic_signed, or
std_logic_unsigned. I would re-check your code to make sure those
libraries aren't in there. If you're sure, I'd be interested to know
what tool it is that's giving you this error.

The problem stems from the fact that std_logic_arith has two "+"
functions for each possible combination of input argument types: one
which has a result of type std_logic_vector, and one which has a
result of either signed or unsigned (depending on the input argument
types). the compiler doesn't know which one to use. Numeric_std
doesn't have this problem, since it only defines the "+" function once
for each possible input argument type combination. If, however, you
were to use both numeric_std and std_logic_arith, then the ambiguity
increases, since there are now 3 options: the two from
std_logic_arith, and the one from numeric_std. I notice that your
error statement mentions three possibilities...

Dave

Article: 133463
Subject: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
From: timinganalyzer <timinganalyzer@gmail.com>
Date: Mon, 30 Jun 2008 11:00:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 30, 1:21 pm, mahesh <mahesh...@gmail.com> wrote:
> On Jun 30, 5:50 am, timinganalyzer <timinganaly...@gmail.com> wrote:
>
>
>
> > On Jun 29, 11:36 pm, mahesh <mahesh...@gmail.com> wrote:
>
> > > On Jun 29, 5:54 pm, timinganalyzer <timinganaly...@gmail.com> wrote:
>
> > > > Hello All,
>
> > > > A new version beta 0.85 is now available.  The following changes and
> > > > additions have occurred.
>
> > > > 1 Quickly add previously used Delays and Constraints from pop-up menu
> > > > 2 The current state is inverted automatically when adding new pulse if
> > > > the newstate in the
> > > >    toolbar is the same as the current state in the signal.
> > > > 3 Keystroke shortcuts for all the signal state buttons in toolbar.
> > > > Hover over button to see keystrokes.
> > > > 4 Signals can now use text values for next state.  This is useful when
> > > > labels are needed in digital signals.
> > > > 5 Moving text and edges by mouse drags now use undo and redo
> > > > 6 Should work with JRE1.5 or newer
>
> > > > You can download the Free Edition now and read all about the
> > > > TimingAnalyzer at:
>
> > > >www.timing-diagrams.com
>
> > > Hi,
> > >      I tried to install it on Vista Basic.But facing difficulty in
> > > installing.I did install the JRE.when I run the timinganalyzer.jar exe
> > > file It pops me a message saying main class not found exiting !!
> > >      Could u pls help me in fixing the problem ...ur help will be
> > > appreciated
>
> > > Thanks in advance,
> > > hesh
>
> > Can you tell what version of Java you are using?  I have used beta
> > 0.85
> > with JRE1.5.
>
> > If you bring up a dos window,  enter
>
> > java -jar TimingAnalyzer.jar
>
> > This will report the OS,  Java version,  ....
>
> > Thanks,  Dan
>
> Hi ,
>
>        I installed java version 1.6.0_06.but unable to run the
> analyzer...pls do gimme ur inputs...
>
> Thanks in advance,
> hesh

Hello Hesh,

Maybe somehow the the zip file you downloaded was corrupted?  The file
size is 5,170KB.
When you extract the zip file,  you should see the directory structure
shown below

 c:\Apps\TimingAnalyzer_bxx dir
          TimingAnalyzer.jar     --   The executable program
          docs dir               --   html help files required by
program
          images dir             --   images required by program
          scripts dir            --   user scripts
          themes dir             --   look and feel themes
          pics dir               --   saved images of example files
          examples dir           --   timing diagram example files
          settings dir           --   default and user
settings

If your extracted directory structure and the size the program looks
correct, then do
the following and let me know the results.

Open dos window.
cd to TimingAnalyzer_b85
java -jar TimingAnalyzer.jar

Copy the output shown in the dos window and send that to me.
Let me know how you make out.

Thanks,
Dan

Article: 133464
Subject: on FRAME_ECC_VIRTEX4 functionality
From: rha_x@yahoo.com
Date: Mon, 30 Jun 2008 12:56:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,
I have two questions:
1.- On the meaning of the syndrome word: Virtex-4 Libraries Guide for
HDL Designs says that syndrome(11) = 0 means there is a one bit error
and that syndrome(10 downto 0) indicates the error position (pag 94).
However, Virtex 4 FPGA Configuration User Guide (pag 75, latest
version, april 2008) says that syndrome(11) = 0 means there is more
than one bit error and that syndrome(10 downto 0) is meaningless. Does
anybody knows which one is correct?
2.- If my design uses LUTRAMs, I am suppose to set the GLUTMASK_B bit
to 0 for active readback. By doing this I'll readback all 0's from the
bits corresponding to LUTRAMs and I'll avoid any kind of corruption
while performing an active readback. This means that whatever I'll be
reading back will not be the original bitstream data since the LUTRAM
bits are masked. Thus FRAME_ECC_VIRTEX4 will signal an error with
every frame readback. Am I right in this assumption? Does anybody have
had an experience with this?
Any comment would be appreciated,
Thanks,
Alonzo.

Article: 133465
Subject: Re: on FRAME_ECC_VIRTEX4 functionality
From: austin <austin@xilinx.com>
Date: Mon, 30 Jun 2008 13:23:08 -0700
Links: << >>  << T >>  << A >>
>From pages 75, and 76:

http://www.xilinx.com/support/documentation/user_guides/ug071.pdf

S[11] = 0, S[10:0] = 0: no error.

S[11] = 1, S[10:0] ? 0: single bit (SED) error; S[10:0] denotes location
of bit to patch (indirectly).

S[11] = 1, S[10:0] = 0: single-bit error; syndrome bit is in error.

S[11] = 0, S[10:0] ? 0: double-bit error, not correctable.



So, if the MSB (bit 11) equals 1, there is a correctable error (and the
bits 10:0 are the indirect location of the bit to flip, or if bits
10:0=0, the error bit itself is in error [ bits 10:0 defined as from 704
= first bit of frame, to 2047 the last bit in the frame]).

If the MSB is 0, and the location bits 10:0 are non-zero, then there is
a multiple bit hit (uncorrectable).

So, for example:
100000000001 -> 640 (bit 0 of syndrome in error)
100000000010 -> 641
100000000100 -> 642
100000001000 -> 643
100000010000 -> 644
100000100000 -> 645
100001000000 -> 646
100010000000 -> 647
100100000000 -> 648
101000000000 -> 649
110000000000 -> 650
100000000000 -> 651 (bit 11 of syndrome in error)

all indicate an error in a syndrome bit (there are 11 syndrome bits,
which you can correct, too).

Austin





rha_x@yahoo.com wrote:
> Hi all,
> I have two questions:
> 1.- On the meaning of the syndrome word: Virtex-4 Libraries Guide for
> HDL Designs says that syndrome(11) = 0 means there is a one bit error
> and that syndrome(10 downto 0) indicates the error position (pag 94).
> However, Virtex 4 FPGA Configuration User Guide (pag 75, latest
> version, april 2008) says that syndrome(11) = 0 means there is more
> than one bit error and that syndrome(10 downto 0) is meaningless. Does
> anybody knows which one is correct?
> 2.- If my design uses LUTRAMs, I am suppose to set the GLUTMASK_B bit
> to 0 for active readback. By doing this I'll readback all 0's from the
> bits corresponding to LUTRAMs and I'll avoid any kind of corruption
> while performing an active readback. This means that whatever I'll be
> reading back will not be the original bitstream data since the LUTRAM
> bits are masked. Thus FRAME_ECC_VIRTEX4 will signal an error with
> every frame readback. Am I right in this assumption? Does anybody have
> had an experience with this?
> Any comment would be appreciated,
> Thanks,
> Alonzo.

Article: 133466
Subject: Re: on FRAME_ECC_VIRTEX4 functionality
From: austin <austin@xilinx.com>
Date: Mon, 30 Jun 2008 13:25:45 -0700
Links: << >>  << T >>  << A >>
If a LUTRAM is used for SRL 16/(32) or for LUTRAM (LUTROM), then the
GLUT_Mask bit is set for that LUT, and FRAME_ECC will not include those
LUT contents (masked for readback).  All other bits in that frame are
part of the FRAME_ECC, however.



And, yes, the bitstream you read back is not the bitstream you put in.

Austin

Article: 133467
Subject: What is TIEOFF_X0Y31
From: chestnut <adam0818@gmail.com>
Date: Mon, 30 Jun 2008 13:49:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I ran into a problem which is related to TIEOFF_X0Y31. I opened
FPGA_Editor and see such sites around Xilinx Virtex5. i am wondering
what's this site for? I googled and could not get any infos.

Thank you,

Adam

Article: 133468
Subject: Re: on FRAME_ECC_VIRTEX4 functionality
From: austin <austin@xilinx.com>
Date: Mon, 30 Jun 2008 13:52:05 -0700
Links: << >>  << T >>  << A >>
And,

I did note inconsistency with the software manual (and reported it to
tech pubs).

Since I am a "hardware guru" and I know that we write the manuals
(first), I have to think the software guide is incorrect.

Perhaps that isn't fair, I also know that a '1' in bit 11 indicates an
error when the syndrome is non-zero with the location of the bit in
error offset by 704.

Austin

Article: 133469
Subject: Re: on FRAME_ECC_VIRTEX4 functionality
From: alonzo <rha_x@yahoo.com>
Date: Mon, 30 Jun 2008 13:52:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jun 30, 2:25 pm, austin <aus...@xilinx.com> wrote:
> If a LUTRAM is used for SRL 16/(32) or for LUTRAM (LUTROM), then the
> GLUT_Mask bit is set for that LUT, and FRAME_ECC will not include those
> LUT contents (masked for readback).  All other bits in that frame are
> part of the FRAME_ECC, however.
>
> And, yes, the bitstream you read back is not the bitstream you put in.
>
> Austin

Hi Austin,
Interesting. I tough FRAME_ECC takes in consideration the ECC bits
created during the bitstream generation. If the LUTRAM bits are not
taken into account, wouldn't the ECC calculation by FRAME_ECC fail
(signal an error). Anyways, I am testing the idea just now. Let's see
what happens. I'll post my results.

Thank you for your answer.
Alonzo.

Article: 133470
Subject: Re: FIR filter with integer coefficients
From: alonzo <rha_x@yahoo.com>
Date: Mon, 30 Jun 2008 14:32:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi Raj,
This is correct. There is well know result that relates the number of
bits you use for quantization with the level of noise added to your
signal (about 6dB per bit). Note that quantizing your filter
coefficients will result in a completely different filter. There are
implementations that are less sensitive to coefficient quantizations
than others. Particularly, FIRs are better than IIRs in that sense.
Check a DSP book on filters theory. You will find your answers there.
Alonzo.


. I think it is about 6dB per bit. But don't quote me on that. Check
any DSP book.
On Jun 30, 12:30 am, rajesho...@yahoo.co.in wrote:
> Hai,
>
> Can i implement FIR filter in FPGA using fixed point number..
>
> I referred various FIR filter implementation in FPGA all have used
> integer coefficients for their implementation and i am interested to
> know the difficulties of using fixed point numbers.I knew fixed point
> numbers utilize more hardware.
>
> I understand fixed point number is scaled and rounded to get integer
> values from various tools(FDAtool) hence some  information will
> lost..Ultimately this will alter the filter
> response(cutoff,passband,stopband)
>
> am i correct?
>
> if it is possible to implement in fixed point can anyone compare the
> accuracy of integer FIR implementation and fixed point implementation?
>
> pls clarify ..
>
> regards,
> raj


Article: 133471
Subject: Re: What is TIEOFF_X0Y31
From: austin <austin@xilinx.com>
Date: Mon, 30 Jun 2008 14:55:11 -0700
Links: << >>  << T >>  << A >>
Adam,

There are tie-off pins for the TEMAC, the 440PPC, and other blocks.
Which tie-off is this associated with?

Austin

Article: 133472
Subject: Design of a BFSK transmitter/receiver using Xilinx System Generator
From: kvoskaki@nps.edu
Date: Mon, 30 Jun 2008 19:35:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
I would like someone to comment my BFSK design as I am a student and
not much experienced.

Article: 133473
Subject: Translate problem
From: Zhane <me75@hotmail.com>
Date: Mon, 30 Jun 2008 19:43:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
when i try to translate it, it tells me this



ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s)
'DCM_SP_INST'
   in the design.  To suppress this error specify the correct instance
name or
   remove the constraint.



my top.vhd, make use of a component from clockmanager.vhd ...inside
clockmanager.vhd has




   DCM_SP_INST : DCM_SP
   generic map( CLK_FEEDBACK => "1X",
            CLKDV_DIVIDE => 2.0,
            CLKFX_DIVIDE => 1,
            CLKFX_MULTIPLY => 2,
            CLKIN_DIVIDE_BY_2 => FALSE,
            CLKIN_PERIOD => 20.000,
            CLKOUT_PHASE_SHIFT => "NONE",
            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE => "LOW",
            DLL_FREQUENCY_MODE => "LOW",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF => x"C080",
            PHASE_SHIFT => 0,
            STARTUP_WAIT => FALSE)



under its architecture



what's wrong huh?

Article: 133474
Subject: Re: Design of a BFSK transmitter/receiver using Xilinx System Generator
From: Frank Buss <fb@frank-buss.de>
Date: Tue, 1 Jul 2008 04:58:29 +0200
Links: << >>  << T >>  << A >>
kvoskaki@nps.edu wrote:

> I would like someone to comment my BFSK design as I am a student and
> not much experienced.

We can try it. Please upload it to some web host (blog, free web hosting
etc.), if it is long and post the link, or post the code (assuming you are
using Verilog or VHDL) in this newsgroup, if it is not too long.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de



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