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> Tried already. I can program/erase the flash with no problems. Readback too ? >> Try to bypass the flash perhaps disconnect TDO and solder a wire TDI -> >> TDO). > > This is not easy. Both chips are BGAs and the board is 14 layers... Oops. I'm really grateful I put that via on the JTAG signals... because before I bypassed the flash it failed... this is entirely the fault of my crummy cable I think, but I'm too cheap to get a real JTAG cable ;) >> You can also try to make a super simple bitstream like a LED blinker >> with >> all pins tristated except the LED. > > Yeah, I guess that's the next step... Sigh... Rant : Why is it that the very complicated things like FPGAs, work the first time, but the simple things, like JTAG, don't ?Article: 132976
Well, I think I have found the problem. It looks as the EDK portion of my design hasn't got updated properly. FX40 has 2 PPC cores vs. 1 in FX20. I forgot to include the second PPC in the chain and it never complained. Fixing it now... /MikhailArticle: 132977
Link for Joining the FPGA/CPLD Design Group on LinkedIn http://www.linkedin.com/e/gis/56713/3CC3BF77FD22Article: 132978
On Jun 11, 12:20 am, Henry Wong <he...@stuffedcow.net.nospam> wrote: > If anyone is curious, there is a newly-removed feature in 8.0: Parallel > compiles have been disabled in Web Edition. That's not quite correct. I have set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 in my .qsf file and indeed it uses them. I find this in my fitter report: ... Info: Parallel compilation is enabled and will use up to 2 processors ... Info: Parallel compilation was enabled and used an average of 1.1 processors and a maximum of 2 processors out of 2 processors allo wed Furthermore, version 8.0 enables the use of multiple parallel local runs for DSE, thus taking advantages are all the core you could possible have. Version 8.0 is also a bit faster. Oddly, some designs took a slight Fmax hit with 8.0, but I haven't found a consistent pattern. TommyArticle: 132979
hi all....
i use xilinx EDK 9.1i. i'm trying to use opb EMAC....
when i run libgen i get this error:
"Running system level Update ...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Sourcing tcl file
C:/EDK/hw/XilinxProcessorIPLib/pcores/intc_core_v1_00_c/data/
intc_core_v2_1_0.tc
l ...
Check platform configuration ...
INFO:MDT - IPNAME:opb_ethernet INSTANCE:Ethernet_MAC - C:\trials
\system.mhs line
132 - This design requires design constraints to guarantee
performance.
Please refer to the opb_ethernet_v1_02_a data sheet for details.
The OPB Bus clock frequency must be greater than or equal to 65 MHz
for 100
Mbs Ethernet operation and greater than or equal to 6.5 MHz for 10
Mbs
Ethernet operation.
INFO:coreutil - License for component <opb_ethernet_v1> not found.
You may use the customization GUI for this component but you will
not be able to generate any implementation or simulation files.
For license installation help, please visit:
www.xilinx.com/ipcenter/ip_licensing_help.htm
For ordering information, please refer to the
product page for this component on www.xilinx.com
FLEXlm Error: No such feature exists (-5,21)
ERROR:MDT - IPNAME:opb_ethernet INSTANCE:Ethernet_MAC - C:\trials
\system.mhs
line 132 - invalid license or no license found!
IPNAME:plb_v34 INSTANCE:plb - C:\trials\system.mhs line 88 - 2
master(s) : 2
slave(s)
IPNAME:opb_v20 INSTANCE:opb - C:\trials\system.mhs line 98 - 1
master(s) : 4
slave(s)
ERROR:MDT - Errors occured while creating Hardware System"
from what i've been told, the evaluation licence for the EMAC IP core
can be used to run the Ethernet MAC for a few hours.... why do i get
this error, and more importantly, what do i do to generate libraries?
pl reply asap
thanks in advance
vikram
Article: 132980but i'm supposed to work until the 2nd layer i.e data link layer...so i'll only be needing MAc addresses right?Article: 132981
Hi Morphiend, thanks for your reply. Unfortunately I've got absolutely no experience with the Microblaze oder PowerPC stuff. So would it be possible to provide me with an example design? I'll promise not to use it in my design, I'd just like to have a look at it to learn how to deal with integrated processors in combination with the external FLASH. Really appreciate your support! Joe "morphiend" <morphiend@gmail.com> schrieb im Newsbeitrag news:ffc5ef67-f250-4466-96c6-f41fec730798@x41g2000hsb.googlegroups.com... > On Jun 6, 11:42 am, "Denkedran Joe" <denkedran...@googlemail.com> > wrote: >> Hi, >> >> I'd like to use an Intel StrataFlash Memory 28F320J3A with my Virtex4 >> FPGA >> and write / read data from it. Is there a ready-to-use core available to >> communicate with the Flash or am I supposed to start from the scratch, >> writing VHDL code line by line. >> >> Does anybody know how complicated this can get? Is it something >> sophisticated or just "line production"..?! ;-) >> >> Greetz >> >> Joe > > If you have EDK, there is a core readily available with it: the EMC: > External Memory Controller. It's worked flawlessly for every external > discrete flash part I've used it with. > > -- MikeArticle: 132982
Hi, There are reference designs available from Xilinx, here's just one example: http://www.xilinx.com/products/boards/ml403/reference_designs.htm Regards, -- Hauke D On Jun 12, 10:10 am, "Denkedran Joe" <denkedran...@googlemail.com> wrote: > Hi Morphiend, > > thanks for your reply. Unfortunately I've got absolutely no experience with > the Microblaze oder PowerPC stuff. So would it be possible to provide me > with an example design? I'll promise not to use it in my design, I'd just > like to have a look at it to learn how to deal with integrated processors in > combination with the external FLASH. > > Really appreciate your support! > > JoeArticle: 132983
"PFC" <lists@peufeu.com> wrote in message news:op.uclqjtafcigqcu@apollo13.peufeu.com... > > Rant : Why is it that the very complicated things like FPGAs, work the > first time, but the simple things, like JTAG, don't ? It's perhaps because some designers think that because JTAG is a 'slow' bus compared to the hundreds of MHz on the other I/O pins, they don't do proper SI design on the JTAG signals. They think it's a 'simple thing' to just wire it up. If they do the simulation, it works first time, every time. HTH., Syms.Article: 132984
> It's perhaps because some designers think that because JTAG is a 'slow' > bus > compared to the hundreds of MHz on the other I/O pins, they don't do > proper > SI design on the JTAG signals. They think it's a 'simple thing' to just > wire > it up. If they do the simulation, it works first time, every time. > HTH., Syms. I looked into that, but the SI simulation software is "slightly" pricey for a hobbyist ;) (not to mention where to find the models for the cable and the JTAG adapter) so I used a trace impedance calculator and tried to match with the stated impedance in the ribbon cable's datasheet, minimize stubs, insert source termination on TDO, etc, yet I still have problems sometimes though. Configuration works about 95% of the times so I let it be... I suspect double clocking on TCK yet the waveforms look good on the scope (but it's only a 100 MHz analog scope so perhaps I don't see what happens). As I said I think the culprit is my crummy Xilinx parallel III clone from Trenz... but it was cheap... too cheap perhaps !Article: 132985
PFC wrote: > > I looked into that, but the SI simulation software is "slightly" > pricey for a hobbyist ;) (not to mention where to find the models for > the cable and the JTAG adapter) so I used a trace impedance > calculator and tried to match with the stated impedance in the ribbon > cable's datasheet, minimize stubs, insert source termination on TDO, > etc, yet I still have problems sometimes though. Configuration works > about 95% of the times so I let it be... I suspect double clocking on > TCK yet the waveforms look good on the scope (but it's only a 100 MHz > analog scope so perhaps I don't see what happens). > As I said I think the culprit is my crummy Xilinx parallel III clone > from Trenz... but it was cheap... too cheap perhaps ! Did you source terminate the TCK? It might help. On my boards I've been known to use a NC7NZ34 or somesuch to buffer CCLK/TCK with source termination to each individual destinations. In your ribbon cable, did you make every other conductor ground? Works wonders for reducing crosstalk. Make sure you connect all the grounds at both ends of the ribbon cable. Ribbon cable is a great invention. It makes excellent speaker cable, BTW. Fits nicely under the carpet! Cheers, Syms.Article: 132986
> Did you source terminate the TCK? It might help. Yep there is a 30R resistor in the JTAG adapter. > On my boards I've been > known to use a NC7NZ34 or somesuch to buffer CCLK/TCK with source > termination to each individual destinations. I was thinking of doing that next time, thanks for the chip reference, it looks perfect for the purpose. > In your ribbon cable, did you make every other conductor ground? Works > wonders for reducing crosstalk. Make sure you connect all the grounds at > both ends of the ribbon cable. Of course. Sharing a single ground pin between signals in a flat cable is... evil ;) > Ribbon cable is a great invention. It makes excellent speaker cable, BTW. > Fits nicely under the carpet! A bit high L/C, but yeah. So does Cat5... (but it doesn't go under the carpet)Article: 132987
Hai, Can anyone explain how FIR filter implemented in real time application....Wat is the role of software supporting the hardware??? regards, faza On Jun 11, 2:41=A0am, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > "faza" <fazulu.v...@gmail.com> wrote in message > > news:f12c9aaf-9935-4571-8b11-6333b534b37e@f24g2000prh.googlegroups.com... > I am planning to support 256-taps with direct > =A0form FIR filter ... > =3D=3D=3D=3D=3D=3D > The question really was to your motivations and design goals. Possible > answers might be: > > "I read somewhere that I could." > "I want to build an 8-channel, 16-band graphic equalizer for my home > theater." > "To make a brick wall filter for my sub-woofer." > "To disguise my voice when I call co-workers in the middle of the night." > "I love karaoke." > > In any case, the background and specifics fill multiple chapters in > textbooks. I don't expect anyone can condense it down into a digestible > newsgroup message for you. The best you'll get is a reading list. Google i= s > your friend there. > > > > I have tested my design with inputs as =A0impulse test,step > test,sine,square,sawtooth,pulse and white noise...I dont know how to > check for overflow?wat is the test case? > > =3D=3D=3D=3D=3D=3D > Quantization effects is a whole chapter in itself.Article: 132988
faza wrote: > Hai, > > Can anyone explain how FIR filter implemented in real time > application....Wat is the role of software supporting the hardware??? > > regards, > faza > > > Dear faza, You're starting to get slightly irritating now. This won't help you get answers to your queries. A lot of folks on this newsgroup are willing and able to help people just starting out in the field, but, like God, they like to help those who help themselves. Take your latest post. Why don't you STW before posting? Googling for FIR filter implemented in real time gets nearly 10^6 hits. It may also further your education to read this:- http://catb.org/~esr/faqs/smart-questions.html Please pay particular attention to the section:- http://catb.org/~esr/faqs/smart-questions.html#writewell Spelling 'what' as 'wat' apparently "makes you look like a semi-literate boob" to save one entire keystroke, especially as you piss away the saving by using three question marks when one will do just fine. Finally, here are some feebie DSP books, http://www.dspguru.com/info/books/online.htm this site http://www.xilinx.com/support/documentation/application_notes.htm has at least two app notes about FIR filters in FPGAs, and this site http://andraka.com/ is for when you become more experienced. Now, be a good chap, and go do some reading. HTH., Syms.Article: 132989
>but i'm supposed to work until the 2nd layer i.e data link layer...so >i'll only be needing MAc addresses right? > Assuming that they haven't been mis-edited recently, http://en.wikipedia.org/wiki/Address_Resolution_Protocol and the articles it references should tell you what you need to know...Article: 132990
I get the following error with chipscope analyzer whenever I do the intialize chain. ERROR: Socket Open Failed. localhost/127.0.0.1:50001 localhost java.net.ConnectException: Connection refused ERROR: Failed to detect cable. Try to open a specific cable from the 'JTAG Chain' menu IMPACT is able to initialize the chain successfully. I am trying this after a long time. Before it used to work properly. -DArticle: 132991
Thanks Austin. My confusion now is how to initialize the pci bridge in between the fpga and the pci. AMIRIX provided me with an uboot image which was run by the powerpc . I want to try to implement the design without the powerpc and hence will have to initialize the pci bridge without the powerpc runnng from the host. austin wrote: > ni, > > The Virtex 2 Pro is a FPGA. > > The 405PPC core is programmable. Instantiate it in your design, and you > use it. > > Don't instantiate it in your design, and it is unused. > > It is your choice in your VHDL or verilog before it is placed routed, > and the bitstream created. > > Once you have a bitstream, you need to go back, and redesign for what > you actually want. > > Or, you can create another bitstream, and load that one in after the > first one (use reconfiguration to do task 1, followed by task 2). > > The 405PPC core in in the silicon, so you can not "take it out." All > you are able to do is to either include it in your design, or exlude it > from your design: your choice. > > AustinArticle: 132992
On Jun 12, 8:14 am, ni <nbg2...@gmail.com> wrote: > I get the following error with chipscope analyzer whenever I do the > intialize chain. > ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > localhost > java.net.ConnectException: Connection refused > ERROR: Failed to detect cable. > Try to open a specific cable from the 'JTAG Chain' menu > > IMPACT is able to initialize the chain successfully. It looks like a network connection is failing. Are you sure you are not being blocked by your firewall? Alan NishiokaArticle: 132993
Alan Nishioka wrote: > On Jun 12, 8:14 am, ni <nbg2...@gmail.com> wrote: >> I get the following error with chipscope analyzer whenever I do the >> intialize chain. >> ERROR: Socket Open Failed. localhost/127.0.0.1:50001 >> localhost >> java.net.ConnectException: Connection refused >> ERROR: Failed to detect cable. >> Try to open a specific cable from the 'JTAG Chain' menu >> >> IMPACT is able to initialize the chain successfully. > > It looks like a network connection is failing. Are you sure you are > not being blocked by your firewall? > > Alan Nishioka Hi Alan, I don't think that's it. http://en.wikipedia.org/wiki/Localhost Did the OP try turning his computer off and on again? ;-) Cheers, Syms.Article: 132994
Automotive Temperature +100 deg C+ FPGA's -- who's parts are available from Distributor stock? Am really interested in -40 to +125 deg C solutions that are Automotive grade or Similar --Article: 132995
Tommy Thorn wrote: > On Jun 11, 12:20 am, Henry Wong <he...@stuffedcow.net.nospam> wrote: >> If anyone is curious, there is a newly-removed feature in 8.0: Parallel >> compiles have been disabled in Web Edition. > > That's not quite correct. I have > > set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 > > in my .qsf file and indeed it uses them. I find this in my fitter > report: Indeed. I'd think that's a bug, one I hope won't get fixed. :) I filed a report thinking the GUI setting was broken, and got the response that parallel compiles are now disabled. http://www.altera.com/b/quartus-ii-80.html They've recently buried a line here suggesting you need the subscription edition.Article: 132996
"Symon" <symon_brewer@hotmail.com> wrote in message news:g2r74u$bbm$1@aioe.org... > Spelling 'what' as 'wat' apparently "makes you look like a semi-literate > boob" to save one entire keystroke, especially as you piss away the saving > by using three question marks when one will do just fine. Ironically, it is precisely that which keeps me from writing him off completely. There's an outside chance he's some jr. high school kid feeling his way into the deep end. But, as you say, I'm still waiting for the right questions. > > Finally, here are some feebie DSP books, > http://www.dspguru.com/info/books/online.htm > > this site > http://www.xilinx.com/support/documentation/application_notes.htm > has at least two app notes about FIR filters in FPGAs, > > and this site http://andraka.com/ is for when you become more experienced. > > Now, be a good chap, and go do some reading. > HTH., Syms. > > > > > > > >Article: 132997
Tommy Thorn wrote:
> Version 8.0 is also a bit faster. Oddly, some designs took a slight
> Fmax hit with 8.0, but I haven't found a consistent pattern.
We have seen 9% higher utilization for Q8.0 vs Q7.2 (subscription)
on the same project. I think I'll wait for 8.1.
-- Mike Treseler
Article: 132998Mike Treseler wrote: > We have seen 9% higher utilization for Q8.0 vs Q7.2 (subscription) > on the same project. I think I'll wait for 8.1. Looks like a nice marketing trick: Release a new software version and you can sell bigger FPGAs :-) -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 132999
On Jun 11, 12:26 pm, rickman <gnu...@gmail.com> wrote: > On Jun 8, 10:00 pm, timinganalyzer <timinganaly...@gmail.com> wrote: > > > > > Hello All, > > > A new version beta 0.83 is now available. The following changes and > > additions have occurred. > > > * Improved Image Preview Display. > > * Context sensitive popup menus to edit objects. > > * Path set in image save dialog works. > > * Metric paper sizes added to image preview. > > * Lower case z, and x now work bus value combobox in toolbar. > > * Move signals up and down commands now respect any space in > > diagrams used for Text. > > * Objects attached to any signal being deleted are deleted > > automatically. > > * Save file now includes some more error checking before saving > > objects. > > * Delays can not be added to DigitalClocks. > > > You can download the Free Edition now and read all about the > > TimingAnalyzer at: > > >www.timing-diagrams.com > > > ---------------------------------------------------------------------------------------------------------------------------------------- > > > The TimingAnalyzer can be used to quickly and easily draw timing > > diagrams. Signals, clocks, buses, delays, constraints, and states are > > easily added from the GUI. > > > It can also be used to quickly do a timing analysis and check for > > timing faults. Minimum, typical, and worst case analysis can be > > performed. Delays and constraints are easily specified and changed to > > see if faster clocks or slower parts can be used without any timing > > faults. > > > There are 3 editions planned. The Free Edition(FE), a Standard > > Edition(SE), and the Professional Edition(PE). > > You asked for suggestions... I suggest that you spend some time > working on the docs. I don't mean the full up, detailed manual. I > mean come up with something that lets a beginner produce some simple > diagrams quickly. Leave out the fancy features and just explain the > basics of how this program is intended to be used. I think you feel > the program is simple, but it is not. Maybe once you get the user > over the initial hump, it is easy. But that initial hum is > significant. > > You have several ways of getting documentation or help. I could only > find one that worked. In particular, you have a menu item in the > program that opens a link in the web browser... to an empty page. I > understand that this is a placeholder, but why have a placeholder that > only frustrates the user? Grey out the menu item to anything that is > not implemented or that does not work. No point in having users go > down dead ends. > > Rick The documentation in the application works. Help Menu -> User Manual It is very limited in scope but has the basics. There is also an step by step example. I know the documentation page on the website is empty. I'm looking for help, beta testing and things like documentation. Anyone interested in helping, please let me know. I will try to improve the docs with each new release. Thanks, Dan
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z