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Messages from 132350

Article: 132350
Subject: Re: 1250gbps input on virtex-5
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 22 May 2008 14:44:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 22, 6:13=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> Hi,
>
> we need to input a continous stream of 32 LVDS data bits at 1.25gbps
> per pin into a Virtex-5.
> There is a clock provided for each byte (source synchronous).
>
> There was a news item by Xilinx that says this is possible. But how
> many loops do I need
> to jump through to make it work?
>
> - What speedgrade do we need?
> - Is there a difference in timing between LXT, FXT and SXT for LVDS
> inputs?
> - Are there any constraints regarding the placement of the pins?
>
> Has anyone in this group done speeds like this before?
>
> Thanks,
>
> Kolja Sulimma

Kolja, there is a very good app note (43 pages long) that describes
the design, and its dynamic alignment in gory detail.
This is all based on actual testing of Virtex-5 chips on our
evaluation board. Greg Burton, the applications engineer, drove the
design all the way to 1.4 GHz, where the eye got very small.(see page
25).
Good luck with your design, you are in good hands with this app note,
XAPP855

http://www.xilinx.com/support/documentation/application_notes/xapp855.pdf

Peter Alfke

Article: 132351
Subject: globals
From: uche <uraniumore235@hotmail.com>
Date: Thu, 22 May 2008 16:40:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
I need some help with this one...

Illegal LOC on IPAD symbol "CLK" or BUFGP symbol "CLK_BUFGP"
   (output signal=DONE_OBUF), IPAD-IBUFG should only be LOCed to
GCLKIOB site.

What does that mean ?

Thanks

Article: 132352
Subject: URGENT :problem using Ethernet MAC ip core...
From: vikram <vikram788@gmail.com>
Date: Thu, 22 May 2008 19:29:25 -0700 (PDT)
Links: << >>  << T >>  << A >>
hello

i am using a virtex 2 pro board to implement a communication system,
and want to interface it with my pc (Matlab) via rthernet. for this
purpose, i have acquired a Xilinx Ethernet MAC ip core (OPB). i am new
to this kind of work, and donot know how to use the core. please tell
me, in as simple a way as possible, :

1) what do i get as part of the core? (the hardware descri[tion fi;es
like hdl codes? software drivers to use with an embedded processor?)

2) using Xilinx XPS, how do i use it in my system? (add the core to
project? add as peripheral?)

3) am i required to do any coding to implement this MAC or is
everything available as part of the core?

please reply as soon as possible, and, for my benefit, please keep it
simple.

thanks in advance

vikram

Article: 132353
Subject: Re: asic gate count
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 22 May 2008 22:11:17 -0800
Links: << >>  << T >>  << A >>
vijayant.rutgers@gmail.com wrote:

> I am looking for some tool / ip that can give me approximate gate
> count of mapper/demapper. Any helpful hint is greatly welcome.

The traditional method for ASIC is to divide the number
of transistors by the number of transistors in a 2 input
NAND gate.  For CMOS, that is four.

Good or bad, that is the usual way.

-- glen


Article: 132354
Subject: Re: 1250gbps input on virtex-5
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Fri, 23 May 2008 01:27:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thx. That is exactly what I was looking for. (Actually I need XAPP860)
As I read this we have multiple options:
- use a -3 speedgrade
- use a power supply 5% over nominal voltage with extremely good
regulation
- rely on the fact that the signal quality will be better than what is
used in the application note.

We probably will choose all three options at once. :-)
Are -3 devices available? Our distributor could not give us a quote.

Kolja


On 22 Mai, 23:44, Peter Alfke <pe...@xilinx.com> wrote:
> Kolja, there is a very good app note (43 pages long) that describes
> the design, and its dynamic alignment in gory detail.
> This is all based on actual testing of Virtex-5 chips on our
> evaluation board. Greg Burton, the applications engineer, drove the
> design all the way to 1.4 GHz, where the eye got very small.(see page
> 25).
> Good luck with your design, you are in good hands with this app note,
> XAPP855
>
> http://www.xilinx.com/support/documentation/application_notes/xapp855...
>
> Peter Alfke


Article: 132355
Subject: Re: timing constraint is impossible to meet
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Fri, 23 May 2008 10:13:27 +0100
Links: << >>  << T >>  << A >>
Rob Gaddi <rgaddi@technologyhighland.com> writes:

> HT-Lab wrote:
>> Try this environmental variable before running P&R
>>
>> set XIL_TIMING_ALLOW_IMPOSSIBLE=1
>>
>> Hans
>> www.ht-lab.com
>>
>>
>
> Can I mention the deep and abiding love I have for whoever decided
> that the options to MAP needed to be passed through a combination of
> command line arguments, settings files, and nearly undocumented
> environment variables, with any given setting only accessible through
> one of those? That hasn't complicated my build chain one tiny bit,
> nosireebob.
>

Seconded!

Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 132356
Subject: Re: 1250gbps input on virtex-5
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 23 May 2008 10:37:10 +0100
Links: << >>  << T >>  << A >>
"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message 
news:ffe626f9-7404-4398-a311-6308d9c2a86d@s50g2000hsb.googlegroups.com...
> Thx. That is exactly what I was looking for. (Actually I need XAPP860)
>
Hi Kolja,
Indeed, XAPP860 is a big improvement. In fact, it strikes me that with a 
little work, an initial Rx cal with a training pattern isn't necessary for 
eye alignment and the V5 can dynamically align to random data by comparing 
the outputs of the master and slave ISERDES. Word alignment could be 
achieved by looking for known patterns in the incoming signal, e.g. F628 for 
SONET.
Cheers, Syms. 



Article: 132357
Subject: Re: globals
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 23 May 2008 11:27:52 +0100
Links: << >>  << T >>  << A >>
"uche" <uraniumore235@hotmail.com> wrote in message 
news:2530908c-024f-4c71-9f1d-5d7daa3a2d96@i36g2000prf.googlegroups.com...
>I need some help with this one...
>
> Illegal LOC on IPAD symbol "CLK" or BUFGP symbol "CLK_BUFGP"
>   (output signal=DONE_OBUF), IPAD-IBUFG should only be LOCed to
> GCLKIOB site.
>
> What does that mean ?
>
> Thanks

STFW
http://www.google.com/search?q=Illegal+LOC+on+IPAD+symbol 



Article: 132358
Subject: Re: URGENT :problem using Ethernet MAC ip core...
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 23 May 2008 11:38:34 +0100
Links: << >>  << T >>  << A >>
"vikram" <vikram788@gmail.com> wrote in message 
news:72422d23-86bf-4916-a7ee-ad9fb22185d4@x1g2000prh.googlegroups.com...
> hello
>
> i am using a virtex 2 pro board to implement a communication system,
> and want to interface it with my pc (Matlab) via rthernet. for this
> purpose, i have acquired a Xilinx Ethernet MAC ip core (OPB). i am new
>
blah, blah
>
> vikram

Vikram,
You posted this 4 days ago. I worry that you haven't found a solution for 
your URGENT problem. Perhaps this link would help you.
http://www.xilinx.com/company/contact.htm
You could try calling someone on the telephone. There are folks in India. I 
just hope you don't get put through to some guy with a thick English accent 
that you can barely understand.
HTH., Syms.



Article: 132359
Subject: Software instabilities with EDK 10.01 and PPC405?!??!!!
From: Philipp Hachtmann <hachti@hachti.de>
Date: Fri, 23 May 2008 13:20:43 +0200
Links: << >>  << T >>  << A >>
Hi folks,

I am short before going mad...

I have a Xilinx ML403 board with a Virtex 4 FX12 FPGA sitting on my desk.

I use an EDK generated PPC405 design as a submodule.

My current task is to interface with a simple IIC chip via the Xilinx 
IIC core. That works - from time to time.
My software behaves completely strange - hangs, seems to skip parts, 
runs into Xilinx' assertion stop code, etc...

I use the following libs and drivers:
Xilinx intc, iic, uartlite, xil_printf
libc's printf

I tried to dig into the problem using the Xilinx supplied XMD debugger. 
It looks like I am suffering from "side effects": I have seen data going 
corrupt (function pointers NULLing) while execution is somewhere else.
I have also seen program exception and machine check exeptions in the 
PPC's ESR register :-(
Behavior changes with position of code in memory. Sometimes an inserted 
or removed operation completely changes the behaviour...

So the question is: Does anyone have similar experiences? Is there any 
known corrupt driver code in the last EDK revision?
Am I doing something badly wrong?

If you have some ideas, PLEASE let me know... I can provide more details 
on request.


Thanks a lot,

Philipp :-)




-- 
You have to reboot your computer after powerfail? Haha!
http://h316.hachti.de

Article: 132360
Subject: Re: VHDL document generation utilities
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Fri, 23 May 2008 13:27:21 +0200
Links: << >>  << T >>  << A >>
Mr. Coesel posted on Thu, 27 Mar 2008 17:05:02 GMT:
|---------------------------------------------------------------------|
|"Anyone using such a utility on my watch is fired immediately. Proper|
|documentation describes the idea behind an implementation. Tools like|
|doxygen produce nice looking documents, but the contents of the      |
|documents are useless because the idea behind it all is missing."    |
|---------------------------------------------------------------------|

Do you think that perhaps you overreacted?

Regards,
N. C. P. Gloster

Article: 132361
Subject: Avalon interconnect fabric : arbiter
From: Charles Wagner <charles.wagner@irisa.fr>
Date: Fri, 23 May 2008 13:52:15 +0200
Links: << >>  << T >>  << A >>
Hi all,

I just have two simple questions but I can't find the answer from the 
altera's documents.

Each master port has an integer value of transfer shares (M) wich 
respect to a slave port.
A slave port can declare the minimum number of shares (S) in each round 
robin cycle.

If M<S how many transfers are performed in each round robin cycle ?
Where is this minimum number of shares in SOPC Builder declared ?

Thanks in advance for your help

Article: 132362
Subject: Simple PRNG problem -> clk not recognised as input
From: Dan Arik <DanA@hotmail.com>
Date: Fri, 23 May 2008 13:22:50 +0100
Links: << >>  << T >>  << A >>
Hi

I wanted to sythesize a simple PRNG which is implemented as a LFSR.
However, the problem is that when I debug the implemnetation on the chip
I always get the same random value which are the last two bits of
the tmp varible. So in my case its always 01. Can anyone tell me what I 
am missing? Because in simulation it works. The strange thing is
that ISE 10.1 tells me XST:647: INPUT <clk> is never used. This port 
will be preserved abd left unconnected if it belongs to a top-level 
block. But I have surely connected the clk and also need it in the 
process for the PRNG?

entity Testbench is
             port(
                 clk            : in  std_logic;
		dbg_R0         : inout std_logic;
                 dbg_R1         : inout std_logic
             );
end Testbench;

architecture Behavior of Testbench is

     component PRNG is
		port (
			clk : in std_logic;
			R0  : out std_logic;
			R1  : out std_logic
		);
	 end component;

begin

     --LEFT OUT SOME CODE FOR CHIPSCOPE DEGGUGING

     ARCH_PRNG:PRNG
		port map(
			clk => clk,
			R0  => dbg_R0,
			R1  => dbg_R1
		);

end architecture Behavior;


entity PRNG is
   port (
     clk : in std_logic;
     R0  : out std_logic;
     R1  : out std_logic
   );
end PRNG;

architecture Behavior of PRNG is

begin
   process(clk)
     variable temp : std_logic_vector(7 downto 0) := B"01110101";
   begin
     temp := (temp(1) xor temp(0)) & temp(7 downto 1);
     R0 <= temp(0);
     R1 <= temp(1);
   end process;

end architecture Behavior;

Article: 132363
Subject: Re: Simple PRNG problem -> clk not recognised as input
From: Dan Arik <DanA@hotmail.com>
Date: Fri, 23 May 2008 13:28:40 +0100
Links: << >>  << T >>  << A >>
 > So in my case its always 01. Can anyone tell me what I
> am missing? Because in simulation it works. 

Thats not right, Chipscope tells me that the last two bits
are always 0....

Article: 132364
Subject: Re: Simple PRNG problem -> clk not recognised as input
From: Dan Arik <DanA@hotmail.com>
Date: Fri, 23 May 2008 13:48:16 +0100
Links: << >>  << T >>  << A >>
Dan Arik wrote:
>  > So in my case its always 01. Can anyone tell me what I
>> am missing? Because in simulation it works. 
> 
> Thats not right, Chipscope tells me that the last two bits
> are always 0....

alright, it seems that i have to use the clk signal explicily again
in the process itself that it acitvates....

So if I use a if clk'event and clk='1' then it works

Article: 132365
Subject: HWICAP and BRAM
From: fmostafa <fatma.abouelella@ugent.be>
Date: Fri, 23 May 2008 06:07:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi all,

Iam trying to use HWICAP , as a first test i tried to write to HWICAP
BRAM using  XHwIcap_StorageBufferWrite and read the stored data using
XHwIcap_StorageBufferRead , i noticed that the data read from the bram
is identical to what it was written except in one position, as this
position stuck at a certain value (249) , i don't understand what is
this problem


thanks

Article: 132366
Subject: it doesn't work if increase a little traffic for DMA read.
From: "water9580@yahoo.com" <water9580@yahoo.com>
Date: Fri, 23 May 2008 06:30:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
The unidirection DMA read only or write only of my PCIE NIC controller
V5-based works fine .



However,if DMA read(from host--->ethernet port) is
progress ,additional i send ping packet continuing from Host or
client.the NIC will doesn't work.the send/receive is stoppped.



But,if DMA write(from ethernet --->host) is progress,additional i send
ping packet continuing from Host or client. it still works fine.



who can provide any clue to debug the issue?

Article: 132367
Subject: Re: asic gate count
From: "Mike Lewis" <someone@micrsoft.com>
Date: Fri, 23 May 2008 10:54:08 -0400
Links: << >>  << T >>  << A >>

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message 
news:hvydnRGK27J_zKvVnZ2dnUVZ_uqdnZ2d@comcast.com...
> vijayant.rutgers@gmail.com wrote:
>
>> I am looking for some tool / ip that can give me approximate gate
>> count of mapper/demapper. Any helpful hint is greatly welcome.
>
> The traditional method for ASIC is to divide the number
> of transistors by the number of transistors in a 2 input
> NAND gate.  For CMOS, that is four.
>
> Good or bad, that is the usual way.
>
> -- glen
>

What is your method for determining how many transistors are in the design? 
My synthesis tools only give me area.

Mike 



Article: 132368
Subject: Re: XILINX Ethernet MAC (URGENT...)
From: morphiend <morphiend@gmail.com>
Date: Fri, 23 May 2008 08:05:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 22, 12:19 am, vikram <vikram...@gmail.com> wrote:
> Dear Mike
>
> > If you have the core unlocked, it should show up as a core in the High-
> > Speed Communication 'folder' in the cores tree. In other words, there
> > isn't much you'd have to do to 'import' it into EDK. It should be
> > their auto-magically.- Hide quoted text -
>
> Got that part.... Once the core is in the repository in EDK, do I add
> it to my project through XPS as a peripheral (using the create/import
> peripheral option) or do i use the Add/Edit core option? after this,
> do i just download it to the board?
>
> thanks
> vikram

I don't think you got that part, because it would be the same as using
any other Xilinx-provided core. For me, I just drag it from the
Available Cores list on the left-hand window pane into the System
Assembly in the right-hand window pane. If that doesn't work, I
recommend reading up on how to use EDK. A good starting point is the
EDK reference manual.

Article: 132369
Subject: Re: asic gate count
From: Jon Beniston <jon@beniston.com>
Date: Fri, 23 May 2008 08:05:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
> What is your method for determining how many transistors are in the design?
> My synthesis tools only give me area.

Divide the area of your design by the area of a 2-input NAND with
lowest drive strength * 4.

Cheers,
Jon


Article: 132370
Subject: Re: Simple PRNG problem -> clk not recognised as input
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Fri, 23 May 2008 09:50:28 -0700
Links: << >>  << T >>  << A >>
Dan Arik wrote:
> Hi
> 
> I wanted to sythesize a simple PRNG which is implemented as a LFSR.
> However, the problem is that when I debug the implemnetation on the chip
> I always get the same random value which are the last two bits of
> the tmp varible. So in my case its always 01. Can anyone tell me what I 
> am missing? Because in simulation it works. The strange thing is
> that ISE 10.1 tells me XST:647: INPUT <clk> is never used. This port 
> will be preserved abd left unconnected if it belongs to a top-level 
> block. But I have surely connected the clk and also need it in the 
> process for the PRNG?
> 
> <snip>
> 
> begin
>   process(clk)
>     variable temp : std_logic_vector(7 downto 0) := B"01110101";
>   begin
>     temp := (temp(1) xor temp(0)) & temp(7 downto 1);
>     R0 <= temp(0);
>     R1 <= temp(1);
>   end process;
> 
> end architecture Behavior;

The reason that ISE is telling you that <clk> is never used is that you 
never used the clk.

What you're looking for probably looks more like this:

    process(clk)
      variable temp : std_logic_vector(7 downto 0) := B"01110101";
    begin
      if rising_edge(clk) then
        temp := (temp(1) xor temp(0)) & temp(7 downto 1);
        R0 <= temp(0);
        R1 <= temp(1);
      end if;
    end process;

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 132371
Subject: Re: it doesn't work if increase a little traffic for DMA read.
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Fri, 23 May 2008 09:54:43 -0700
Links: << >>  << T >>  << A >>
water9580@yahoo.com wrote:
> The unidirection DMA read only or write only of my PCIE NIC controller
> V5-based works fine .
> 
> 
> 
> However,if DMA read(from host--->ethernet port) is
> progress ,additional i send ping packet continuing from Host or
> client.the NIC will doesn't work.the send/receive is stoppped.
> 
> 
> 
> But,if DMA write(from ethernet --->host) is progress,additional i send
> ping packet continuing from Host or client. it still works fine.
> 
> 
> 
> who can provide any clue to debug the issue?

Probably someone with any information whatsoever about what hardware 
you're using, how it's wired up, what tools you're trying to implement 
this with, or what cores you're trying to work with.  But who that would 
be is anyone's guess.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 132372
Subject: Xilinx EDK inferred dual port BRAM unconnected clkb
From: mozilla <godzillalad@gmail.com>
Date: Fri, 23 May 2008 10:27:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
As part of an edk peripheral i have inferred 2 dual port BRAMs which
synthesise and simulate correctly

For both BRAMs
port a is controlled by the microblaze
port b is controlled by fsm


BRAM 1 is used for PLB to peripheral communication
in this case the input to port b data_in is never used or assigned

BRAM 2 is used for peripheral to PLB communication
in this case the input to port b *data_out* is never used or assigned




when i import the peripheral into edk  during MAP it gives me the
following error

ERROR:LIT:459 - DATA_WIDTH_B is set to 36 for RAMB16BWER symbol
   "physical_group_plb_pipeline_simulator_0/plb_pipeline_simulator_0/
USER_LOGIC_
   I/read_wrapper_dout<19>/plb_pipeline_simulator_0/
plb_pipeline_simulator_0/USE
   R_LOGIC_I/Inst_pipeline_simulator/Mram_IP2Pipe_BRAM".  This
requires CLKB,
   REGCEB, ENB, RSTB and WEB[0-3] to be connected.
Errors found during logical drc.

Following this error back i noticed when xst is inferring one of the
BRAMS it doesn't connect clkb

 
-----------------------------------------------------------------------
    | ram_type           | Block
 
-----------------------------------------------------------------------
    | Port
A
    |     aspect ratio   | 512-word x 20-bit
    |     mode           | write-first
    |     clkA           | connected to signal <clk>
    |     enA            | connected to signal <read_wrapper_en>
    |     weA            | connected to signal <read_wrapper_we>
    |     addrA          | connected to signal <read_wrapper_add>
    |     diA            | connected to signal <read_wrapper_din>
    |     doA            | connected to signal <read_wrapper_dout>
 
-----------------------------------------------------------------------
    | optimisation       | speed
 
-----------------------------------------------------------------------
    | Port
B
    |     aspect ratio   | 512-word x 20-bit
    |     mode           | write-first
    |     weB            | connected to signal <delta_val>
    |     addrB          | connected to signal <runCnt>
    |     diB            | connected to signal <delta_x>
 
-----------------------------------------------------------------------
    | optimisation       | speed
 
-----------------------------------------------------------------------


So my question

Why does xst not connect clkb to the port b of the second BRAM?


I

Article: 132373
Subject: Re: 1250gbps input on virtex-5
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 23 May 2008 11:08:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 23, 1:27=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> Thx. That is exactly what I was looking for. (Actually I need XAPP860)
> As I read this we have multiple options:
> - use a -3 speedgrade
> - use a power supply 5% over nominal voltage with extremely good
> regulation
> - rely on the fact that the signal quality will be better than what is
> used in the application note.
>
> We probably will choose all three options at once. :-)
> Are -3 devices available? Our distributor could not give us a quote.
>
> Kolja
>
Kolja, I should have referred you to the XAPP860. My oversight...
Regarding -3 devices, they do exist for all the smaller part types,
but not for the largest ( '200 and above).
-2 might be good enough for your application. -3 has a faster clock
distribution, but there is little (if any) difference in the LVDS and
ISERDES structures.
Gru=DF
Peter

Article: 132374
Subject: Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
From: Alan Nishioka <alan@nishioka.com>
Date: Fri, 23 May 2008 12:19:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On May 23, 4:20 am, Philipp Hachtmann <hac...@hachti.de> wrote:
> I have a Xilinx ML403 board with a Virtex 4 FX12 FPGA sitting on my desk.
>
> I use an EDK generated PPC405 design as a submodule.
>
> My current task is to interface with a simple IIC chip via the Xilinx
> IIC core. That works - from time to time.
> My software behaves completely strange - hangs, seems to skip parts,
> runs into Xilinx' assertion stop code, etc...
>
> I tried to dig into the problem using the Xilinx supplied XMD debugger.
> It looks like I am suffering from "side effects": I have seen data going
> corrupt (function pointers NULLing) while execution is somewhere else.
> I have also seen program exception and machine check exeptions in the
> PPC's ESR register :-(
> Behavior changes with position of code in memory. Sometimes an inserted
> or removed operation completely changes the behaviour...

My guess would be that you have a timing error.  Does your design meet
timing?  Do you have a timing specification?

Are you running from external memory?  Can you run a memory test on
it?

Alan Nishioka



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