Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Peter Alfke wrote: (snip) > To re-configure, you must pull down PROG for a certain length of > time,expressed in microseconds.If you use one FPGA output to do this, > you face a dilemma: Once reconfiguration starts, every output is being > 3-stated, which violated the min PRG=Low time requirement.In older > parts, this self-triggering worked reliably "by design", since both > reconfiguration and 3-stating were controlled by a common latch. Once > set, there was no way to stop configuration. Wouldn't a small capacitor hold it low long enough? Though I agree that the latch method sounds even better. -- glenArticle: 132201
Enes Erdin wrote: (snip) > I am looking at VHDL like software- > will be very tiring. If you try to observe some characteristics of the > FPGA's I don't have any idea about it but for me buy a kit and > continue your work on it. You should look at VHDL like hardware in text form. If you look at it like software, you will get confused. -- glenArticle: 132202
The trick is knowing how small.. "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:3fudnQrFX4_ku7PVnZ2dnUVZ_gednZ2d@comcast.com... > > Wouldn't a small capacitor hold it low long enough? >Article: 132203
Are you sure you are doing a Camera Link interface? The interface is a 7x interface. So, a 40MHz clock would yield each lane running at 280MHz. I'm a little confused why you say your running at 378Mbps. You said your receiver worked with the short cable but now with the longer one. It could be a few things but I would analyze the timing on your receiver to assure yourself you have the best skew margin. Some National receivers have de-skew technology. Most of the higher end FPGA's can implement this, too. My guess is that V4 has the power to do so. Another thought, shy don't you just buy a 5m camera link cable and see if your problems go away. Why are you using two 2.5m cables? JPiqueras.M@gmail.com wrote: > First of all, thank you for your answers. > > I answer some of your questions: > > - cam_clk = 40 MHz > - Data rate = (about) 378 Mbps [30 fps; frame size 1024 x 1024; 12 bit > digitalization] > - My ucf and vhdl is the same that Brad's one (but without ISERDES) > > About the cable, is 5 meters in length. The problem is that there is > an intermediate sub-D connector which is joining two 2.5 m cables, id > est, the cable consists in a camera link connector - a sub-D female - > a sub-D male - pins to FPGA board. > I really know that this is not the most suitable for high frequency > signals, but the thing is that this cable works when the receiver is a > frame grabber or a board using the NI deserializer chip. > > Once the input signals are received by the FPGA, they're wrong, > so...if there's a problem I guess it's a mismatch or something like > that. Anyway I'm not an expert...if you have more ideas... > > Thank you, > ChronosArticle: 132204
On 17 May=FDs, 03:35, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > You should look at VHDL like hardware in text form. > > If you look at it like software, you will get confused. > > -- glen Hi Glen, Yes you are right. Perhaps I could not tell what I think. As I understand O.Olson has no FPGA experience. I think producing a PCB with multiple FPGAs and writing FPGA codes and verify that the system is working -only one person is doing all of these- is a tiring job. Am I wrong? Thank you. --enesArticle: 132205
Hello everyone, Something quick to entertain you for a few minutes. I built an FPGA video synthesizer. You can see it in action, plus some additional info here: (epileptics beware!) http://vimeo.com/1025348 I have performed with this synthesizer at the 2007 Monterrey Forum of Cultures, and at this year's International Symposium of Visual Studies, also in Monterrey. The star of the show was a Spartan 3E Starter Kit! Anyway, hopefully this will inspire others to explore the artistic possibilities of programmable logic. Maybe there will be a scene some day ;) Regards, -Sergio, from MexicoArticle: 132206
Hi, A good video. Thanks. Do you fully control the shapes? --enesArticle: 132207
I am using the ISE simulator and I can't seem to figure out how to display variables in the waveform display. All of the documentation refers to "signals", but I am never sure if this term is used in the general or the VHDL specific sense. Am I missing something or is waveform display of variables not supported in the ISE simulator? I am also finding it a bit of a PITA that the simulator seems to want to talk to something, maybe itself, through my firewall! I am using Sophos and it does not have a way of blanket saying that this is ok. It wants to verify every program that accesses the network by comparing the checksum of the program. It am guessing that ISE simulator is compiling the code down to machine executable because the checksum is different every time I compile new source! So every time I have to tell the firewall that this is a new, but valid program! Is this really necessary? Or is there a way to tell ISE simulator to stop talking to itself? RickArticle: 132208
On May 17, 3:54 am, Enes Erdin <eneser...@gmail.com> wrote: > Hi, > > A good video. Thanks. Do you fully control the shapes? > > --enes >From the video page: "How does it work? It basically renders a wire frame model. The vertices of the model can be moved around using the keyboard. You don't really have much control over the shape. The keyboard is sort of a "random data source", which means the user just bashes the keyboard like a monkey until something pretty shows up on the screen ;). More precise controls could be easily implemented, but I am happy with them as they are now." Just scroll down the page for more info.Article: 132209
I am using a vhdl conversion package from freemodelfoundry.com,
conversions.vhd. The function I am having a problem with is
to_hex_str(slv,int). The simulation stops saying
Value 3 is out of valid range : 1 TO 2 of subtype of integer
Simulation stopped when executing process: IRIG_TB.vhd:CTPControl
on line 601 in file "C:/Arius/Boards/IRIG-B/FPGA/IRIG-B-X/
conversions.vhd"
function to_hex_str(x : std_logic_vector;
rtn_len : natural := 0;
justify : justify_side := right;
basespec : b_spec := yes) return
string is
When I look the error line, it is "ptr := ptr + 1;" which obviously
could be running out of bounds. But looking at the code, the
delclaration of ptr is based on the same information that controls the
loop that is executing the statement, "ptr := ptr + 1;" I don't see
any way for it to be assigning ptr out of bounds.
It gets trickier. I tried stripping my code down to the minimum that
would cause the error and it very quickly went away. I am passing
this function two parameters and allowing two to default. I don't see
how anything in my code could cause a failure inside this function.
So now I am pretty stumped. I tried adding some debug statements, but
they only told me that it was crapping out and the details that might
actually tell me why can't be investigated... like what range is being
assigned to ptr and why?
variable nxt : positive := nextmultof(x'length,4);
variable int : std_logic_vector(1 to nxt):= (others => '0');
variable ptr : positive range 1 to (nxt/4)+1 := 1;
I can't "see" the value of x'length. The only way to explain the loop
indexing ptr too high is that something is wrong with the
initialization of the range of ptr. I added some debug statements to
the function and got this...
at 150.000 ns(1): Note: nxt is d"8"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: ptr is d"1"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: rtn_len is d"2"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: loop i d"1"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: r string "0$"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: ptr old d"1"
(/IRIG_TB_vhd/). <<<--- ptr is
updated here
at 150.000 ns(1): Note: ptr new d"2" loop
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: loop i d"2"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: loop i d"3"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: loop i d"4"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: loop i d"5"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: r string "00"
(/IRIG_TB_vhd/).
at 150.000 ns(1): Note: ptr old d"2"
(/IRIG_TB_vhd/).
Value 3 is out of valid range : 1 TO 2 of subtype of integer
Simulation stopped when executing process: IRIG_TB.vhd:CTPControl
on line 607 in file "C:/Arius/Boards/IRIG-B/FPGA/IRIG-B-X/
conversions.vhd"
What this is saying is that the function looped thorough 5 bits of the
input vector. On the fifth loop iteration, it should have converted
the second digit and incremented ptr to 3. But for what ever reason,
when ptr should have had a range of 1 to 3, it crapped out at 3.
Anyone else use the conversions.vhd package? Anyone seen something
like this? Any chance it is a simulator issue?
Article: 132210On May 17, 10:15 pm, rickman <gnu...@gmail.com> wrote: > I am using a vhdl conversion package from freemodelfoundry.com, > conversions.vhd. The function I am having a problem with is > to_hex_str(slv,int). The simulation stops saying I ran another test with interesting results. Let me recap... I have three calls to to_int_str using an SLV. The first uses a 4 bit SLV, the second an 8 bit and the third a 16 bit SLV. In this order, I get an error on the second call saying ptr is out of range at 3 when 3 should be ok. If I remove the first call, the third call craps out with ptr being 4 when it should be ok at 5. Just for grins, I swapped the first and second calls. Sure enough, the third call craps out at 4. The range of ptr is set in the variable declaration of the function to_int_str. I seem to recall reading recently that the declaration is only evaluated once before the function is run, not each time it is invoked. So that would make sense that the range of ptr does not change... which fits perfectly with the third case of it failing on the third call when the 8 bit SLV is used in the first call and the 4 bit SLV is used in the second. Then the third call fails at 4 as if the range of ptr was set by the initial call using an 8 bit SLV. Did I find a bug in this code??? I can't believe I am the first to find this. This code has been around for a long time! However, there is still the fact that if I change the code to remove the extraneous stuff outside of this procedure, it doesn't fail anymore. So clearly there is something else going on. Anyone have a clue???Article: 132211
On Sat, 17 May 2008 20:59:17 -0700 (PDT), rickman <gnuarm@gmail.com>
wrote:
>On May 17, 10:15 pm, rickman <gnu...@gmail.com> wrote:
>> I am using a vhdl conversion package from freemodelfoundry.com,
>> conversions.vhd. The function I am having a problem with is
>> to_hex_str(slv,int). The simulation stops saying
>
>I ran another test with interesting results. Let me recap...
>
>I have three calls to to_int_str using an SLV. The first uses a 4 bit
>SLV, the second an 8 bit and the third a 16 bit SLV. In this order, I
>get an error on the second call saying ptr is out of range at 3 when 3
>should be ok. If I remove the first call, the third call craps out
>with ptr being 4 when it should be ok at 5. Just for grins, I swapped
>the first and second calls. Sure enough, the third call craps out at
>4.
>
>The range of ptr is set in the variable declaration of the function
>to_int_str. I seem to recall reading recently that the declaration is
>only evaluated once before the function is run, not each time it is
>invoked.
At elaboration.
VHDL is not a dynamically typed language; you can't stretch and shrink
subtypes e.g. ranges during run time.
So I am guessing that the first length (x'length) is statically
determinable (i.e. without actually running the code) from initial
conditions (e.g. an initial value of x).
It is a good idea to use constants to determine ranges; preventing this
sort of error from happening. I had no idea that you could do it with
the initial value of a variable; perhaps the Xilinx simulator is being
incorrectly permissive here (and therefore hiding a subtle bug for you
to find later).
In any case you have to adopt some design that allows the range to be
the largest you will need, and derive any checking you require from the
actual parameter x to your SLV function.
variable ptr : positive range 1 to largest_I_need;
...
assert (nxt/4)+1 = (size_I_expect) report "Something wrong here"
severity warning; -- if I am paranoid
- Brian
Article: 132212Hello All, I have an XSA-50 board and am programming it to count the amount of high input signals from the header pins. The signal that I want to count is coming in at least 4ns as TTL signals--this is my clock signal in the verilog code, but not physically hooked to the clock pin on the board. Will this board be able to detect the signals, even though this signals have short time span ? Please note, I am very new to this timing stuff and would like some guidance. Also, please keep in mind that I looked at the signal on an oscilloscopes and it comes in very fast! I am currently using the Xlinx 9.1 package to do all of the simulations for this device; I looked at the wave forms using a nanoseconds range on the simulator and it functions fine. Thanks, UchennaArticle: 132213
On Sat, 17 May 2008 20:59:17 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >The range of ptr is set in the variable declaration of the function >to_int_str. I seem to recall reading recently that the declaration is >only evaluated once before the function is run, not each time it is >invoked. I wrote: VHDL is not a dynamically typed language; you can't stretch and shrink subtypes e.g. ranges during run time. Which makes sense if you think about its orientation as a hardware language; it is difficult to stretch and shrink registers or counters after synthesis. But it does mean some unnecessary restrictions creating things like testbenches. VHDL 2006 suposedly relaxes some of these restrictions; but at a wild guess, not this one. - BrianArticle: 132214
On Sun, 18 May 2008 08:22:24 +0100, Brian Drummond wrote: >I wrote: VHDL is not a dynamically typed language; you can't stretch and >shrink subtypes e.g. ranges during run time. > >Which makes sense if you think about its orientation as a hardware >language; it is difficult to stretch and shrink registers or counters >after synthesis. Yes, but subprograms (procedures and functions) are dynamically elaborated: all their arguments, and their local variables, are constructed dynamically at the moment of invocation. This is what allows you to handle unconstrained arguments so elegantly. For synthesis, the tool must convince itself that each subprogram call is in a context in which the tool can statically determine what will get elaborated; in other words, you effectively get a new static instance of each subprogram for each distinct invocation. That's what people mean when they say that functions represent combinational logic, and you get a new instance of the logic for each call to the function. It sounds very much as though Rickman has encountered a tool bug. Is there any way you can run your test case in a second simulator? The free version of Simili, for example? Alternatively, there may be other ways to get your type conversion, saving you the trouble of fighting a possibly buggy FMF package. Converting a SLV to its hex text representation is easy enough. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 132215
On May 18, 6:25 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sun, 18 May 2008 08:22:24 +0100, Brian Drummond wrote: > >I wrote: VHDL is not a dynamically typed language; you can't stretch and > >shrink subtypes e.g. ranges during run time. > > >Which makes sense if you think about its orientation as a hardware > >language; it is difficult to stretch and shrink registers or counters > >after synthesis. > > Yes, but subprograms (procedures and functions) are dynamically > elaborated: all their arguments, and their local variables, are > constructed dynamically at the moment of invocation. This is > what allows you to handle unconstrained arguments so elegantly. > For synthesis, the tool must convince itself that each subprogram > call is in a context in which the tool can statically determine > what will get elaborated; in other words, you effectively get > a new static instance of each subprogram for each distinct > invocation. That's what people mean when they say that > functions represent combinational logic, and you get a > new instance of the logic for each call to the function. > > It sounds very much as though Rickman has encountered a > tool bug. Is there any way you can run your test case > in a second simulator? The free version of Simili, > for example? > > Alternatively, there may be other ways to get your > type conversion, saving you the trouble of fighting > a possibly buggy FMF package. Converting a SLV to > its hex text representation is easy enough. > -- > Jonathan Bromley, Consultant I expected what you said. I don't see how subroutines could work (or make sense) in an HDL unless they are separately elaborated for each place in the code where they are invoked. We *are* describing hardware. I don't have the time right now, but later I will try again to boil this down to a simple test case that can be submitted to whoever "owns" the bug... including myself possibly. Another very odd thing. I have replaced the calls to to_hex_str with to_int_str which is a different function with a different structure. The display shows the values d"x" with x being the value displayed... all except for the first invocation. Then it displays h"x"!!! This is the same line of code in my program in each case! I tried to debug this a bit by adding printouts and I found that there is a small bug for the case of x being 0. They have a default line of code to handle this with the base hardwired! I will report this one. RickArticle: 132216
Some of the other posts seems to have touched on the issues I want to discuss, but not in much detail. On May 16, 5:29 am, "O. Olson" <olson_...@yahoo.it> wrote: > Hi, > > I need to interconnect two or four FPGAs on a PCB, and I am lookin= g > at the prospect of designing these boards myself. If any one has done > this, I would be grateful if you could provide some pointers, > especially links to websites that have this information. I would > probably be using the Xilinx Virtex II Someone did point out that this part is ancient technology and you would be better served with a newer device. Also, don't feel like you need to limit yourself to Xilinx parts. Altera parts and software are just as good. But you need to ask yourself a few questions. Why do you think you need multiple FPGAs? Why do you think you need to build your own hardware? Both of these design decisions will result in extra work... work which can interfere with getting results for your thesis. You want to focus on your work and not on the details of building hardware or getting multiple chips to communicate or even load together. > I don=92t know how to start this =96 but I have a few questions. I= s it > possible for me to simulate the setup between FPGAs connected on a PCB > board. Or is it possible for me to bread board the FPGA =96 I have not > heard of this though. I have looked at the manual of the Virtex II, > and there are a large numbers of pins =96 I have yet to figure out which > pins I need to power at the minimum to get this to work. So I don=92t > want to start laying out a PCB Board immediately. There are two kinds of simulation that you might be talking about. If you mean digital logic simulation, then yes, any HDL simulator can simulate multiple FPGA chips just as well as a single chip. A test bench is typically used to tie together the different pieces of a design and can tie together multiple chip designs. If you mean to simulate the electrical signals between the chips, then yes, that can be done too. It will take a board signal simulator such as Hyperlynx. These cost some real money though. I don't know if there are educational versions available or not. > I would be requiring significant on board communication =96 but I = don=92t > think I need the Rocket IOs that are available with Virtex4 =96 the > simple LVDS would do for me I guess. Is there a way for me to test > this aspect before actually putting it on the PCB?? Before designing your board, you need to decide exactly what it is that you need to do with it. To make a decision about the I/O, you need to know what it will be interfacing to and the details of the signals. Don't just pick an interface because is sounds good. > I have so far used FPGAs on the protyping board that comes with th= e > Spartan Kit from Xilinx. I have also used an Emulation machine with a > couple of FPGAs. In all of this I have never been concerned about the > external connections between FPGAs, so I am new to all of this. I would ask why you think you need to be concerned with the design of an FPGA board? There are lots of FPGA boards available and you can get a dozen or so at less cost than designing your own board and building it. Most FPGAs that you will want to use are BGA packaged which requires professional assembly. Some amateurs have had success with the larger pitch parts, but I don't recommend it. Have you looked at the boards available? Do you know how large a part you intend to use? Do you know what I/Os you need for the external interfaces, if any? For doing research work, I would follow the KISS rule. Don't try to design stuff you don't really need.Article: 132217
In the newsgroups comp.arch.fpga, comp.lang.verilog, comp.arch.embedded, sci.electronics.design and comp.lang.vhdl, I saw a thread in which the following words were approximately attributed to the following posters: On Wed, 7 May 2008 17:19:31 -0700, "BobW" <nimby_NEEDSPAM@roadrunner.com> wrote: > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:o1e424d2h2uldtu4qm4589v667lu96hip8@4ax.com... >> On Wed, 7 May 2008 12:19:40 -0700 (PDT), John_H >> <newsgroup@johnhandwork.com> wrote: >> >>>John Larkin wrote: >>>> >>>> To Lattice: >>>> >>>> We dumped Lattice over buggy compilers and dinky performance. Now that >>>> you're spamming our group, I'll make the ban permanent. >>>> >>>> >>>> To the group: >>>> Whenever anybody spams us, please >>>> >>>> 1. Blackball them as a vendor >>>> >>>> 2. Say bad things about their companies and products, preferably with >>>> lots of google-searchable keywords. >>>> >>>> John >>> >>>Was this really necessary? Yes. >>>If there were technical webcasts from any of the big vendors, I'd like >>>to know about them though preferably more than 8 minutes beforehand. Email them, and sign up for subscriptions to all their blurbs. A confirmed opt-in email list is a good way to disseminate such info. If they don't have such a list or don't announce events timely, tell them you'll only consider sources from companies who do. >>>If the posts of this nature got to be more than a couple a month from >>>any one source I'd agree with the spam catagorization but it isn't >>>that frequent. "Well, there's spam egg Lattice and spam, that's not got much spam in it." In other words, "they're not breaking the rules THAT often." With the thousands of suppliers that provide products and services relevant to even one of the cross-posted newsgroups, there could be hundreds of posts per day of "legitimate" commercial posts. >>>I'm disappointed that you had problems with them in the past and won't >>>trust them for future designs because of your history; competition is >>>almost always good. But is it reason to be publicly vocal? It's always good to be vocal about inappropriate posts. As for the poster airing his previous problems with Lattice, perhaps they would be better put in a blog or in a post where someone asks about using Lattice, but that's a minor thing compared to the original post. >>>Kill-lists are easy to manage if bart's messages offend you. I have better things to do than manage kill lists. I've got "better things to do" than write this, but but c.a.e and especially s.e.d have been useful to me a while back, and between all the spam and splorge in recent years, it's a pleasant surprise to see these groups are still viable. So I'm doing my little part to help keep them alive. >>> >>>- John_H >> >> >> If we don't discourage commercial posts, newsgroups will be flooded >> with them. I can't kill-file the tens of thousands of companies who >> would spam newsgroups if they thought it would pay off. So let's make >> sure it *doesn't* pay off. >> >> If they want to advertise, let them pay for it somewhere else. >> >> >> John >> > >For what it's worth, I agree with John. > >It's a real shame that we, now, have to go out of our way to filter >commercial and sexual posts. There are proper places for both of those. >Usenet is not one of them, in my opinion. Just to make a slight correction, THESE NEWSGROUPS (see crosspost list at the top of my post) are not the proper place for commercial posts. There are "marketplace" and "sex" newsgroups - if he's going to spam, perhaps Bart Borosky of Lattice would do well to post to those instead. There's no telling where a lonely engineer might go in his spare time, and after all, "posting to Usenet is free" (as in both beer AND speech). Post, drink and speak responsibly. > >BobArticle: 132218
On May 18, 1:29 pm, Ben Bradley <ben_nospam_brad...@frontiernet.net> wrote: > In the newsgroups comp.arch.fpga, comp.lang.verilog, > comp.arch.embedded, sci.electronics.design and comp.lang.vhdl, I saw a > thread in which the following words were approximately attributed to > the following posters: > > On Wed, 7 May 2008 17:19:31 -0700, "BobW" > > > > <nimby_NEEDS...@roadrunner.com> wrote: > > >"John Larkin" <jjlar...@highNOTlandTHIStechnologyPART.com> wrote in message > >news:o1e424d2h2uldtu4qm4589v667lu96hip8@4ax.com... > >> On Wed, 7 May 2008 12:19:40 -0700 (PDT), John_H > >> <newsgr...@johnhandwork.com> wrote: > > >>>John Larkin wrote: > > >>>> To Lattice: > > >>>> We dumped Lattice over buggy compilers and dinky performance. Now that > >>>> you're spamming our group, I'll make the ban permanent. > > >>>> To the group: > >>>> Whenever anybody spams us, please > > >>>> 1. Blackball them as a vendor > > >>>> 2. Say bad things about their companies and products, preferably with > >>>> lots of google-searchable keywords. > > >>>> John > > >>>Was this really necessary? > > Yes. > > >>>If there were technical webcasts from any of the big vendors, I'd like > >>>to know about them though preferably more than 8 minutes beforehand. > > Email them, and sign up for subscriptions to all their blurbs. A > confirmed opt-in email list is a good way to disseminate such info. If > they don't have such a list or don't announce events timely, tell them > you'll only consider sources from companies who do. > > >>>If the posts of this nature got to be more than a couple a month from > >>>any one source I'd agree with the spam catagorization but it isn't > >>>that frequent. > > "Well, there's spam egg Lattice and spam, that's not got much spam > in it." > > In other words, "they're not breaking the rules THAT often." With > the thousands of suppliers that provide products and services relevant > to even one of the cross-posted newsgroups, there could be hundreds of > posts per day of "legitimate" commercial posts. > > >>>I'm disappointed that you had problems with them in the past and won't > >>>trust them for future designs because of your history; competition is > >>>almost always good. But is it reason to be publicly vocal? > > It's always good to be vocal about inappropriate posts. As for the > poster airing his previous problems with Lattice, perhaps they would > be better put in a blog or in a post where someone asks about using > Lattice, but that's a minor thing compared to the original post. > > >>>Kill-lists are easy to manage if bart's messages offend you. > > I have better things to do than manage kill lists. I've got "better > things to do" than write this, but but c.a.e and especially s.e.d have > been useful to me a while back, and between all the spam and splorge > in recent years, it's a pleasant surprise to see these groups are > still viable. So I'm doing my little part to help keep them alive. > > > > > > >>>- John_H > > >> If we don't discourage commercial posts, newsgroups will be flooded > >> with them. I can't kill-file the tens of thousands of companies who > >> would spam newsgroups if they thought it would pay off. So let's make > >> sure it *doesn't* pay off. > > >> If they want to advertise, let them pay for it somewhere else. > > >> John > > >For what it's worth, I agree with John. > > >It's a real shame that we, now, have to go out of our way to filter > >commercial and sexual posts. There are proper places for both of those. > >Usenet is not one of them, in my opinion. > > Just to make a slight correction, THESE NEWSGROUPS (see crosspost > list at the top of my post) are not the proper place for commercial > posts. There are "marketplace" and "sex" newsgroups - if he's going to > spam, perhaps Bart Borosky of Lattice would do well to post to those > instead. There's no telling where a lonely engineer might go in his > spare time, and after all, "posting to Usenet is free" (as in both > beer AND speech). > > Post, drink and speak responsibly. > > > > >Bob Guys, I read this thread after it was created and just wanted to ask a couple of questions (while completely agreeing with the generally accepted conclusion): Was all this 'hot air' necessary? Was all this bad-mouthing coming from some of the authors proper for the group? With respect,Article: 132219
"Alex" <enginven@gmail.com> wrote in message news:05bd2c8f-8660-49f3-8140-16baa048898f@n1g2000prb.googlegroups.com... > On May 18, 1:29 pm, Ben Bradley <ben_nospam_brad...@frontiernet.net> > wrote: >> In the newsgroups comp.arch.fpga, comp.lang.verilog, >> comp.arch.embedded, sci.electronics.design and comp.lang.vhdl, I saw a >> thread in which the following words were approximately attributed to >> the following posters: >> >> On Wed, 7 May 2008 17:19:31 -0700, "BobW" >> >> >> >> <nimby_NEEDS...@roadrunner.com> wrote: >> >> >"John Larkin" <jjlar...@highNOTlandTHIStechnologyPART.com> wrote in >> >message >> >news:o1e424d2h2uldtu4qm4589v667lu96hip8@4ax.com... >> >> On Wed, 7 May 2008 12:19:40 -0700 (PDT), John_H >> >> <newsgr...@johnhandwork.com> wrote: >> >> >>>John Larkin wrote: >> >> >>>> To Lattice: >> >> >>>> We dumped Lattice over buggy compilers and dinky performance. Now >> >>>> that >> >>>> you're spamming our group, I'll make the ban permanent. >> >> >>>> To the group: >> >>>> Whenever anybody spams us, please >> >> >>>> 1. Blackball them as a vendor >> >> >>>> 2. Say bad things about their companies and products, preferably >> >>>> with >> >>>> lots of google-searchable keywords. >> >> >>>> John >> >> >>>Was this really necessary? >> >> Yes. >> >> >>>If there were technical webcasts from any of the big vendors, I'd like >> >>>to know about them though preferably more than 8 minutes beforehand. >> >> Email them, and sign up for subscriptions to all their blurbs. A >> confirmed opt-in email list is a good way to disseminate such info. If >> they don't have such a list or don't announce events timely, tell them >> you'll only consider sources from companies who do. >> >> >>>If the posts of this nature got to be more than a couple a month from >> >>>any one source I'd agree with the spam catagorization but it isn't >> >>>that frequent. >> >> "Well, there's spam egg Lattice and spam, that's not got much spam >> in it." >> >> In other words, "they're not breaking the rules THAT often." With >> the thousands of suppliers that provide products and services relevant >> to even one of the cross-posted newsgroups, there could be hundreds of >> posts per day of "legitimate" commercial posts. >> >> >>>I'm disappointed that you had problems with them in the past and won't >> >>>trust them for future designs because of your history; competition is >> >>>almost always good. But is it reason to be publicly vocal? >> >> It's always good to be vocal about inappropriate posts. As for the >> poster airing his previous problems with Lattice, perhaps they would >> be better put in a blog or in a post where someone asks about using >> Lattice, but that's a minor thing compared to the original post. >> >> >>>Kill-lists are easy to manage if bart's messages offend you. >> >> I have better things to do than manage kill lists. I've got "better >> things to do" than write this, but but c.a.e and especially s.e.d have >> been useful to me a while back, and between all the spam and splorge >> in recent years, it's a pleasant surprise to see these groups are >> still viable. So I'm doing my little part to help keep them alive. >> >> >> >> >> >> >>>- John_H >> >> >> If we don't discourage commercial posts, newsgroups will be flooded >> >> with them. I can't kill-file the tens of thousands of companies who >> >> would spam newsgroups if they thought it would pay off. So let's make >> >> sure it *doesn't* pay off. >> >> >> If they want to advertise, let them pay for it somewhere else. >> >> >> John >> >> >For what it's worth, I agree with John. >> >> >It's a real shame that we, now, have to go out of our way to filter >> >commercial and sexual posts. There are proper places for both of those. >> >Usenet is not one of them, in my opinion. >> >> Just to make a slight correction, THESE NEWSGROUPS (see crosspost >> list at the top of my post) are not the proper place for commercial >> posts. There are "marketplace" and "sex" newsgroups - if he's going to >> spam, perhaps Bart Borosky of Lattice would do well to post to those >> instead. There's no telling where a lonely engineer might go in his >> spare time, and after all, "posting to Usenet is free" (as in both >> beer AND speech). >> >> Post, drink and speak responsibly. >> >> >> >> >Bob > > Guys, > > I read this thread after it was created and just wanted to ask a > couple of questions (while completely agreeing with the generally > accepted conclusion): > Was all this 'hot air' necessary? > Was all this bad-mouthing coming from some of the authors proper for > the group? > > With respect, Which group? It was crossposted to 5 different newsgroups, and is unwelcome in at least one of them.Article: 132220
On May 18, 2:43 pm, "Robert Miles" <robertmi...@bellsouthNOSPAM.net> wrote: > "Alex" <engin...@gmail.com> wrote in message > > news:05bd2c8f-8660-49f3-8140-16baa048898f@n1g2000prb.googlegroups.com... > > > > > On May 18, 1:29 pm, Ben Bradley <ben_nospam_brad...@frontiernet.net> > > wrote: > >> In the newsgroups comp.arch.fpga, comp.lang.verilog, > >> comp.arch.embedded, sci.electronics.design and comp.lang.vhdl, I saw a > >> thread in which the following words were approximately attributed to > >> the following posters: > > >> On Wed, 7 May 2008 17:19:31 -0700, "BobW" > > >> <nimby_NEEDS...@roadrunner.com> wrote: > > >> >"John Larkin" <jjlar...@highNOTlandTHIStechnologyPART.com> wrote in > >> >message > >> >news:o1e424d2h2uldtu4qm4589v667lu96hip8@4ax.com... > >> >> On Wed, 7 May 2008 12:19:40 -0700 (PDT), John_H > >> >> <newsgr...@johnhandwork.com> wrote: > > >> >>>John Larkin wrote: > > >> >>>> To Lattice: > > >> >>>> We dumped Lattice over buggy compilers and dinky performance. Now > >> >>>> that > >> >>>> you're spamming our group, I'll make the ban permanent. > > >> >>>> To the group: > >> >>>> Whenever anybody spams us, please > > >> >>>> 1. Blackball them as a vendor > > >> >>>> 2. Say bad things about their companies and products, preferably > >> >>>> with > >> >>>> lots of google-searchable keywords. > > >> >>>> John > > >> >>>Was this really necessary? > > >> Yes. > > >> >>>If there were technical webcasts from any of the big vendors, I'd like > >> >>>to know about them though preferably more than 8 minutes beforehand. > > >> Email them, and sign up for subscriptions to all their blurbs. A > >> confirmed opt-in email list is a good way to disseminate such info. If > >> they don't have such a list or don't announce events timely, tell them > >> you'll only consider sources from companies who do. > > >> >>>If the posts of this nature got to be more than a couple a month from > >> >>>any one source I'd agree with the spam catagorization but it isn't > >> >>>that frequent. > > >> "Well, there's spam egg Lattice and spam, that's not got much spam > >> in it." > > >> In other words, "they're not breaking the rules THAT often." With > >> the thousands of suppliers that provide products and services relevant > >> to even one of the cross-posted newsgroups, there could be hundreds of > >> posts per day of "legitimate" commercial posts. > > >> >>>I'm disappointed that you had problems with them in the past and won't > >> >>>trust them for future designs because of your history; competition is > >> >>>almost always good. But is it reason to be publicly vocal? > > >> It's always good to be vocal about inappropriate posts. As for the > >> poster airing his previous problems with Lattice, perhaps they would > >> be better put in a blog or in a post where someone asks about using > >> Lattice, but that's a minor thing compared to the original post. > > >> >>>Kill-lists are easy to manage if bart's messages offend you. > > >> I have better things to do than manage kill lists. I've got "better > >> things to do" than write this, but but c.a.e and especially s.e.d have > >> been useful to me a while back, and between all the spam and splorge > >> in recent years, it's a pleasant surprise to see these groups are > >> still viable. So I'm doing my little part to help keep them alive. > > >> >>>- John_H > > >> >> If we don't discourage commercial posts, newsgroups will be flooded > >> >> with them. I can't kill-file the tens of thousands of companies who > >> >> would spam newsgroups if they thought it would pay off. So let's make > >> >> sure it *doesn't* pay off. > > >> >> If they want to advertise, let them pay for it somewhere else. > > >> >> John > > >> >For what it's worth, I agree with John. > > >> >It's a real shame that we, now, have to go out of our way to filter > >> >commercial and sexual posts. There are proper places for both of those. > >> >Usenet is not one of them, in my opinion. > > >> Just to make a slight correction, THESE NEWSGROUPS (see crosspost > >> list at the top of my post) are not the proper place for commercial > >> posts. There are "marketplace" and "sex" newsgroups - if he's going to > >> spam, perhaps Bart Borosky of Lattice would do well to post to those > >> instead. There's no telling where a lonely engineer might go in his > >> spare time, and after all, "posting to Usenet is free" (as in both > >> beer AND speech). > > >> Post, drink and speak responsibly. > > >> >Bob > > > Guys, > > > I read this thread after it was created and just wanted to ask a > > couple of questions (while completely agreeing with the generally > > accepted conclusion): > > Was all this 'hot air' necessary? > > Was all this bad-mouthing coming from some of the authors proper for > > the group? > > > With respect, > > Which group? It was crossposted to 5 different newsgroups, and is > unwelcome in at least one of them. comp.arch.fpga -that is the group I had in mind (that's where I had read this thread) . I'm reading the group's threads often (and for many years) and in most cases find myself getting excellent information, quite often enjoying quick wit and clever advice of many contributors ... That's why seeing this kind of language (and I'll repeat- I do not approve spam in no way) from _some_ authors is so disappointing (I'm not talking about you, Robert :^) . Why not to express your right-full indignation directly to the person who generated the spam (when you can, as in this case) and/or modify you spam filter if you'd like.(period) AlexArticle: 132221
hello, I am trying to interface between my pc (windows) and a Xilinx Virtex2Pro board using ethernet. i am told i require Xilinx PLB Ethernet MAC ip core. i must admit i am very new to such work, forgive my blatantness.... i would like to know: 1) What exactly do i get in the Xilinx Ethernet MAC ip core? (design files etc?) 2) Using XPS (EDK 9.1) and ISE 9.1, how do i integrate it into an existing project? 3) the ethernet is just a part of the project.... i only need to transfer data between my pc and the board.... should the MAC be a part of the board? 4) do i have to use an embedded processor (microblaze/powerpc) to integrate the MAC? Please let me know as soon as possible, and keep it as simple as possible- i am new to this. thanks in advance Awaiting your advice vikramArticle: 132222
On May 17, 1:52 am, explore <chethanzm...@gmail.com> wrote: > Hi, > I have been running my designs on ISE 9.2i for a virtex-5 LX110t FPGA. > The time taken by the tool to complete a full synthesis and > implementation is a little over 3 hours on a Core2 Quad CPU running at > 2.4 GHz with 2GB of RAM and Windows XP Pro 32-bit edition. I have > tried using ISE 10.1 and have observed that the time taken to run the > same design is less than 2 hrs. I have read the threads on Xilinx > about using more memory, I will be upgrading my memory to 3 GB or > more. I would like to get some recommendations for a system > configuration in terms of the best suitable processor, memory and any > other useful configuration to bring down the synthesis-map-par run- > time. The other discussion threads that I went through were either old > or did not point to an optimal configuration. Your inputs will be > helpful and is highly appreciated. > > Thanks! Hi, I cannot give a comment on the usage of better processor or a system with a bigger RAM but I faced a similar situation some time ago when my synthesis on XC2V8000 took some 25-hours to complete on a Multiprocessor machine. For a slightest change in RTL I would wait for a working day to get the bitstream. Later I used Xilinx PlanAhead to floorplan the design and a modification in RTL was sythesized for that individual module and netlist was updated with that frozen floor plan. I reduced our PAR time from 20-hours to just one hour. Hope this helps /MHArticle: 132223
could anybody please explain me ....whether is there any chance of clock skew being greater than or equal to the timeperiod of the clock? If so,what are the effects? Any explaination would be deeply appreciated..... Thanks in advance....Article: 132224
Thanks for your Reply Wicky!! But the ISE 9.2i version has OPB_IPIF documents. MoreOver The Unified PLB46 bus is available from ISE 10.1 not in ISE 9.2. I will be much intrested on ISE 9.2i and 8.2i Microblaze versions. Hope you got the question. regds karthick.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z