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John_H wrote: > MM wrote: >> "John_H" <newsgroup@johnhandwork.com> wrote in message >> news:d01a8184-3019-4926-bbcb-ef5a929a1ccb@z66g2000hsc.googlegroups.com... >>> Have you recompiled the FX20 design for the FX40 package? Hex digits >>> 4-5 (94 vs 8c) are supposed to be the part size. Since the chain >>> report shows the correct size, I've got to assume you have the wrong >>> programming file. >> >> Hmm... As I've already said in another post the file has been compiled >> for FX40... I've checked that several times... But I will check again.... >> >>> If you run the scan on a board with the xc4vfx20, do you get this >>> "other" IDCODE? >> >> No, in that case it works fine... >> >> /Mikhail > > "it works fine" > > The question was whether the other board returns > > Validating chain... > Boundary-scan chain validated successfully. > '2': IDCODE is '00000001111010010100000010010011' > '2': IDCODE is '01e94093' (in hex). > '2': : Manufacturer's ID =Xilinx xc4vfx20, Version : 0 > > OR if the IDCODE is something completely different. > > If you're programming the OLD board with the NEW programming file and > "it works fine" then YES you have the old programming file for the new > board. I'm hoping that a read from the FX20 board (or a look at the BSDL file) would show 01e64093 per the lone table I found at the bottom of page 19 in http://www.xilinx.com/support/documentation/user_guides/ug071.pdf My worry is with the note attached to your FX40 JTAG IDCODE of 01e8c093(1): 1. Does not reflect the actual device array size. This note suggests someone may have taken on the responsibility of changing the IDCODE to reflect the proper "device array size." You HAVE actually talked to a CAE at the Xilinx Support Hotline (or opened a webcase) haven't you? This sounds like a very specific issue that might just not be in the external answers database yet. The date code on the chips may also be helpful information for the CAE handling your case. - John_HArticle: 132951
As you all know, downloading files from usenet leaves you with two sets of files.. The rar files from what you're downloading and the par2 files for incomplete file repair. If anyone has attempted to download anything in the 8GB range, you'll find that well.. if you're missing enough parts of the file, the par2 recovery can be a painful, painful process taking up to three hours in some cases. I'm sick of it. So, here's the idea. Use a FPGA to do the reed-solomon decoding to accelerate the PAR2 repair/recovery process. The system should utilize a USB connection to pipe data directly from the disk to the FPGA that will do the offboard processing of the data. The data transfer should be controlled by an application on the computer. Second Problem.. The XBOX 360 doesn't play x.264 and all the good movies are in x.264. Converting from x.264 to h.264 could be done offboard on an FPGA because it takes for-ever to complete on my system (8 hours). This should have the same premise as the previous issue, minus using a x. 264 decoding core and possibly directly converting it to h.264 or doing a decompression-recompression.. SPECS: The development system i'm using is the XILINX ML-505 board with the Virtex 5 chip. This is a open-source project being done for fun and learning btw. Suggestions / Comments / Complaints?Article: 132952
John, > > I'm hoping that a read from the FX20 board (or a look at the BSDL file) > would show 01e64093 per the lone table I found at the bottom of page 19 in > > http://www.xilinx.com/support/documentation/user_guides/ug071.pdf It reads 21e64093, which I believe is fine, as 2 at the start is just a version code. > You HAVE actually talked to a CAE at the Xilinx Support Hotline (or opened > a webcase) haven't you? Not yet, but probably will very soon... :) /MikhailArticle: 132953
Rob, How many devices do you need to run this fast? I will assume V5, as that is the only one which could do this. If it is one, this is probably not too hard: make the design as fast as you can (by the proper architecture, try to use DDR (use both edges of the clock), and then cool the device to keep it at room temperature. You may also run it 5% Vccint high, but no more than that. The reason is that raising Vccint does not raise the pass-gate voltages, so raising Vccint any higher provides no increase in speed. Our devices since V2P have actually become slower if too cold! Then go through a dozen -3 (highest/fastest speed grade) devices from different lots until you find the fastest one. Due to process variations, there is a lot of performance in the devices which is "wasted" because we like to ship all the parts which test "good!" Along with the slow parts that just barely meet -3, there are at least another 5% to 10% which exceed -3 by one or two more speed grades (even faster). If you have to do this for more than one device, then it becomes far too difficult to find, make work, and so on (can't go to production like this). I bring this up, only because there is performance there, and if it is a one-off study, it is do-able. Of course, since Xilinx won't get rich off one part, I and Xilinx can not endorse this, nor can we support this. This is just here for your educational pleasure. AustinArticle: 132954
Seems like a really nice idea. Please notify your progress.Article: 132955
MM wrote: > "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message > news:484F2F1D.3070201@xilinx.com... >> MM wrote: >> >> In some versions of the software the xc4vfx40 idcode was incorrectly coded >> into the BSDL files which will effect the programming. >> >> See this Answer Record for more information. >> http://www.xilinx.com/support/answers/30095.htm >> > > It seemed for a moment that it had to be it, but I've checked the BSDL files > and they are correct in both ISE8.2 and 10.1. I have 9.2 installed as well > and indeed the file in 9.2 is wrong, however there is no way it gets used as > this installation is completely dormant (no paths or environment variables > pointing to it)... Very confusing... > > Here is the beginning of the bitgen report proving that the file is for > FX40: > > Release 8.2.03i - Bitgen I.34 > Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. > Loading device for application Rf_Device from file '4vfx40.nph' in > environment > C:\Xilinx\ISE82. > "curc_top" is an NCD, version 3.1, device xc4vfx40, package ff672, > speed -10 > The STEPPING level for this design is 0. > Opened constraints file curc_top.pcf. > > Tue Jun 10 17:59:41 2008 > > C:\Xilinx\ISE82\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g > Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g > M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g > InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g > RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g > TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g > DCIUpdateMode:AsRequired -g StartUpClk:JtagClk -g DONE_cycle:4 -g > GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g > Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No curc_top.ncd I believe that the problem is that the 8.2 software that you are using has a hardcoded (not in the BSDL) IDCODE value of 0x01e94093 and this has been written into your BIT file. The correct value should 0x01e8c093. Try rerunning bitgen to create a newBIT file using 10.1 software (the 9.2 might also work, it was just the BSDL file that was wrong in this version). Ed McGettigan -- Xilinx Inc.Article: 132956
> The XBOX 360 doesn't play x.264 and all the good movies are in x.264. > Converting from x.264 to h.264 could be done offboard on an FPGA > because it takes for-ever to complete on my system (8 hours). This > should have the same premise as the previous issue, minus using a x. > 264 decoding core and possibly directly converting it to h.264 or > doing a decompression-recompression.. There are chips that will do this already. Here's one: http://www.aspex-semi.com/q/product_features.shtml Cheers, JonArticle: 132957
On Jun 11, 11:24=A0am, Jon Beniston <j...@beniston.com> wrote: > > The XBOX 360 doesn't play x.264 and all the good movies are in x.264. > > Converting from x.264 to h.264 could be done offboard on an FPGA > > because it takes for-ever to complete on my system (8 hours). This > > should have the same premise as the previous issue, minus using a x. > > 264 decoding core and possibly directly converting it to h.264 or > > doing a decompression-recompression.. > > There are chips that will do this already. Here's one: > > http://www.aspex-semi.com/q/product_features.shtml > > Cheers, > Jon Thanks for the reply. Aspects of this design can certainly be used and incorporated into this design, but as you know.. Their product isn't free/open source. As this is also a learning project, I think it would be better to build it from the ground up (using some pre-existing open source IP if possible).Article: 132958
On Jun 10, 10:28=A0pm, Alex Freed <al...@mirrow.com> wrote: > Peter Alfke wrote: > > > Alex, Xilinx is a U.S. company, and your number is called 1.5 billion > > over here. (Yes, I know Europeans call it a milliard.) > > You also picked a very long config time. Typical FPGAs can be > > configured much faster. > > But it seems that you just want to create some controversy. I am not > > so sure that you succeeded. Better luck next time! > > Peter > > Peter, I was trying to create a smile, not a controversy. That should > have been clear from =A0the smiley if nothing else. > > -Alex. Alex, sorry for over-reacting. I am perhaps overly sensitive to accusations of "marketing hype", since I am very close to Marketing, but try to curb their excesses. I should have interpreted the smiley the way you intended it. Cheers PeterArticle: 132959
Hi, Well, since the Xilinx functional re-organization, I have a new responsibility (here at Xilinx). The bad news(?): I will still participate here on c.a.f. and my Xilinx blog (is that of any use to anyone?) and I am still willing to find the answers to those questions that seem not to have any answers in our documentation, or on our website. The good news(?): I no longer manage the FPGA Lab (silicon verification and characterization planning, testing, and coordination). That has been re-organized, and its role expanded (which is all goodness). The best news(?): I am part of Xilinx Labs (the research side of Xilinx), where I get to do lots of useful and practical stuff, as well as try to peer into the future. I wish to thank those that emailed me personally and expressed any concerns for me: I have fairly diverse and useful talents, so finding a place where I fit in in the new organization was never a concern. I regret that there were those that did not fit in to the new structure, and as I have said before, I wish them the best, and I would recommend them highly to anyone. AustinArticle: 132960
Hi Ed, > > I believe that the problem is that the 8.2 software that you are using has > a hardcoded (not in the BSDL) IDCODE value of 0x01e94093 and this has been > written into your BIT file. The correct value should 0x01e8c093. Try > rerunning bitgen to create a newBIT file using 10.1 software (the 9.2 > might also work, it was just the BSDL file that was wrong in this > version). That's indeed the case. I rebuilt the file with 10.1 bitgen and the IDCODE problem is gone now. However the Done still doesn't go high... Although I do see now that something gets loaded in the device, so maybe it's just the Done signal itself... I am investigating... Thanks, /MikhailArticle: 132961
I have AMIRIX ap1070 board with a xilinx virtex II PRO XC2VP70 . I am trying to use it for network based application . I am not using the powerpc at all and was wondering if there is a way to disable the powerpcs and the plb/opb buses on the chip. There is a pci bridge from tundra on board which helps in pci communication with the host. I dont knwo if I would be able to configure it using the host drivers and then use my ip cores exclusively with no powerpc and linux running on the fpga. Right now I am just trying to do a workaround by not fiddling with the base design and just adding my ip passively into the design containing the poweprc plb/opb structure. The manufacturer has a u-boot code on a flash which gets loaded into the SDRAM on board which is used to initializing and assigning the address space. I have o figure out a way to assign the address space using the host instead but before that I wanted to know if there is away to remove the powerpcs from the design. Thanks DArticle: 132962
On Jun 8, 10:00 pm, timinganalyzer <timinganaly...@gmail.com> wrote: > Hello All, > > A new version beta 0.83 is now available. The following changes and > additions have occurred. > > * Improved Image Preview Display. > * Context sensitive popup menus to edit objects. > * Path set in image save dialog works. > * Metric paper sizes added to image preview. > * Lower case z, and x now work bus value combobox in toolbar. > * Move signals up and down commands now respect any space in > diagrams used for Text. > * Objects attached to any signal being deleted are deleted > automatically. > * Save file now includes some more error checking before saving > objects. > * Delays can not be added to DigitalClocks. > > You can download the Free Edition now and read all about the > TimingAnalyzer at: > > www.timing-diagrams.com > > ---------------------------------------------------------------------------------------------------------------------------------------- > > The TimingAnalyzer can be used to quickly and easily draw timing > diagrams. Signals, clocks, buses, delays, constraints, and states are > easily added from the GUI. > > It can also be used to quickly do a timing analysis and check for > timing faults. Minimum, typical, and worst case analysis can be > performed. Delays and constraints are easily specified and changed to > see if faster clocks or slower parts can be used without any timing > faults. > > There are 3 editions planned. The Free Edition(FE), a Standard > Edition(SE), and the Professional Edition(PE). You asked for suggestions... I suggest that you spend some time working on the docs. I don't mean the full up, detailed manual. I mean come up with something that lets a beginner produce some simple diagrams quickly. Leave out the fancy features and just explain the basics of how this program is intended to be used. I think you feel the program is simple, but it is not. Maybe once you get the user over the initial hump, it is easy. But that initial hum is significant. You have several ways of getting documentation or help. I could only find one that worked. In particular, you have a menu item in the program that opens a link in the web browser... to an empty page. I understand that this is a placeholder, but why have a placeholder that only frustrates the user? Grey out the menu item to anything that is not implemented or that does not work. No point in having users go down dead ends. RickArticle: 132963
In article <g2os8s$7f97@cnn.xsj.xilinx.com>, austin <austin@xilinx.com> wrote:
>The good news(?): I no longer manage the FPGA Lab (silicon verification
>and characterization planning, testing, and coordination). That has
>been re-organized, and its role expanded (which is all goodness).
Uh oh, so much for having accurate timing files for Virtex-6 :-)
I don't understand the reorganization either, other than in cynical excuse
for an executive bonus terms. XLNX stock price was a little low at the
beginning of this year, but not terribly low. It came back without this
action. The price has pretty much tracked ALTR so you can't say that X was
doing anything terribly wrong.
On the other hand, FPGA stock prices have been flat since the 2000 boom- I
don't see how a re-organization is going to change this. Maybe if Xilinx
entered a new market...
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 132964Joseph, I do understand the reorganization. And, it was not to increase executive bonuses. It was to better serve our customers. Time will only tell, but I think that it is a very good thing. Rather re-org while on top to get even better, than to re-org (down-size) because there is no money. This was not a re-org to down-size. 7% hardly matters in terms of the costs. But putting 93% in the right positions to get things done right, is critical to future success. And the executives have the same "pay for performance" that everyone else faces: they need to show tangible progress and meet their goals, or else their jobs are likely to "go-away." AustinArticle: 132965
ni, The Virtex 2 Pro is a FPGA. The 405PPC core is programmable. Instantiate it in your design, and you use it. Don't instantiate it in your design, and it is unused. It is your choice in your VHDL or verilog before it is placed routed, and the bitstream created. Once you have a bitstream, you need to go back, and redesign for what you actually want. Or, you can create another bitstream, and load that one in after the first one (use reconfiguration to do task 1, followed by task 2). The 405PPC core in in the silicon, so you can not "take it out." All you are able to do is to either include it in your design, or exlude it from your design: your choice. AustinArticle: 132966
On Jun 11, 10:29 am, austin <aus...@xilinx.com> wrote: > Rob, > > How many devices do you need to run this fast? > > I will assume V5, as that is the only one which could do this. > > If it is one, this is probably not too hard: make the design as fast as > you can (by the proper architecture, try to use DDR (use both edges of > the clock), and then cool the device to keep it at room temperature. > [snip] > Our devices since V2P have actually become slower if too cold! > [snip]> > Austin Any explanation as to the physics of slowing down when colder? Does this make sense for the new process or is it still black magic? I'm assuming the device also slows down when hotter? Regards, GaborArticle: 132967
Gabor, Thanks for asking! Yes, it also slows down when hotter. Not modeled very well by foundry spice models, the issue appears to be related to the mid oxide pass gates, whose supply is from a band gap controlled reference from the 2.5V Vccaux, combined with models that didn't have all the 'wiggles' needed (to simple). The nmos passgates all run at a slightly higher voltage than Vccint (so the interconnect does not have a VT drop from the nmos). The nearly constant passgate voltage, and a varying temperature, and (constant) Vccint varying leads to some interesting behavior of the speed (which is largely due to the interconnect). First time we saw it, we were really puzzled, but then we went back and measured the devices in the scribe lines, and further refined our models. The "problem" with today's advanced technologies is that second, third, and fourth order effects are all beginning to pop up, which leads to needing even better models than we have enjoyed in the past. Better models take more time, or more effort. For example, it is well known that the RF models for a process node come out as much as one year after the foundry is making silicon at that node. One year to wait for models is pretty tough, and if you are making cell-phones (or FPGAs with MGTs) you pretty much have to wait for the models, or do test chips, and make them yourself (there is (ain't) no such thing as a free lunch...TANSTAAFL). An often heard remark between IC Designers "at the bleeding edge" at lunch is "those damn models changed again" (so you have to go back and re-verify everything). AustinArticle: 132968
austin wrote: > Hi, > > Well, since the Xilinx functional re-organization, I have a new > responsibility (here at Xilinx). > > The best news(?): I am part of Xilinx Labs (the research side of > Xilinx), where I get to do lots of useful and practical stuff, as well > as try to peer into the future. Glad you are happy with the results of the re-org! Best wishes for the future in your new position. I tend to use Xilinx products in some really unusual ways, almost never as straightforward digital "blocks". In one case, due to the number of I/Os required, I have a Spartan XCS20 used as a motherboard slot manager, where it controls passing tokens across vacant card slots and reading out the population status of those slots. Except when reading out the status info, it is totally combinatorial. Another project some years ago was using a bunch of 95xxx series chips largely as flip-flops. We had a multi-channel delay device using the AD9501 programmable delay chip, but we wanted it to work like a one-shot, not a delay. So, I needed a LOT of FFs on each board. I looked at other vendor's products, and everybody had their FFs set up to use global clocks, ONLY, no way to individually clock them. Xilinx, however, always has a switch to allow the logic fabric to provide clocks to the FFs. I hope Xilinx will continue to provide these special "hooks" that allow us to do really oddball applications with their FPGAs and CPLDs. JonArticle: 132969
Still no luck... Now when programming finishes, the status register reads all zeros and I can't read the IDCODE from the device at all unless I power cycle the board... I tried changing all kinds of bitgen options I could think of, all to no avail..... Perhaps I should mention that another device in the chain is a Platform Flash, but it is of a wrong size (forgot to upgrade it). I can't replace it now as I am waiting for the new parts to arrive, but I can't see how it can cause any harm while it's blank... // *** BATCH CMD : Program -p 2 Maximum TCK operating frequency for this device chain: 15000000. Validating chain... Boundary-scan chain validated successfully. PROGRESS_START - Starting Operation. '2': Programming device... Match_cycle = NoWait. Match cycle: NoWait done. '2': Reading status register contents... CRC error : 0 Decryptor security set : 0 DCM locked : 0 DCI matched : 0 End of startup signal from Startup block : 0 status of GTS_CFG_B : 0 status of GWE : 0 status of GHIGH : 0 value of MODE pin M0 : 0 value of MODE pin M1 : 0 Value of MODE pin M2 : 0 Internal signal indicates when housecleaning is completed: 0 Value driver in from INIT pad : 0 Internal signal indicates that chip is configured : 0 Value of DONE pin : 0 Indicates when ID value written does not match chip ID: 0 Decryptor error Signal : 0 System Monitor Over-Temperature Alarm : 0 WARNING:iMPACT:2218 - Error shows in the status register, release done bit is NOT 1. INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0000 0000 0000 0000 0000 0000 0000 0000 INFO:iMPACT:579 - '2': Completed downloading bit file to device. Match_cycle = NoWait. Match cycle: NoWait INFO:iMPACT - '2': Checking done pin....done. '2': Programming terminated. DONE did not go high. PROGRESS_END - End Operation. Elapsed time = 30 sec. /Mikhail "MM" <mbmsv@yahoo.com> wrote in message news:6babecF3b35l5U1@mid.individual.net... > Hi Ed, > >> >> I believe that the problem is that the 8.2 software that you are using >> has a hardcoded (not in the BSDL) IDCODE value of 0x01e94093 and this has >> been written into your BIT file. The correct value should 0x01e8c093. >> Try rerunning bitgen to create a newBIT file using 10.1 software (the 9.2 >> might also work, it was just the BSDL file that was wrong in this >> version). > > That's indeed the case. I rebuilt the file with 10.1 bitgen and the IDCODE > problem is gone now. However the Done still doesn't go high... Although I > do see now that something gets loaded in the device, so maybe it's just > the Done signal itself... I am investigating... > > Thanks, > /Mikhail > > >Article: 132970
"PFC" <lists@peufeu.com> wrote in message news:op.ucloonjacigqcu@apollo13.peufeu.com... > > JTAG sometimes is voodoo. > Check your JTAG cables, try to program the flash and read it back to see > if your chain works. Tried already. I can program/erase the flash with no problems. > Try to bypass the flash perhaps disconnect TDO and solder a wire TDI -> > TDO). This is not easy. Both chips are BGAs and the board is 14 layers... > You can also try to make a super simple bitstream like a LED blinker with > all pins tristated except the LED. Yeah, I guess that's the next step... Sigh... /MikhailArticle: 132971
> Still no luck... Now when programming finishes, the status register reads > all zeros and I can't read the IDCODE from the device at all unless I > power > cycle the board... I tried changing all kinds of bitgen options I could > think of, all to no avail..... Perhaps I should mention that another > device > in the chain is a Platform Flash, but it is of a wrong size (forgot to > upgrade it). I can't replace it now as I am waiting for the new parts to > arrive, but I can't see how it can cause any harm while it's blank... JTAG sometimes is voodoo. Check your JTAG cables, try to program the flash and read it back to see if your chain works. Try to bypass the flash perhaps disconnect TDO and solder a wire TDI -> TDO). You can also try to make a super simple bitstream like a LED blinker with all pins tristated except the LED.Article: 132972
Hi, There are three sources for plb master interface. 1) plb_master_single.vhd and plb_master_burst.vhd use a combined read- write controller for the qualifier signals. 2) plb_master.vhd has a split bus architecture that give separate read and write qualifier signals. -I want to use the split bus architecture but the EDK plbv46 IPIF generator generates interfaces that have the combined read write controller. What procedure should I follow in 'Create/Import Peripheral' to generate IPIF that uses split bus architecture. -Also, can I instantiate plb_master directly into IPIF instead of plb_master_burst? So I can use the separate read and write qualifiers. Thanks and Regards, Tejaswy HariArticle: 132973
> Alex, sorry for over-reacting. I am perhaps overly sensitive to > accusations of "marketing hype", since I am very close to Marketing, > but try to curb their excesses. I should have interpreted the smiley > the way you intended it. Engineering vs Marketing, the clash of civilisations... When I read the brochure about the software we created, I needed a stiff drink afterwards. Then the phone rings, no, our software doesn't run on Macs. Really ? Cuz we sold 300 Mac licenses already you know. Eeeeehhh ? Mac Contractor was very happy. An emergency mission to catch the shit before it hits the fan is generally well paid. How not to love work in a company where the big boss has green carpet and a minigolf in his office ? It was fun until the CEO ran away with the cash and the black mercedeses. Ah, startups... Stirs up memories.Article: 132974
> So, here's the idea. Use a FPGA to do the reed-solomon decoding to > accelerate the PAR2 repair/recovery process. The system should utilize > a USB connection to pipe data directly from the disk to the FPGA that > will do the offboard processing of the data. The data transfer should > be controlled by an application on the computer. Why USB ? Gigabit Ethernet would be much faster ;) Don't tell me a Virtex5 can't handle a measly 100 MB/s ;) And... is it a PCI express slot that I see there ? That's even better ! > Second Problem.. > > The XBOX 360 doesn't play x.264 and all the good movies are in x.264. > Converting from x.264 to h.264 could be done offboard on an FPGA > because it takes for-ever to complete on my system (8 hours). This > should have the same premise as the previous issue, minus using a x. > 264 decoding core and possibly directly converting it to h.264 or > doing a decompression-recompression.. I was under the impression that x264 was h264 in disguise. Perhaps tweaking the file format would be enough ? Also you could recode the thing in a much simpler codec like MPEG2 or something, who cares if it takes 10x the size, just stream it in realtime ;) Stick a DVI port on your FPGA ! > SPECS: The development system i'm using is the XILINX ML-505 board > with the Virtex 5 chip. This is a open-source project being done for > fun and learning btw.
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