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On Jun 30, 5:16 am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > Hi, > > I tried to install it on Vista Basic.But facing difficulty in > > installing.I did install the JRE.when I run the timinganalyzer.jar exe > > file It pops me a message saying main class not found exiting !! > > Could u pls help me in fixing the problem ...ur help will be > > appreciated > > Thanks in advance, > > hesh > > I had this when trying a previous release with a version of the JRE > that was to old. Dan say's he's changed things so it should work > with JRE1.5 or later, it might be worth trying with JRE1.6? I have to say I don't understand the need for Java. I get the idea that it allows a single version of an application to run on many different machines and OSs. But it never seems to work very well. For one, most applications have a different look and feel than the typical application on that machine. So the user still has to learn new GUI details. But the big issue is that Java seems to always be buggy! I have a friend who is very much behind Java and the typical question about any Java problem is "do you have the most current release"? The answer is always yes, but the fact that this is the first question says to me that Java is still not stable and full of bugs. Am I missing something with Java? If it is not buggy, why does it always seem to be messing up the windows it draws leaving shattered pieces of glass lying around? So what is the use of having a way to run an application on all platforms if by "running" it means running very poorly? RickArticle: 133601
On Jul 4, 4:57 am, wzab <wza...@gmail.com> wrote: > I have found the following post:http://forums.xilinx.com/xlnx/board/message?board.id=Virtex&thread.id... > So as I can see it was more common problem. > > In the part of my system I have switched to monitoring of the DONE > line instead of the INIT line to detect, that the device have been > deconfigured. Unfortunately in some chips the previous policy is > almost hardcoded (they are the FLASH based CPLDs, which must be > removed from the system to be reprogrammed). This really doesn't sound right. In the post you link to, one guy had a problem, another guy gives him bad information and a third gives him some good advice which is not replied to. I don't see where this shows that this issue is at all "common". Configuration of FPGAs seems much more complex than it really is. The operation of the INIT and DONE lines involve certain time delays and conditions. For example, the INIT signal is not immediately brought low when PROG is brought low. It takes a bit of time, I forget how long, but it is in the data sheet. Are you checking this in a program which may be running too fast? Or does the INIT line *never* go low in the 2% of the cases where it fails? JTAG can override the configuration interface. So be sure that the JTAG signals are pulled to the correct state. My understanding is that the TCK signal should be pulled low, not high to prevent a positive clock edge from being seen on power up. There may be a number of other possible issues in the design. But I would not say it is a problem with the chips... Oh, that reminds me of a real flaw in the Spartan 3 chips. If you are working with the original chips (not the A or E versions) they ended up with much stiffer internal pullups than was planned. As a result, pulling signals low, like the configuration select pins, may not be low enough if you are using resistors instead of 0 ohm jumpers. I think the maximum value for pull down resistors is around 400 ohms... that's right, not 400K ohms, 400 ohms. To be safe, a 0 ohm jumper is good. I don't recall if this affects the JTAG signals, but I expect it would. So the TCK signal needs a 330 ohm resistor to ground I think. RickArticle: 133602
On Sat, 5 Jul 2008 13:43:34 +0200, "Kappa" <78kappa78(at)virgilio(dot)it> wrote: >I have built a QPSK modulator, but I have some doubts about the generation >of SymbolRate variable. > >The SymbolRate range should from 1 to 45 Msymb/s. I intend to use an >external AD9850 DDS, which generates the clock from 1 MHz to 45 MHz for >clockout the Symbol. > >The Symbols (I and Q) is interpolated by x2 or x4. > >How can multiply internally this clock (1 to 45 MHz) by x2 or x4 ? I >remember that the clock is variable. Why not run the external DDS at 4Fsym and then *divide* as necessary in the FPGA? Much easier. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 133603
Hi Jonathan Bromley, > Why not run the external DDS at 4Fsym and then *divide* as necessary > in the FPGA? Much easier. I could use this system, but should I use a DDS from at least 180 MHz ... Some other idea ? Thanks. Kappa.Article: 133604
Goli wrote: > hi, > > I am looking for connecting my proprietary 8 bit bus interface across > two Xilinx FPGAs across the back plane, (10 inch trace). I dont want > to use differential as that would take lot of pins, Is there any > single ended interface that I can use. I dont think LVTTL and LVCMOS > would work at such high speeds, whereas HSTL kind of interfaces can > not drive that long a trace. > > So is there any other IO standard that I can use for this? If you were trying to run at 210 MHz, I'd see where you might need to be more careful. You can use virtually any logic standard to get 70 MHz operation over 10 inches. Since you're point-to-point, I'd suggest using source-series termination which is simply adding a resistor to your front end so your driver impedance plus resistor roughly matches the characteristic impedance of your PC board trace. Simon mentioned you need a ground plane; to get a good impedance without huge crosstalk and other problems, the ground plane is integral to any solid design driven with high edge-rate signals. When you drive a source-terminated signal to VCCIO, the source impedance looks like a resistor divider into the instantaneous load of the transmission line that's about 2ns long on your PC board. While a half-amplitude signal may seem bad conceptually, when the signal reaches the nearly open end of the PC trace, the voltage level doubles as a reflection heads back to the driver. When the reflection finally hits the driver 4ns after the signal starts driving, the voltage level establishes to right around VCCIO with little or no drive current, hence minimal further activity on the line. If you used a heavy drive current without a resistor, the reflection would be much higher than VCCIO and the driver's protection diode would have to swallow a large amount of current for 4ns (round trip time). Not recommended. A single resistor is cheap and easy. LVCMOS and LVTTL give you a broad choice of drive currents. If you wanted to look through the IBIS models for the "best" source impedance match to your PC trace and even *skip* the source series resistor, you'd work well. The tolerance on the drive current at half voltage is sloppy enough that driving harder with a series resistor gives you a more consistent source impedance. Once you get the basics of source series terminations under your belt, the use can be quick and easy in future designs and your signal fidelity will thank you. If you probe this signal to see what it looks like, do so as close to the receiver pin as possible since you'll see the full voltage swing there rather than a couple inches away where you'll see the incident 1/2 voltage before the reflection brings the voltage back to VCCIO. If you use a multi-drop bus instead, this approach is not advised without further investigation and simulation. For a bidirectional bus, the approach is still valid with the series resistor on each end. An open with a series resistor still looks pretty much like an open. The RC time constant of your receiver will be higher but you're talking a very few pF parasitics into a resistor typically 22-49 ohms; both directions look like source series terminated signals. This stuff is great. I would have *no* qualms running a 200 MHz TTL bus with properly selected termination schemes. - John_HArticle: 133605
On Jul 5, 9:33 am, rickman <gnu...@gmail.com> wrote: > On Jun 30, 5:16 am, "Nial Stewart" > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > > Hi, > > > I tried to install it on Vista Basic.But facing difficulty in > > > installing.I did install the JRE.when I run the timinganalyzer.jar exe > > > file It pops me a message saying main class not found exiting !! > > > Could u pls help me in fixing the problem ...ur help will be > > > appreciated > > > Thanks in advance, > > > hesh > > > I had this when trying a previous release with a version of the JRE > > that was to old. Dan say's he's changed things so it should work > > with JRE1.5 or later, it might be worth trying with JRE1.6? > > I have to say I don't understand the need for Java. I get the idea > that it allows a single version of an application to run on many > different machines and OSs. But it never seems to work very well. > For one, most applications have a different look and feel than the > typical application on that machine. So the user still has to learn > new GUI details. But the big issue is that Java seems to always be > buggy! I have a friend who is very much behind Java and the typical > question about any Java problem is "do you have the most current > release"? The answer is always yes, but the fact that this is the > first question says to me that Java is still not stable and full of > bugs. > > Am I missing something with Java? If it is not buggy, why does it > always seem to be messing up the windows it draws leaving shattered > pieces of glass lying around? > > So what is the use of having a way to run an application on all > platforms if by "running" it means running very poorly? > > Rick Hi Rick, Why didn't you follow up your message with that fact that the download was corrupt as the OP said? Please be fair and constructive with any criticisms , don't forget it is in beta testing now and not a final release. BTW, Java is being used by a lot of the big guys, Xilinx, Synopsys, Mentor Graphics for CAD tools. Actually, NASA used Java for parts of the mars rover and other CAD type tools for analysis. In my case, I have found that it is always something in the code that is wrong but is easily fixed. As a one man show, I hoping on feedback from users as beta testers to help find the bugs or features that need improvements. I just don't have the time to do it all and need help testing. But my goal is to make this program the easiest and best way to draw timing diagrams, do timing analysis, and document the results with publishing quality images. So, please focus on the features of the program, not on the language, and help me by recommending improvements, new features, and testing. Regards, DanArticle: 133606
"Pablo" <pbantunez@gmail.com> wrote in message
news:2f27c020-f771-40e2-86b0-05d0675f3290@34g2000hsf.googlegroups.com...
> int main (void) {
> int i;
> int array[100];
> int array1[100];
> for (i = 0; i < 100 ; i++) {
> array[i]=1;
> array1[i]=0;
> }
> dma_init(0xC0000004);
> dma_transfer(&array[0],&array1[0],60);
> return 0;
> }
Where is the stack memory?
Article: 133607Irfan, What ChipScope stuff have you tried so far? Syms.Article: 133608
On Jul 5, 2:02 pm, timinganalyzer <timinganaly...@gmail.com> wrote: > On Jul 5, 9:33 am, rickman <gnu...@gmail.com> wrote: > > > > > On Jun 30, 5:16 am, "Nial Stewart" > > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > > > Hi, > > > > I tried to install it on Vista Basic.But facing difficulty in > > > > installing.I did install the JRE.when I run the timinganalyzer.jar exe > > > > file It pops me a message saying main class not found exiting !! > > > > Could u pls help me in fixing the problem ...ur help will be > > > > appreciated > > > > Thanks in advance, > > > > hesh > > > > I had this when trying a previous release with a version of the JRE > > > that was to old. Dan say's he's changed things so it should work > > > with JRE1.5 or later, it might be worth trying with JRE1.6? > > > I have to say I don't understand the need for Java. I get the idea > > that it allows a single version of an application to run on many > > different machines and OSs. But it never seems to work very well. > > For one, most applications have a different look and feel than the > > typical application on that machine. So the user still has to learn > > new GUI details. But the big issue is that Java seems to always be > > buggy! I have a friend who is very much behind Java and the typical > > question about any Java problem is "do you have the most current > > release"? The answer is always yes, but the fact that this is the > > first question says to me that Java is still not stable and full of > > bugs. > > > Am I missing something with Java? If it is not buggy, why does it > > always seem to be messing up the windows it draws leaving shattered > > pieces of glass lying around? > > > So what is the use of having a way to run an application on all > > platforms if by "running" it means running very poorly? > > > Rick > > Hi Rick, > > Why didn't you follow up your message with that fact that the download > was corrupt as the OP said? Please be fair and constructive with any > criticisms , don't forget it is in beta testing now and not a final > release. I wasn't even talking about your program. I was talking about how so many apps use Java and how it often doesn't seem to work well. I think I explained my concerns in detail. The bottom line is that although it seems to work much of the time, it is much, much less reliable than code written for a given architecture. That may be more work for developers if they want to support a wide range of architectures, but in the end targeted code works well. > BTW, Java is being used by a lot of the big guys, Xilinx, Synopsys, > Mentor Graphics for CAD tools. > Actually, NASA used Java for parts of the mars rover and other CAD > type tools for analysis. I won't argue that at all, in fact that is my point. It is used all over the place and often works poorly. Every time I try to use it and have problems I am told to upgrade to the latest version, even when I *am* using the latest version. I just don't think Java is ready for prime time or maybe it is a usage problem. Either way it has the same result, poorly working apps. > In my case, I have found that it is always something in the code that > is wrong but is easily fixed. > As a one man show, I hoping on feedback from users as beta testers to > help find the bugs or > features that need improvements. I just don't have the time to do it > all and need help testing. > > But my goal is to make this program the easiest and best way to draw > timing diagrams, do timing > analysis, and document the results with publishing quality images. > > So, please focus on the features of the program, not on the > language, and help me by recommending > improvements, new features, and testing. When I am discussing your program I try to give constructive criticism. But I wasn't talking about your program. Rather I was discussing the trend of using Java which is fairly buggy compared to most architecture specific apps. RickArticle: 133609
On Jul 5, 5:36 am, meralonu...@gmail.com wrote: > Xilinx ISE 9.2 and 10.1 (Webpack) > > signal cntr: integer range 0 to 3; > ... > if(clk'event and clk='1') then cntr<=cntr+1; end if; > inferres 2 FFs as I see from the RL schematics. > But when I try to simulate, the simulator does not recognize any upper > limit. That is, it counts limitlessly. > I am a beginner. What is the problem? > Thanks. Yeah, well... the Xilinx simulator is not the best. They even admit that, but say they are working to improve it. This is clearly a simulator bug. When the integer gets incremented above 3, the simulation should stop. RickArticle: 133610
On Sat, 5 Jul 2008 17:26:42 +0200, "Kappa" <78kappa78(at)virgilio(dot)it> wrote: > >Hi Jonathan Bromley, > >> Why not run the external DDS at 4Fsym and then *divide* as necessary >> in the FPGA? Much easier. > >I could use this system, but should I use a DDS from at least 180 MHz ... > >Some other idea ? Sorry, I should have checked the AD9850 data sheet - it's limited to only 60MHz max output frequency. You say you need to vary the symbol rate over 1MHz to 45MHz. What size frequency steps? If you need really smoothly variable frequency, it could be quite tricky... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 133611
I'm using the following code. I've managed to make it work on my fpga
before. but when I try to simulate on my modelsim, it seems that it
never gets into the statemachine.
I've configured the settings for a 50Mhz clock...also set the config
for model sim to be 10ns 10ns for clock high and low.
How should I go about simulating this?
------------------------------------------------------------------------------
--
-- Engineer: Wojciech Powiertowski
--
-- Module Name: transmitter
-- Project Name: UART
-- Description: A VHDL UART controller
--
-- Comments:
-- If your clkFreq or baudRate values are different than you should
-- calculate proper: phase accumulator width and proper tuning word
with
-- the following equations:
-- phaseAccWidth = round(log2((clkFreq/(baudRate))^2))
-- phaseAccTuning = round(baudRate*2^(phaseAccWidth+1)/clkFreq)
--
-- Example:
-- clkFreq = 100000000 -- 100MHz
-- baudRate = 115200 -- 115.2kHz
-- phaseAccWidth = 19.5233 -- round it up to 20
-- phaseAccTuning = 2415.9 -- round it up to 2416
--
-- generated baud will have frequency of 115199.99 which is only
-- 0.000005% different than ideal baud rate of 115200
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity transmitter is
port(
clk : in std_logic;
startTxD : in std_logic;
reset : in std_logic;
dataTxD : in std_logic_vector (7 downto 0);
TxD : out std_logic;
showtick : out std_logic;
busyTxD : out std_logic
);
end transmitter;
architecture TxD_arch of transmitter is
-- phase accumulator constants and core - see details on top of the
file !!!
constant phaseAccWidth : integer := 25;
constant phaseAccTuning : integer := 12885;
signal phaseAcc : std_logic_vector (phaseAccWidth downto 0);
-- signals in design
signal dataBuffer : std_logic_vector (7 downto 0);
signal baudTick : std_logic;
signal state : integer range 0 to 15;
begin
-- baud generator based on phase accumulator
baudTickGen : process (clk) is begin
if(rising_edge(clk))then
phaseAcc <= phaseAcc + phaseAccTuning;
end if;
end process baudTickGen;
-- MSB of phase accumulator generates the proper baud rate
baudTick <= phaseAcc(phaseAccWidth);
-- transmitter: 8 bits of data, no parity control, 1 stop bit
transmitter : process (baudTick) is begin
if(rising_edge(baudTick))then
showtick <='1';
if(reset = '1')then
state <= 0;
dataBuffer <= (others => '0');
else
if(state = 0 and startTxD = '0')then
busyTxD <= '0';
TxD <= '1';
elsif(state = 0 and startTxD = '1')then
TxD <= '0';
dataBuffer <= dataTxD;
busyTxD <= '1';
state <= state + 1;
elsif(state > 0 and state < 9)then
busyTxD <= '1';
TxD <= dataBuffer(state-1);
state <= state + 1;
elsif(state = 9)then
TxD <= '1';
busyTxD <= '1';
state <= 0;
end if;
end if;
end if;
end process;
end TxD_arch;
Article: 133612Hi Jonathan Bromley, > Sorry, I should have checked the AD9850 data sheet - it's limited > to only 60MHz max output frequency. > You say you need to vary the symbol rate over 1MHz to 45MHz. > What size frequency steps? In my application the frequency input of AD9850 is 100MHz, I can safely generate frequencies from 1 to 45 MHz, with step of "100000000 / 2^32" = 0.023283064 Hz. > If you need really smoothly variable frequency, it could > be quite tricky... It is not so difficult, but my problem is to interpolate into the FPGA signal I and Q in order to apply the filter "Baseband Shaping". If I am not mistaken it is necessary to interpolate at least x2 to filter to Nyquist / 2 of SymbolRate. Example: SymbolRate 27500000 (Hz) for Iand Q for apply a "Basebad Shaping" at 13750000(Hz) (Nyquist/2) true output SymbolRate is at least 55000000(Hz) (Interpolated by x2 and filter at 13750000 with SRRC Filter). Is there a way to multiply inside a FPGA a variables clock ? Thanks. Kappa.Article: 133613
"Zhane" <me75@hotmail.com> wrote in message news:ae6c34d6-5951-4523-a905-ab06b5b21333@j22g2000hsf.googlegroups.com... > I'm using the following code. I've managed to make it work on my fpga > before. but when I try to simulate on my modelsim, it seems that it > never gets into the statemachine. > 'Never gets into the statemachine'....is that supposed to mean something? (Hint: It doesn't) > I've configured the settings for a 50Mhz clock...also set the config > for model sim to be 10ns 10ns for clock high and low. > > How should I go about simulating this? > In a word, 'debug'. Put some waveforms up to view, step through the code, look at the signals, however it is that works best for you. It's your design and testbench, it's up to you to figure out what the problem is. Debugging by newsgroup is hardly worth the effort. KJArticle: 133614
Zhane wrote:
> I'm using the following code. I've managed to make it work on my fpga
> before. but when I try to simulate on my modelsim, it seems that it
> never gets into the statemachine.
Maybe rising_edge(baudTick) isn't happening.
Have a look at that wave.
A better design would use clk here
and make baudTick a clock enable.
> I've configured the settings for a 50Mhz clock...also set the config
> for model sim to be 10ns 10ns for clock high and low.
What settings?
I would write my own sim clock process.
> How should I go about simulating this?
I would buy a quartus license to get their oem modelsim.
-- Mike Treseler
Article: 133615I compared the V4FX40 speed files in 8.2 and 10.1 using speedprint utility. There are a few parameters related to BRAM read, where they added second pair of numbers. Otherwise the timing is identical. Since I wasn't sure how and when this second pair of numbers gets used by the tools I ported the design to 10.1 and rebuilt it. This however hasn't fixed my problem, which is the design works up to 60 C and fails after that. This same design used to be very robust in FX20. The timing constraints are met with a margin and I've checked all the unconstrained paths. None of them seem to be relevant. The power seems fine as well. The core voltage is 1.185V, which is a little low, but well within the spec. If I keep the card under good airflow, so that the die temperature never rises above 52 C, it can work for days without any problem... The design is centered around a PPC subsystem, which talks to another card through an async serial interface using UART Lite. When the problem happens, I stop receiving messages from the PPC. At this point the debugger doesn't seem to be able to stop processor properly, so I can't really debug it through software. The clocks in the PPC part of the design aren't fast: the PPC runs at 166 MHz, and the buses run at half of that... I believe the rest of the design, while might be broken as well, doesn't matter for the purpose of this discussion, as the PPC subsystem shouldn't be dying regardless of it. I will appreciate any ideas on what else to check... /MikhailArticle: 133616
On Jul 6, 5:08=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > Irfan, > What ChipScope stuff have you tried so far? > Syms. Hello Symon, Thank you for your reply, i looked at ug029,user guide and some tutorial.i want to go through chipscope inserter and then analyze it. how can i verify a simple program? where i want to give some inputs and look at the output or signal. i have synthesized and opened core inserter through xilinx and then i took one trigger with width 24 and i connected the input and output signals(this is where i am getting problem) for example in xilinx simulator entity ram1 is port( clk:in std_logic; wr_addr:in std_logic_vector(2 downto 0); rd_addr:in std_logic_vector(2 downto0); we:in std_logic; oe:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic_vector(7 downto 0)); end ram1 first i make write operation normally in xilinx simulator i give we =3D1 and wr_addr=3D101 and din 10101010 then after some delay of 10ns i make read operation i give we=3D0 re=3D1 ,oe_addr=3D101 and i get the output dout=3D10101010 now when i want to test in chipscope how can i give din,we,wr_addr and after 10 ns sec how can i give inputs we,re,oe_addr Its very urgent or else u can give some example other than counter using core inserter and analyzer. Thanks in advance IrfanArticle: 133617
On Sun, 6 Jul 2008 11:39:51 -0700 (PDT), irfan.mohammed@gmail.com wrote: >On Jul 6, 5:08 am, "Symon" <symon_bre...@hotmail.com> wrote: >> Irfan, >> What ChipScope stuff have you tried so far? >> Syms. > >Hello Symon, > >Thank you for your reply, > >i looked at ug029,user guide and some tutorial.i want to go through >chipscope inserter and then analyze it. > >how can i verify a simple program? where i want to give some inputs >and look at the output or signal. >now when i want to test in chipscope how can i give din,we,wr_addr > >and after 10 ns sec how can i give inputs we,re,oe_addr There may be a way to do that but I doubt it's in Chipscope. You supply input signals din, we, wr_addr etc just as you normally do in your FPGA. That is, you cannot test a RAM on its own; it must be part of a system (e.g. including a Microblaze processor which writes and reads the RAM) Chipscope will show you whatever activity is on these signals - like an oscilloscope or logic analyzer - but it is not a stimulus generator. (unless things have changed a LOT in 10.1!) - BrianArticle: 133618
On Jul 6, 11:44=A0pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
> "Zhane" <m...@hotmail.com> wrote in message
>
> news:ae6c34d6-5951-4523-a905-ab06b5b21333@j22g2000hsf.googlegroups.com...
>
> > I'm using the following code. I've managed to make it work on my fpga
> > before. but when I try to simulate on my modelsim, it seems that it
> > never gets into the statemachine.
>
> 'Never gets into the statemachine'....is that supposed to mean something?
> (Hint: =A0It doesn't)
>
> > I've configured the settings for a 50Mhz clock...also set the config
> > for model sim to be 10ns 10ns for clock high and low.
>
> > How should I go about simulating this?
>
> In a word, 'debug'.
>
> Put some waveforms up to view, step through the code, look at the signals=
,
> however it is that works best for you. =A0It's your design and testbench,=
it's
> up to you to figure out what the problem is. =A0Debugging by newsgroup is
> hardly worth the effort.
>
> KJ
I did
the baudtick does changes, but it doesnt get into the
if(rising_edge(baudTick))then
showtick <=3D'1';
section. I've no idea why it happens though..since baudtick changes..
there should be a rising edge
Article: 133619On Jul 7, 12:30=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > Zhane wrote: > > I'm using the following code. I've managed to make it work on my fpga > > before. but when I try to simulate on my modelsim, it seems that it > > never gets into the statemachine. > > Maybe rising_edge(baudTick) isn't happening. > Have a look at that wave. > A better design would use clk here > and make baudTick a clock enable. > > > I've configured the settings for a 50Mhz clock...also set the config > > for model sim to be 10ns 10ns for clock high and low. > > What settings? > I would write my own sim clock process. > > > How should I go about simulating this? > > I would buy a quartus license to get their oem modelsim. > > =A0 =A0 =A0 =A0 =A0 -- Mike Treseler I changed the settings of the baudgen to match my 9600bps and my 50Mhz clock. I'm noob, so trying to save some effort from recoding by using this code which I found somewhere ~_~ it did work when I try on the actual fpga...Article: 133620
Zhane wrote: > I've no idea why it happens though..since baudtick changes.. > there should be a rising edge Does the testbench wait for 2*12885 clk cycles per 'tick' Does the testbench drive reset back low? Good luck. -- Mike Treseler PS: Might want to reset showtick. Might want to strobify the MSB and sync up both counters to clk.Article: 133621
On Jul 7, 9:31=A0am, Mike Treseler <mike_trese...@comcast.net> wrote: > Zhane wrote: > > I've no idea why it happens though..since baudtick changes.. > > there should be a rising edge > > Does the testbench wait for 2*12885 clk cycles per 'tick' > Does the testbench drive reset back low? > Good luck. > > =A0 -- Mike Treseler > > PS: > Might want to reset showtick. > Might want to strobify the MSB and sync up both counters to clk. hmm sorry ... i dont understand what you mean by .. > Does the testbench wait for 2*12885 clk cycles per 'tick' > Might want to strobify the MSB and sync up both counters to clk. =3D_=3D!! i only put my reset up for 1 cycle only..the remaining are all lowArticle: 133622
On Jul 5, 12:47 am, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Goli wrote: > > hi, > > > I am looking for connecting my proprietary 8 bit bus interface across > > two Xilinx FPGAs across the back plane, (10 inch trace). I dont want > > to use differential as that would take lot of pins, Is there any > > single ended interface that I can use. I dont think LVTTL and LVCMOS > > would work at such high speeds, whereas HSTL kind of interfaces can > > not drive that long a trace. > > > So is there any other IO standard that I can use for this? > > Does this have to pass any EMC tests ? > Will you need any headroom, or will the Bus NEVER > be faster than 70Mhz ? > There are also 4 bit busses : The intel LPC and QuadSPI > use fewer pins. > > -jg This is proprietary bus and it would not run greater than 70Mhz, but it is bi-directional bus. -- GoliArticle: 133623
On Jul 4, 5:45=A0pm, "Icky Thwacket" <i...@it.it> wrote: > "Zorjak" <Zor...@gmail.com> wrote in message > > news:2a3e6b51-ccf4-4b1c-83cb-3cd1935a5120@m44g2000hsc.googlegroups.com... > > > Hi, > > > I have one question if anyone can give me some clues. I need to > > realize SPI (Serial Pheriferal Interface for my project). Does anybody > > knows is there any free version of this core that can be foud on the > > net. TO be honest, I tought that I will find this easy on the net but > > it turns out that it was not.. I need that my interface be fully > > programed. > > > Please if someone can give me any clue where can I find this. If you > > don't know, some good literature would also help if I must to do it by > > myself from the beginning. > > > Thank you very much > > Zoran > > Christ! It takes about an hour tops to put together an SPI interface. If = you > cannot even do that you should not even be playing with FPGA's! > > Read the SPI interface spec for the peripheral(s) you want to interface a= nd > go design. > > Icky OK, thanks for said that to me Icky ZoranArticle: 133624
"MM" <mbmsv@yahoo.com> wrote in message news:6dchc4F1p6nuU1@mid.individual.net... >I compared the V4FX40 speed files in 8.2 and 10.1 using speedprint utility. >There are a few parameters related to BRAM read, where they added second >pair of numbers. Otherwise the timing is identical. Since I wasn't sure how >and when this second pair of numbers gets used by the tools I ported the >design to 10.1 and rebuilt it. This however hasn't fixed my problem, which >is the design works up to 60 C and fails after that. This same design used >to be very robust in FX20. The timing constraints are met with a margin and >I've checked all the unconstrained paths. None of them seem to be relevant. >The power seems fine as well. The core voltage is 1.185V, which is a little >low, but well within the spec. If I keep the card under good airflow, so >that the die temperature never rises above 52 C, it can work for days >without any problem... > > The design is centered around a PPC subsystem, which talks to another card > through an async serial interface using UART Lite. When the problem > happens, I stop receiving messages from the PPC. At this point the > debugger doesn't seem to be able to stop processor properly, so I can't > really debug it through software. The clocks in the PPC part of the > design aren't fast: the PPC runs at 166 MHz, and the buses run at half of > that... I believe the rest of the design, while might be broken as well, > doesn't matter for the purpose of this discussion, as the PPC subsystem > shouldn't be dying regardless of it. > > I will appreciate any ideas on what else to check... > > > /Mikhail > hi, Speedfiles are often updated (improved ;-) ) with new Service Packs. In many cases the timing information becomes more accurate because Xilinx has more accurate feedback based on their production process. In other words the newer versions more likely represent the timing in the actual silicon. Regards, Stephan
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