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On Jun 18, 3:23 pm, John_H <newsgr...@johnhandwork.com> wrote: > Beantown wrote: > > > Hi John, > > > The tool reports that there could be excessive skew on the clk > > signal. I also have this signal mapped to an IO pin. Maybe that is > > what the tool is complaining about? > > > Thanks for the suggestion of using the FPGA Editor. I will take a > > look to see what is actually going on. > > You probably have it figured out. What I like to do to get clocks to > the outputs is use the IOB DDR flops with opposite DC values on the > the D inputs for the two phases. I get a clock that stays 100% global > and is better correlated to output data generated by that clock. > > - John Hi John, I have dug into the DCM issue a bit more. It looks like it is indeed being routed onto a global clock net after the DCM. I decided to create a simple design to remove the complexity and focus on the DCM. I now have a design that instantiates a 8-bit counter. The tool states it can run at 220+ MHZ. Once, I add the DCM, the frequency is cut in half. Have you seen this behavior from a DCM? It seems strange that the max frequency would be cut in half like this. Thanks.Article: 133176
Beantown wrote: > > Hi John, > > I have dug into the DCM issue a bit more. It looks like it is indeed > being routed onto a global clock net after the DCM. > > I decided to create a simple design to remove the complexity and focus > on the DCM. I now have a design that instantiates a 8-bit counter. > The tool states it can run at 220+ MHZ. Once, I add the DCM, the > frequency is cut in half. Have you seen this behavior from a DCM? It > seems strange that the max frequency would be cut in half like this. > > Thanks. It only makes sense if you have signals in a counter loop that are registered by a different version of the clock, adding unexpected delays. A properly synchronous counter does not care if its clock is from a DCM or from a global input. There's a remote possibility the DCM jitter affects the maximum frequency but the timing budget is only affected by DCM jitter on a few devices, not the whole Xilinx portfolio. I've had a 300 MHz DCM working two synchonous circuits internally in a DDR phased arrangement in a Spartan-3E, no problem. Your timing report should be able to give you the full timing budget. If you look at the report with the DCM and the report without, you should see where they differ so widely. - John_HArticle: 133177
In article <20080619124737.4526bf02@wolfenstein.jpl.nasa.gov>,
Jason Zheng <Xin.Zheng@jpl.nasa.gov> wrote:
>Invoke vsim with -do "log -r *; run -all; quit -f" and -wlf
>"mydump.wlf", and you'll get similar results (just in a different
>format). In my experience ncsim is faster than Modelsim, and of course
>it carries a higher price tag.
This didn't work, but I eventually figured it out:
Start with an empty directory except for some verilog files you want to
simulate:
# Create work directory
vlib work
# Compile verilog files (vcom for vhdl)
vlog tb.v
vlog dut.v
# Simulate
vsim -do "log -r *; run -all; quit -f" work.tb
- this creates a vsim.wlf file with everything in it just
as you say.
Now try to view the waveform. If I try:
vsim -wlf vsim.wlf work.tb -do "view wave; add wave *"
This brings up modelsim GUI and opens the waveform viewer window. All of
signals are in the viewer, and they're all empty.
But this does work:
vsim -view vsim.wlf -do "view wave; add wave *"
but it won't work after you have done the previous vsim -wlf command, vsim
-wlf does something to the .wlf file or sets something in an initialization
file somewhere. I had to re-run the simulation before "vsim -view ..." for
it to work.
BTW, I notice that if I do add
initial
begin
$dumpvars(0);
$dumpon;
...
end
vsim will generate a dump.vcd file, and I can use gtkwave to view it just
fine. I had thought this didn't work, I guess I was wrong or something
changed recently. Maybe I should just forget about using modelsim's
built-in viewer.
I notice that when the GUI is open, I can't also run a simulation on the
command line because there is only one license.
This is modelsim 6.1g which comes with Quartus 8.0 web edition running under
windows.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 133178
On 18 juin, 21:01, "SynopsysFPGAexpress" <fp...@sss.com> wrote:
> As commodity PC hardware and prouctivity applications deline in price, EDA
> tools are as (relatively) expensive as ever, necessitating yet another
> discussion of "Which simulator is right for me?"
>
> The contendors are ...
>
> 1) Aldec Active-HDL
> + great design-flow assistants (state-diagram, block-diagram,
> waveform-diagram editing, export to PDF)
> + possibly faster than Modelsim/PE?
> - no direct support in FPGA design-suites (Webpack/Quartus)
> - Windoze only (can WINE 1.0 run it?)
> - Systemverilog is almost but not quite usable ('package' not
> supported?!?)
> "less than $6000 for mixed-lang. VHDL+Verilog simulation"
> (Note, that configuration is the most basic, doesn't have
> SWIFT/Smartmodel)
> [first year pepetual-license, yearly maint. is additional 20%/year]
One vote for Active-HDL. I briefly used Modelsim before we bought
Active-HDL and for me anyway, the Active-HDL interface is much better.
It's true that it's not officially supported by Xilinx but in practice
that really never caused too much of a problem.
I really like to create a schematic top level with blocks that are
either more schematics themselves or directly vhdl blocks. That way
it's much easier to see how everything connects together, it helps
comprehension. I don't quite understand why some people insist on
writing direct VHDL connections between blocks. It's a little bit like
insisting on writing pspice netlists for simulations instead of using
the schematic editor. Active-HDL converts schematics to vhdl code
anyway, so it's never too late to go back to vhdl-only code. The
resulting code will be very clean if you keep your top level free of
logic.
The state-machine editor in Active-HDL is another story. To me simple
state machines don't need to be represented by a diagram to be
understood. On the other hand, large ones are hard to represent in a
diagram. So in the end I only write vhdl state machines.
Patrick
Article: 133179
Jeff Cunningham wrote:
>
> Speaking of FPGA alternatives, this recently caught my eye. Don't know
> much about it, but it sure looks cool:
>
> http://www.tilera.com/products/processors.php
Availability? Price?
Dave
Article: 133180On 19 Jun., 21:53, Beantown <ghouri...@gmail.com> wrote: > I decided to create a simple design to remove the complexity and focus > on the DCM. =A0I now have a design that instantiates a 8-bit counter. > The tool states it can run at 220+ MHZ. =A0Once, I add the DCM, the > frequency is cut in half. =A0Have you seen this behavior from a DCM? =A0I= t > seems strange that the max frequency would be cut in half like this. That probably is the input clock frequency. If you feed a 200MHz counter through a 2x DCM the input clock can only run at up to 100MHz before the maximum frequency of the counter is exceeded. Kolja SulimmaArticle: 133181
"Dave" <dave@comteck.com> wrote in message news:f008$485ae84d$40b83d5e$25934@COMTECK.COM... > Jeff Cunningham wrote: >> >> Speaking of FPGA alternatives, this recently caught my eye. Don't know >> much about it, but it sure looks cool: >> >> http://www.tilera.com/products/processors.php > > Availability? Price? Nvidia. Google. Yes. Cheap.Article: 133182
MikeWhy wrote: > "Dave" <dave@comteck.com> wrote in message > news:f008$485ae84d$40b83d5e$25934@COMTECK.COM... >> Jeff Cunningham wrote: >>> >>> Speaking of FPGA alternatives, this recently caught my eye. Don't >>> know much about it, but it sure looks cool: >>> >>> http://www.tilera.com/products/processors.php >> >> Availability? Price? > > Nvidia. Google. > > Yes. Cheap. MikeWhat?Article: 133183
"Mike Treseler" <mtreseler@gmail.com> wrote in message news:4859F704.2040001@gmail.com... > SynopsysFPGAexpress wrote: >> As commodity PC hardware and prouctivity applications deline in price, >> EDA tools are as (relatively) expensive as ever, necessitating yet >> another discussion of "Which simulator is right for me?" > > This reads like a thinly veiled marketing survey. It is, I apologize if I mislead anyone. I wanted to hear other people's choices and compare them to my situation. >> Kidding aside, my real requirements: > Which part were you kidding about? For gHDL and Icarus Verilog, I said "emacs/gvim not included." It was a poor attempt at humor. >> 1) I foresee mixed-HDL as a *requirement* for any serious consulting job. >> (Xilinx and Altera are pretty good about providing 'HDL-neutral IP', but >> third-parties aren't.) > > The device vendors are only HDL-neutral because > they are selling device netlists, not source code. > Not a plus in my book. That's something I didn't think about, and I checked Xilinx's website. It turns out, some of their IP-blocks (Microblaze, PCIe, PPC440, etc.) use a new 'SecureIP' format, and so far, only Modelsim is supported. That doesn't bode well, either... http://www.xilinx.com/support/answers/30481.htmArticle: 133184
On Jun 19, 12:35 pm, John_H <newsgr...@johnhandwork.com> wrote: > rickman wrote: > > I am running Synplify from the Lattice ispLever tools and every time I > > compile the design Synplify beeps when it is started and beeps when it > > finishes. It is a lot louder than the other sounds the computer makes > > and is a very irritating noise. They have a control to turn it off, > > but I can't figure out how to make the control stay off from one run > > to the next. It seems to default to beeping. > > > Anyone know where this configuration is stored? How do I turn it off > > permanently? > > > Rick > > Rick, > > My tool liscensed so I'm not sure if it's the same as what you're > working with. My ispLever Project Manager has the ability to launch > "Synplify Pro Synthesis" from the Tools menu. Once in Synplify Pro, > the Options menu "Project View Options..." has "Beep when a job > completes" checkbox on the second line. This is SynplifyPro for > Lattice 9.4L launched from the 7.1 Lattice tool suite. > > - John_H Hi John, thanks for the info. My version is licensed, but it is just the Lattice specific version. I see the same setting in the same dialog box. When I select it, it stays set (or unset) as long as I don't exit Syniplify. But when it quits and I run it again, the box is once again checked. I thought I would hand edit the setup file, but I can't find it. RickArticle: 133185
On Jun 19, 2:35 pm, Kevin Neilson <kevin_neil...@removethiscomcast.net> wrote: > SynopsysFPGAexpress wrote: > > As commodity PC hardware and prouctivity applications deline in price, EDA > > tools are as (relatively) expensive as ever, necessitating yet another > > discussion of "Which simulator is right for me?" > > > The contendors are ... > ... > > If you have Xilinx ISE 10.1, check out ISIM, which comes "free" with it. > It's much improved and may meet your needs and in future releases > should have better a better user interface. I don't think it currently > supports SystemVerilog, (and you are correct in propagating your > religion) but might soon. Modelsim is still the best, but you pay for a > lot of things you don't really need, and the waveform viewer could be > improved. That's where you spend 90% of your time during debugging so > it should be a little easier to use. > -Kevin Apologies if you are a Xilinx person, but I tried their Web Pack edition with the in house tools and the simulator really sucks... or blows or something not so good. Although I didn't see any issues with the simulation speed, the compile speed is pretty slow. I was using it for a while when my design was pretty small and the compiles were taking half a minute. Using Aldec Active HDL the compiles take a second for a much larger design and the simulation speed is not bad considering that it is "crippled"ware. Xilinx seems committed to improving their in house sim. I posted about in a news group and got a reply from one of the developers which was almost apologetic and sincerely interested in what I found lacking. In the meantime I expect to stick with commercial packages. When I do make the switch, it will likely be to an open source simulator. RickArticle: 133186
On Jun 19, 6:10 pm, Patrick Dubois <prdub...@gmail.com> wrote:
> On 18 juin, 21:01, "SynopsysFPGAexpress" <fp...@sss.com> wrote:
>
>
>
> > As commodity PC hardware and prouctivity applications deline in price, EDA
> > tools are as (relatively) expensive as ever, necessitating yet another
> > discussion of "Which simulator is right for me?"
>
> > The contendors are ...
>
> > 1) Aldec Active-HDL
> > + great design-flow assistants (state-diagram, block-diagram,
> > waveform-diagram editing, export to PDF)
> > + possibly faster than Modelsim/PE?
> > - no direct support in FPGA design-suites (Webpack/Quartus)
> > - Windoze only (can WINE 1.0 run it?)
> > - Systemverilog is almost but not quite usable ('package' not
> > supported?!?)
> > "less than $6000 for mixed-lang. VHDL+Verilog simulation"
> > (Note, that configuration is the most basic, doesn't have
> > SWIFT/Smartmodel)
> > [first year pepetual-license, yearly maint. is additional 20%/year]
>
> One vote for Active-HDL. I briefly used Modelsim before we bought
> Active-HDL and for me anyway, the Active-HDL interface is much better.
> It's true that it's not officially supported by Xilinx but in practice
> that really never caused too much of a problem.
>
> I really like to create a schematic top level with blocks that are
> either more schematics themselves or directly vhdl blocks. That way
> it's much easier to see how everything connects together, it helps
> comprehension. I don't quite understand why some people insist on
> writing direct VHDL connections between blocks. It's a little bit like
> insisting on writing pspice netlists for simulations instead of using
> the schematic editor. Active-HDL converts schematics to vhdl code
> anyway, so it's never too late to go back to vhdl-only code. The
> resulting code will be very clean if you keep your top level free of
> logic.
I use a purely HDL hierarchy. I find that top level schematics or
even low level schematics of large functions tend to end up being more
like a net list than a drawing anyway. You have pins with names X,Y,Z
connected to net R,S,T on page 1. On page 2 you have nets R,S,T
connected to another part with pin names A,B,C. Making it a drawing
doesn't add much in my opinion. Once I gave up hope for schematics
and embraced the HDL world, I found joy in a life of text files and
the infinite advantages they have in the land of version control!
> The state-machine editor in Active-HDL is another story. To me simple
> state machines don't need to be represented by a diagram to be
> understood. On the other hand, large ones are hard to represent in a
> diagram. So in the end I only write vhdl state machines.
I agree. Again a diagram can only offer a bit more here than can the
HDL text file, but I don't like using special tools that make the code
more difficult to port. Keeping it in HDL can work well and has all
of those text and portability advantages.
Rick
Article: 133187
MikeWhy wrote:
>
> "Dave" <dave@comteck.com> wrote in message
> news:f008$485ae84d$40b83d5e$25934@COMTECK.COM...
>>
>> Availability? Price?
>
> Nvidia. Google.
>
> Yes. Cheap.
Really? I got _no_ hits on google for the middle speed-range part
number. Where did you find it available from? Price?
Dave
Article: 133188"Dave" <dave@comteck.com> wrote in message news:4a422$485b1cf1$40b83d5e$30449@COMTECK.COM... > MikeWhy wrote: >> >> "Dave" <dave@comteck.com> wrote in message >> news:f008$485ae84d$40b83d5e$25934@COMTECK.COM... >>> >>> Availability? Price? >> >> Nvidia. Google. >> >> Yes. Cheap. > > Really? I got _no_ hits on google for the middle speed-range part number. > Where did you find it available from? Price? The C870 is $1300, Nvidia direct or second sourced. The C1060 is slated for fall release. Try tesla@nsc-nvidia.com for more directed info. Would you like the phone number also? Here: For Information on How to Purchase Call 408.392.4120Article: 133189
"Symon" <symon_brewer@hotmail.com> wrote in message news:g3esnp$l2b$1@aioe.org... > MikeWhy wrote: >> "Dave" <dave@comteck.com> wrote in message >> news:f008$485ae84d$40b83d5e$25934@COMTECK.COM... >>> Jeff Cunningham wrote: >>>> >>>> Speaking of FPGA alternatives, this recently caught my eye. Don't >>>> know much about it, but it sure looks cool: >>>> >>>> http://www.tilera.com/products/processors.php >>> >>> Availability? Price? >> >> Nvidia. Google. >> >> Yes. Cheap. > > MikeWhat? Second cousin. (Full initials. Also a pronunciation aid. You get my age and you'll find the dimunitive inappropriate also.)Article: 133190
MikeWhy wrote: > "Dave" <dave@comteck.com> wrote in message > news:4a422$485b1cf1$40b83d5e$30449@COMTECK.COM... >> MikeWhy wrote: >>> >>> "Dave" <dave@comteck.com> wrote in message >>> news:f008$485ae84d$40b83d5e$25934@COMTECK.COM... >>>> >>>> Availability? Price? >>> >>> Nvidia. Google. >>> >>> Yes. Cheap. >> >> Really? I got _no_ hits on google for the middle speed-range part >> number. Where did you find it available from? Price? > > The C870 is $1300, Nvidia direct or second sourced. The C1060 is slated > for fall release. > Ahh. The old switcheroo. Jeff wrote about the Tilera TILE64 processor and I asked about its availability and price. You decided to give availability and price (sort of) on Nvidia's Tesla GPU card. "Dave" <dave@comteck.com> wrote in message news:f008$485ae84d$40b83d5e$25934@COMTECK.COM... > Jeff Cunningham wrote: >> >> Speaking of FPGA alternatives, this recently caught my eye. Don't know much about it, but it sure looks cool: >> >> http://www.tilera.com/products/processors.php > > Availability? Price?Article: 133191
Hai, I red the following pdf and it was useful http://www.dsp-fpga.com/pdfs/Lattice.RG07.pdf can anyone guide me how to use fprintf as the following gives an error a = fi( 0.213412, 1, 16, 15 ) fprintf(outfile1, '%f\n', a); I tried hitting in google and didn't get the answer for my problem.. regards, fazal John_H wrote: > faza wrote: > <snip> > > > > My input bits width is 16 > > coefficient bit width is 16 > > output width is 40 > > > > regards, > > faza > > > > > > > > > > > > > > On Jun 19, 9:20 am, Jeff Cunningham <j...@sover.net> wrote: > >> faza wrote: > >>> If i use fixed to integer conversion using left shift operation...I am > >>> not sure i may be thrown with compilation error as the maximum long > >>> int i can is 2^32 only.. > >>> so if i have such a long 0.99999999999999999998888888888888777777777 > >>> iit is impossible to have such a big int converted value.. > > <snip> > > You continue to demonstrate an extremely weak grasp on simple concepts. > While I still encourage you to talk to your professors and *choose > another pursuit* for your final year project, I'll point out that your > declaration that these tiny 32 bit integers are too small to accommodate > your numbers like 0.99999999999999999998888888888888777777777, you state > you have 16 bit input widths and 16 bit coefficients. That number is so > much larger than 16 bits it's silly. > > FIRs need limited size for their operands. You seem to now specify > reasonable constraints on your coefficient and data but do you know why > those values are chosen or did your professor or Matlab (or paperboy) > tell you you needed these realistic values? > > Because precision isn't free, all digital filtering has "quantization > effects" which can affect the filter characteristics and/or noise > generated by your filter, even stability in IIR filters. > > You need to know many characteristics of the filter you're trying to > implement to properly size an FIR in taps, input width, and coefficient > width. It's incomplete to declare a "cutoff frequency" and think you > are ready to design. Do you know your required passband ripple? > Stopband attenuation? Steepness of your cutoff? > > You need to 1) research more what digital filter requirements are needed > for your FIR implementation, 2) understand various ways digital filters > are implemented (or at least research the FIR), and 3) learn how to do > hardware design with FPGAs. This last item will set you back months by > my guess. > > PLEASE choose another project with which you can succeed.Article: 133192
On 18 juin, 17:24, biancim...@gmail.com wrote: > The cypress controller you mentioned (68013a) is a nice peripheral > controller, but it is unfortunately not a host. Cypress does have a > range of easy to use host chips, but this is not one of them (and last > I checked none of them were high speed). Connecting a flash drive > (which is also a 'peripheral' or 'device') requires a host interface. > The cypress chip, however could be easily used to download files from > a PC or other portable host. I just understand that ! It's a shame but I don't have the choice ... > The easiest way to interface the 68013a to a host is simply to > configure it in Slave FIFO mode, such that you merely monitor the > levels of the various endpoints, and read off the data. The endpoints > as well as the operating state are configured by the onboard > microcontroller. The configuration can be done via an external EEPROM > if your board has one, or by downloading over USB and > 'renumerating'. > > We use this chip as a cheap interface for a monitoring application, > just by filling up the fifos as we receive the data. > > Hope this helps. I am going to read more about Slave FIFO, but it seems to be quite complicated. Thank you for your help ! XArticle: 133193
hi all: I have a question about stratix II .An oscillator must drive a constant clock frequency to an FPGA pin. The maximum frequency limit depends on the speed grade of the FPGA. Frequencies of 50 MHz or less should work for most boards.If my oscillator is less than 50 MHz ,how to work about this system ? If about PLL ,I want to know how dose PLL work. 1. Does PLL function automatically or need manual configure to initial PLL in the system? 2. Dose PLL reference anything or any paremeter to lock the frequency? What is the paremeter? Thanks in advance.Article: 133194
MikeWhy wrote: > "Symon" <symon_brewer@hotmail.com> wrote in message > news:g3esnp$l2b$1@aioe.org... >> MikeWhy wrote: >>> "Dave" <dave@comteck.com> wrote in message >>> news:f008$485ae84d$40b83d5e$25934@COMTECK.COM... >>>> Jeff Cunningham wrote: >>>>> >>>>> Speaking of FPGA alternatives, this recently caught my eye. Don't >>>>> know much about it, but it sure looks cool: >>>>> >>>>> http://www.tilera.com/products/processors.php >>>> >>>> Availability? Price? >>> >>> Nvidia. Google. >>> >>> Yes. Cheap. >> >> MikeWhat? > > Second cousin. > > (Full initials. Also a pronunciation aid. You get my age and you'll > find the dimunitive inappropriate also.) I thought your second cousin might explain what Nvidia had to do with Tilera. I see another branch of the thread has cleared that up! :-) Cheers, Syms.Article: 133195
> as the following gives an error > a = fi( 0.213412, 1, 16, 15 ) > > fprintf(outfile1, '%f\n', a); > > I tried hitting in google and didn't get the answer for my problem.. Try the matlab help first, IMHO it has some of the best help documentation out there. E.g. type "help fprintf" at the matlab prompt. Its hard to help if you don't provide the error message :). Here is a hint: ask yourself what is the type of a, and what type is expected by %f. Cheers AndrewArticle: 133196
Xilinx Spartan 3E starter kit.
process (boff, bon )
begin
if (boff= '1') then
led <= '0';
else
if (bon'EVENT AND bon = '1') then
led<='1';
end if;
end if;
end process;
generates a D-FF with D connected to Vcc, clk connected to bon, Rst
connected to boff and O connected to led.
This is very Ok. bon turns the led on and boff turns it off. That was
what I wanted but..
ISE Simulator does not allow me to create a waveform I wish for bon
input on the grounds that it is a clock. How come?
Article: 133197Hi, After reading over the documentation for DDR2 and the SSTL signalling standard, I have a question about the role of termination in DDR2. It appears to me that in addition to the usual termination function, the resistors provide some sort of biasing function around the Vref (1.8v/2) point. Is it the case that the IO on the DDR2 modules can "swing" around that midpoint without the presence of termination resistors, or are these necessary for correct operation (even using On- Die Termination). What I would like to know is whether, in addition to the unidirectional signals (Address, etc...) that do not have ODT, it is necessary to terminate the Bidirectional signals (even with ODT)? Thanks for your assistance, StephenArticle: 133198
Hai, a= fi(output,1,16,15); line 43:fprintf(outfile1, '%f\n', a); The following is the error for the above: ?? Error using ==> fprintf Function is not defined for 'embedded.fi' inputs. Error in ==> imp_o at 43 fprintf(outfile1, '%f\n', a); regards, faza Andrew FPGA wrote: > > as the following gives an error > > a = fi( 0.213412, 1, 16, 15 ) > > > > fprintf(outfile1, '%f\n', a); > > > > I tried hitting in google and didn't get the answer for my problem.. > Try the matlab help first, IMHO it has some of the best help > documentation out there. > E.g. type "help fprintf" at the matlab prompt. > > Its hard to help if you don't provide the error message :). Here is a > hint: ask yourself what is the type of a, and what type is expected by > %f. > > Cheers > AndrewArticle: 133199
Steve wrote: > Hi, > > After reading over the documentation for DDR2 and the SSTL signalling > standard, I have a question about the role of termination in DDR2. > > It appears to me that in addition to the usual termination function, > the resistors provide some sort of biasing function around the Vref > (1.8v/2) point. Is it the case that the IO on the DDR2 modules can > "swing" around that midpoint without the presence of termination > resistors, or are these necessary for correct operation (even using > On- Die Termination). What I would like to know is whether, in > addition to the unidirectional signals (Address, etc...) that do not > have ODT, it is necessary to terminate the Bidirectional signals > (even with ODT)? > > Thanks for your assistance, > > Stephen Hi Stephen, Have a look at Sheet 13 of this:- http://www.xilinx.com/support/documentation/boards_and_kits/ml50x_schematics.pdf There are no terminations on the ODT signals to the DDR2 SODIMM, because the ODT takes care of it. HTH., Syms.
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