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Svenn Are Bjerkem <svenn.bjerkem@googlemail.com> writes: > am looking at how to do syntax checking on single files. Tried to run I usually run the simulator from within the text editor (emacs in my case) to do this. Cyping C-c C-k will do this in VHDL mode. In Verilog mode you can run a linter if you have one. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 138801
On 5 Mar, 19:58, goo...@twinmail.de wrote: > On 5 Mrz., 14:10, deep <infoparaj...@gmail.com> wrote: > > > hi everyone, > > tool : xilinx spartan 3a dsp > > system overview : image taken form digital camera (c3038) connected to > > fpga needs to be stored in simple dual port BRAM (written in one port > > and read from other)and displayed on vga monitor. In default, image size would be 352 X 288 16-bit for ov6630 used by c3038. And I think its 8.9285 MHz in default mode. If you use only 8-bit Y data, that would require around 99KB of memory. Using external memory: display one complete stored frame while another frame gets stored and therefore requiring 2 times the 99KB of memory. But from your post it seems you need to display without storing the complete frame!!!, Hmm, that seems to be a bit more difficult problem. Just duplicating the each pixel three time to be display in VGA may look to be simple solution. But then, there is a problem to map each line with corresponding line on VGA. 352 pixels of camera of each line cannot be mapped to multiple lines of VGA. Any other people here confronted with the similar problem? > > problem statement : digital data given by camera (c3038) written on > > RAM at 17Mhz,but for VGA monitor display these data needs to be read > > at 25Mhz, .i want to take the advantage of two independent clocks of > > dual port bram,but the data should neither be overwritten nor be lost. > > any idea regarding the problems are appreciated. > > hi, > your read clock is about 3 times faster than necessary > so there will be gaps during the data transfer that can > be used for synchronisation of input and output data. > > Draw a time scheme of incoming data und outgoing data. > Check how it can be matched without overlapping. > > Use two memory banks for storing the incoming pics. > (Thats just one more adress line that toggles on every new picture) > > Hope that was helpful. > Regards > =A0 EilertArticle: 138802
On Mar 11, 5:44=A0pm, jacko <jackokr...@gmail.com> wrote: > Hi > > many fixes, now offered open licence, of 1 core per FPGA/CPLD/ASIC > with the restriction that the K Ring logo must appear ontop the chip > or close to it on the PCB, and any documentation produced must credit > copyright to K Ring technologies, and provide the URL to the sitehttp://n= ibz.googlecode.com > > The gforth port is not complete but contains many machine code > examples, including a boot loader for sd card. > > cherrs > Simon jackson, BEng. > Creative technologist > K Ring Technologieshttp://nibz.googlecode.com Hi i do not think BSD license allows you to request the logo to printed on chip or PCB also not to require additional url infos to be present addtional to the copyright notice in the license itself. so if you have made it public under BSD license then it is covered under BSD license.. no other implications apply Antti PS i have hard times understanding your nibz thing, sorry.. maybe my brain is not screwed enough to understand it ;)Article: 138803
On Mar 10, 9:52=A0pm, newman5...@yahoo.com wrote: > On Mar 10, 7:48=A0am, "jag9624" <ma...@grahsl.net> wrote: > > > > > Hello Everybody ! > > > I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitter > > with a Virtex 4 FX12. > > > What troubles me is the movement of data words from the slow system clo= ck > > to the faster serializer clock (fast clock is multiples of slow clock). > > Since the clocks are phase aligned by the dcm, i don't see nescessity f= or > > using an async fifo, but i fail to find a simpler solution. > > > Currently i have three clocks: 100mhz(system clock), 20mhz(marking lvds > > word periods) and 140mhz(DDR serializer). > > Is there any possibility for each clock domain to mark the clock cycle > > which is aligned with all other clocks ? If all clock domains were > > conscious about their aligment with the other clocks, data transfers co= uld > > be arranged in w way that avoids metastabilities. > > > My idea of aligning a fast clock to a slow clock (namely 140mhz to 20mh= z > > =3D> 7 bit cells): > > > State machine running in fast clock: > > > =A0state_wait_sync_0 (reset_state): > > =A0 when slow clock is low go to state_wait_sync_1 > > > =A0state_wait_sync_1: > > =A0 when slow clock is high go to bitcell_1 > > > =A0bitcell_1 > > =A0 goto bitcell_2 > > .. > > =A0bitcell_5 > > =A0 enable_load_data_from_slow_clock > > =A0 goto bitcell_6 > > > =A0bitcell_6: > > =A0 goto bitcell_0 > > > =A0bitcell_0 > > =A0 goto bitcell_1 > > > enable_load_data_from_slow_clock enables a flipflop to register data fr= om > > slow clock at bitcell_5 to grant the signal from slowclock FF enough se= tup > > time to fastclock FF. > > > As simple as that, BUT, i am sampling a clock in transition with a phas= e > > aligned clock (at wait_sync_*). This obviously does not work. So how ca= n > > this be done ? I am curious, there must me a standard method... > > > Thanks and best regards, > > Julian Grahsl. > > You might want to check out XAPP855 16-Channel, DDR LVDS Interface > with Per-Channel Alignment. =A0It is for a Virtex-5 but many of the > components sited are in the Virtex 4. =A0(oserdes, oddr, FIFO16 etc.) 8:1 serializing is pretty easy. 7:1? Not so much. -aArticle: 138804
Hi > PS i have hard times understanding your nibz thing, sorry.. > maybe my brain is not screwed enough to understand it ;) A minimal microprocessor for tight logic area constraints. A minimal microprocessor for such large component technologies like optical/ photonic computing. A minimal microprocessor for developing 1000+ core SoC designs. A minimal microprocessor for super low power applications/ A minimal microprocessor for designing/executing highly portable and simple to bootstrap implement languages. In general then a minimal microprocessor. The BSD licence is open source yes, but it does not limit ME to only offering a BSD licence. Maybe there are people who do not wish to use the BSD licence, but would be happy with the above licence. cheers jackoArticle: 138805
On Mar 11, 8:01=A0pm, Jacko <jackokr...@gmail.com> wrote: > Hi > > > PS i have hard times understanding your nibz thing, sorry.. > > maybe my brain is not screwed enough to understand it ;) > > A minimal microprocessor for tight logic area constraints. A minimal > microprocessor for such large component technologies like optical/ > photonic computing. A minimal microprocessor for developing 1000+ core > SoC designs. A minimal microprocessor for super low power > applications/ A minimal microprocessor for designing/executing highly > portable and simple to bootstrap implement languages. In general then > a minimal microprocessor. > > The BSD licence is open source yes, but it does not limit ME to only > offering a BSD licence. Maybe there are people who do not wish to use > the BSD licence, but would be happy with the above licence. > > cheers jacko so how much stack you get into the maxII- 570? i'm just curious AnttiArticle: 138806
Antti.Lukats@googlemail.com wrote:
> On Mar 11, 8:01 pm, Jacko <jackokr...@gmail.com> wrote:
>
>>Hi
>>
>>
>>>PS i have hard times understanding your nibz thing, sorry..
>>>maybe my brain is not screwed enough to understand it ;)
I too found the description hard to understand, which is a pity
because there may be some interesting ideas hiding there.
>>A minimal microprocessor for tight logic area constraints. A minimal
>>microprocessor for such large component technologies like optical/
>>photonic computing. A minimal microprocessor for developing 1000+ core
>>SoC designs. A minimal microprocessor for super low power
>>applications/ A minimal microprocessor for designing/executing highly
>>portable and simple to bootstrap implement languages. In general then
>>a minimal microprocessor.
Yes, yes, it is clear that these are the goals. But what is the
processor architecture? The description of the registers and
instructions is very hard to understand. For example, you say that
there is an instruction called "BA" and describe its "Details" as
"BA (R)->P - Back". That is far from clear.
You seem to be using some kind of personal abbreviated notation and
terminology, perhaps based on Forth (in which I am not fluent). If
you want to attract users to this processor, make an effort to
describe its architecture in common prose, and include some
examples with explanations.
--
Niklas Holsti
Tidorum Ltd
niklas holsti tidorum fi
. @ .
Article: 138807Hi, I am inexperienced in CPLD design. I am using a slow CPU (PC ISA port) and LUT based CPLD (Altera MAX II) in my design. I implemented many control registers (implemented with D FF) in the CPLD that the CPU will write from time to time. The ISA bus is slow, with a write cycle of several hundred ns. The CPLD is running on 50ns primary clock. I am facing two choices of implementing the register writing signals. 1. The WRITE\ (active low) signal as a secondary global clock. The CS\ and address lines will be decoded into ENABLE signal for those D FFs. The drawback is that I will have two clock domains in the same chip. This was the approach I took, but now I start to be suspicious about it. 2. The WRITE\, CS\, address lines as regular signals, are synced first to the 50ns clock, and then decoded into ENABLE signals for those D FFs. Since the ISA write cycle is much longer than 50ns, I guess this strategy will work too. Please help me to make the right decision. What is the common approach people take for this kind of problem? Thank you. vax9000Article: 138808
On Wed, 11 Mar 2009 11:49:03 -0700 (PDT), VAX9000@gmail.com wrote: >Hi, > I am inexperienced in CPLD design. I am using a slow CPU (PC ISA >port) and LUT based CPLD (Altera MAX II) in my design. I implemented >many control registers (implemented with D FF) in the CPLD that the >CPU will write from time to time. The ISA bus is slow, with a write >cycle of several hundred ns. The CPLD is running on 50ns primary >clock. > >I am facing two choices of implementing the register writing signals. You can't be VERY inexperienced - you are asking the right question :-) The ISA bus is so dog-slow that it is almost certainly easiest to oversample the write strobe and use that to establish a write-enable, synchronous to the internal 20MHz clock, occurring at a time when you know that the write address and data are stable. If the write strobe is shorter than 3 internal clock cycles, it's not safe to do oversampling and instead you need to implement a handshake across the clock domains. This is sure to be more troublesome, although it's not too hard. Good luck! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138809
Hi,
I wanted to preload my counter with a number, so I used the
asynchronous set and reset signal. In the following code the CS and WR
are asynchronous and much longer than CLK.
EN will be '1' sometime after the preloading is done.
process ( the list ...)
begin
if CS='1' and WR='1' then
counter <= DATA;
else if CLK'event and CLK='1' then
if EN='1' then
counter <= counter + '1';
end if;
end if;
end process
This code worked (on Altera MAX II), but now I suspect that there is
better way. Do I better change to synchronous preloading? I am
thinking of something like this,
if CLK'event and CLK='1' then
if CS='1' and WR='1' then
counter <= DATA;
else if EN='1' then
counter <= counter + '1';
end if
end if
Since CS and WR are much longer than the CLK period, and will be
sync'ed first, I guess this code would work too. Is this a better way
to do? Please let me know. Thank you!
vax9000
Article: 138810> >8:1 serializing is pretty easy. 7:1? Not so much. > >-a Tell be about it :-) FYI: I disassembled a handheld computer and want to drive the LCD Panel which requires this format... To be able to use a DDR Register and to keep clock speed low, i combine two 7bit frames into one 14bit frame which is easier to build. So in fact i have built a 14:1 serializer but with two clock periods per frame. julianArticle: 138811
On Mar 11, 3:00=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Wed, 11 Mar 2009 11:49:03 -0700 (PDT), VAX9...@gmail.com wrote: > >Hi, > > =A0I am inexperienced in CPLD design. I am using a slow CPU (PC ISA > >port) and LUT based CPLD (Altera MAX II) in my design. I implemented > >many control registers (implemented with D FF) in the CPLD that the > >CPU will write from time to time. The ISA bus is slow, with a write > >cycle of several hundred ns. The CPLD is running on 50ns primary > >clock. > > >I am facing two choices of implementing the register writing signals. > > You can't be VERY inexperienced - you are asking the right > question :-) > Thank you for your answer. I am an experienced TTL amateur designer, but CPLD or FPGA is different, especially when I could not watch the resulted routing because I am using the free web- software. It is like working in the darkness with a pair of sunglasses. > The ISA bus is so dog-slow that it is almost certainly > easiest to oversample the write strobe and use that to > establish a write-enable, synchronous to the internal 20MHz > clock, occurring at a time when you know that the write > address and data are stable. > > If the write strobe is shorter than 3 internal clock cycles, > it's not safe to do oversampling and instead you need to > implement a handshake across the clock domains. =A0This is > sure to be more troublesome, although it's not too hard. > I think you suggested the single clock domain solution. I will give it a try. Thank you! > Good luck! > -- > Jonathan Bromley, ConsultantArticle: 138812
Hi, I am having difficulty understanding the role of NGC and NGD files. It is my understanding that NGC files are netlists (or synthesised versions) of individual modules within a design. These can be combined to form either an other NGC file, or an NGD file. In the process of doing this the tool (NGCBUILD or NGDBUILD), searches it's paths to find other NGC (or EDIF) files corresponding to the netlists of instantiated modules within it's current top-level block. In essence, NGCBUILD/NGDBUILD is like a linker (in software) linking together various object files to create one executable (resolving an internal "black boxes" automatically). It appears that within the Xilinx tools (PLATGEN especially), it is common to invoke NGCBUILD on an NGC file, without it pulling in other submodules (i.e. simply calling NGCBUILD on an NGC to produce another NGC). This happens for example when it compiles IP blocks instantiated in an MHS file for example. It is then the case that NGCBUILD is run on the top-level to create one complete NGC for the entire design which is then feed directly in to NGDBUILD (i.e. one NGC file is fed into this program to produce one NGD). Does this sound about right? What I don't understand is why NGCBUILD is necessary. Is it not sufficient of take all of the individual NGC files (corresponding to all the modules individually synthesised in the design) and then let NGDBUILD pull them in as necessary (when given the top level NGC as a parameter)? I tried doing this before but it appears that NGDBUILD performs some optimisation before the linking stage and optimises/trims a lot of signals out of the design before it has the chance to link them together. This causes the linking to be performed incorrectly and causes DRC errors during BITGEN (because a lot of signals are no longer connected properly). Thanks for the clarifications, SteveArticle: 138813
Dear PR users, Our tool ReCoBus-Builder allows easily creating runtime reconfigurable systems based on Xilinx FPGAs. The tool can generate a highly optimized bus-based backplane communication infrastructure that may be adapted for implementing many established protocols including Wishbone, PLB, or Avalon. In addition, special streaming links can be provided for connecting I/O or dedicated modules. The GUI assists in floorplanning and generating all required constraints and code templates. More details, the ReCoBus-Builder, and lots of documentation are on the project website: www.recobus.de (in English language) Best regards DirkArticle: 138814
On Mar 11, 12:15=A0pm, VAX9...@gmail.com wrote: > Hi, > =A0 I wanted to preload my counter with a number, so I used the > asynchronous set and reset signal. In the following code the CS and WR > are asynchronous and much longer than CLK. > EN will be '1' sometime after the preloading is done. > > process ( the list ...) > begin > =A0 if CS=3D'1' and WR=3D'1' then > =A0 =A0 counter <=3D DATA; > =A0 else if CLK'event and CLK=3D'1' then > =A0 =A0 if EN=3D'1' then > =A0 =A0 =A0 counter <=3D counter + '1'; > =A0 =A0 end if; > =A0 end if; > end process > > This code worked (on Altera MAX II), but now I suspect that there is > better way. Do I better change to synchronous preloading? I am > thinking of something like this, > > if CLK'event and CLK=3D'1' then > =A0 if CS=3D'1' and WR=3D'1' then > =A0 =A0 counter <=3D DATA; > =A0 else if EN=3D'1' then > =A0 =A0 counter <=3D counter + '1'; > =A0 end if > end if > > Since CS and WR are much longer than the CLK period, and will be > sync'ed first, I guess this code would work too. Is this a better way > to do? Please let me know. Thank you! > > vax9000 The second construct (the synchronous load) is perfectly fine and I use it all the time. -aArticle: 138815
Antti wrote: > if i think of it, it should be doable? > > but i do not recall any projects that would use such transmit method > > normal FPGA LVDS are fast enough that it would be possible just > capacitive decoupling > sure some encoding should be applied but that shouldnt also be a > problem > > Antti Yes it is possible, no, it is not a good idea. Running cables through the world always get you transients. It is much better to put a hardened lvds driver onto external cables since they are easier to replace than fpgas. We have done this both ways.Article: 138816
On 11 Mar, 18:27, Niklas Holsti <niklas.hol...@tidorum.invalid> wrote: > Antti.Luk...@googlemail.com wrote: > > On Mar 11, 8:01 pm, Jacko <jackokr...@gmail.com> wrote: > > >>Hi > > >>>PS i have hard times understanding your nibz thing, sorry.. > >>>maybe my brain is not screwed enough to understand it ;) > > I too found the description hard to understand, which is a pity > because there may be some interesting ideas hiding there. ok. > >>A minimal microprocessor for tight logic area constraints. A minimal > >>microprocessor for such large component technologies like optical/ > >>photonic computing. A minimal microprocessor for developing 1000+ core > >>SoC designs. A minimal microprocessor for super low power > >>applications/ A minimal microprocessor for designing/executing highly > >>portable and simple to bootstrap implement languages. In general then > >>a minimal microprocessor. > > Yes, yes, it is clear that these are the goals. But what is the > processor architecture? The description of the registers and > instructions is very hard to understand. For example, you say that > there is an instruction called "BA" and describe its "Details" as > "BA (R)->P - Back". That is far from clear. BA instruction is indirect memory via R register and place contents into P register, i.e. pop return stack into program counter. (with auto post increment as all indirect memory reads do on this processor). The brackets are indirect memory access, the -> is register transfer. > You seem to be using some kind of personal abbreviated notation and > terminology, perhaps based on Forth (in which I am not fluent). If > you want to attract users to this processor, make an effort to > describe its architecture in common prose, and include some > examples with explanations. I'll think about it, and maybe add it to wiki. Cheers jackoArticle: 138817
Hi > so how much stack you get into the maxII- 570? None. indirect memory access is used. Cheers jackoArticle: 138818
"doug" <xx@xx.com> wrote in message news:uL2dnXB7JbmqoiXUnZ2dnUVZ_qjinZ2d@posted.docknet... > > > Antti wrote: > >> if i think of it, it should be doable? >> >> but i do not recall any projects that would use such transmit method >> >> normal FPGA LVDS are fast enough that it would be possible just >> capacitive decoupling >> sure some encoding should be applied but that shouldnt also be a >> problem >> >> Antti > > Yes it is possible, no, it is not a good idea. Running cables > through the world always get you transients. It is much better > to put a hardened lvds driver onto external cables since they > are easier to replace than fpgas. We have done this both > ways. Doug, I strongly disagree. A few reversed biased PIN diodes, some TVS diodes, and judicious routing beats 'hardened lvds drivers' every time. On cost, reliability, performance, manufacturability and board space. I would like to take this opportunity revise my original post, and recommend 8B10B coding to get rid of DC bias problem. 8B10B is out of patent now... HTH., Syms.Article: 138819
On Mar 11, 1:49=A0pm, Andy Peters <goo...@latke.net> wrote: > On Mar 10, 9:52=A0pm, newman5...@yahoo.com wrote: > > > > > > > On Mar 10, 7:48=A0am, "jag9624" <ma...@grahsl.net> wrote: > > > > Hello Everybody ! > > > > I am trying to build a SN75LVDS84 LVDS 21bit 3 channel LVDS Transmitt= er > > > with a Virtex 4 FX12. > > > > What troubles me is the movement of data words from the slow system c= lock > > > to the faster serializer clock (fast clock is multiples of slow clock= ). > > > Since the clocks are phase aligned by the dcm, i don't see nescessity= for > > > using an async fifo, but i fail to find a simpler solution. > > > > Currently i have three clocks: 100mhz(system clock), 20mhz(marking lv= ds > > > word periods) and 140mhz(DDR serializer). > > > Is there any possibility for each clock domain to mark the clock cycl= e > > > which is aligned with all other clocks ? If all clock domains were > > > conscious about their aligment with the other clocks, data transfers = could > > > be arranged in w way that avoids metastabilities. > > > > My idea of aligning a fast clock to a slow clock (namely 140mhz to 20= mhz > > > =3D> 7 bit cells): > > > > State machine running in fast clock: > > > > =A0state_wait_sync_0 (reset_state): > > > =A0 when slow clock is low go to state_wait_sync_1 > > > > =A0state_wait_sync_1: > > > =A0 when slow clock is high go to bitcell_1 > > > > =A0bitcell_1 > > > =A0 goto bitcell_2 > > > .. > > > =A0bitcell_5 > > > =A0 enable_load_data_from_slow_clock > > > =A0 goto bitcell_6 > > > > =A0bitcell_6: > > > =A0 goto bitcell_0 > > > > =A0bitcell_0 > > > =A0 goto bitcell_1 > > > > enable_load_data_from_slow_clock enables a flipflop to register data = from > > > slow clock at bitcell_5 to grant the signal from slowclock FF enough = setup > > > time to fastclock FF. > > > > As simple as that, BUT, i am sampling a clock in transition with a ph= ase > > > aligned clock (at wait_sync_*). This obviously does not work. So how = can > > > this be done ? I am curious, there must me a standard method... > > > > Thanks and best regards, > > > Julian Grahsl. > > > You might want to check out XAPP855 16-Channel, DDR LVDS Interface > > with Per-Channel Alignment. =A0It is for a Virtex-5 but many of the > > components sited are in the Virtex 4. =A0(oserdes, oddr, FIFO16 etc.) > > 8:1 serializing is pretty easy. 7:1? Not so much. > > -a- Hide quoted text - > > - Show quoted text - The original post mentioned 7 bits every 20 MHz at 140 MHz so it sounded like SDR. A subsequent post said DDR for an effective rate of 280 MBS so it's not clear to me what's going on. I remembered that the app note mentioned something about a recommended clocking scheme for V5. It did not mention V4 but I thought it may be a descent appnote reference. Right, 7:1 is a little different. It looks like the oserdes can handle 7 bits SDR. Perhaps SDR at twice the clock mentioned with the clock output at 140 MHz is worth thinking about. It looked like the oserdes can handle high speeds pretty well. Would need to remember to handle the output timing between the clock and data.Article: 138820
On Mar 11, 9:30=A0pm, bish <bishes...@gmail.com> wrote: > On 5 Mar, 19:58, goo...@twinmail.de wrote: > > > On 5 Mrz., 14:10, deep <infoparaj...@gmail.com> wrote: > > > > hi everyone, > > > tool : xilinx spartan 3a dsp > > > system overview : image taken form digital camera (c3038) connected t= o > > > fpga needs to be stored in simple dual port BRAM (written in one port > > > and read from other)and displayed onvgamonitor. > > In default, image size would be 352 X 288 16-bit for ov6630 used by > c3038. And I think its 8.9285 MHz in default mode. > > If you use only 8-bit Y data, that would require around 99KB of > memory. > Using external memory: display one complete stored frame while another > frame gets stored and therefore requiring 2 times the 99KB of memory. > But from your post it seems you need to display without storing the > complete frame!!!, > Hmm, that seems to be a bit more difficult problem. > Just duplicating the each pixel three time to be display inVGAmay > look to be simple solution. > But then, there is a problem to map each line with corresponding line > onVGA. > 352 pixels of camera of each line cannot be mapped to multiple lines > ofVGA. > Any other people here confronted with the similar problem? > > > > > > problem statement : digital data given by camera (c3038) written on > > > RAM at 17Mhz,but forVGAmonitor display these data needs to be read > > > at 25Mhz, .i want to take the advantage of two independent clocks of > > > dual port bram,but the data should neither be overwritten nor be lost= . > > > any idea regarding the problems are appreciated. > > > hi, > > your read clock is about 3 times faster than necessary > > so there will be gaps during the data transfer that can > > be used for synchronisation of input and output data. > > > Draw a time scheme of incoming data und outgoing data. > > Check how it can be matched without overlapping. > > > Use two memory banks for storing the incoming pics. > > (Thats just one more adress line that toggles on every new picture) > > > Hope that was helpful. > > Regards > > =A0 Eilert- Hide quoted text - > > - Show quoted text - You can display the zoomed version in VGA. For one pixel from camera display it in two consecutive pixels in VGA. Use two memory banks to store one complete line. Once one line is completely written, start reading out, and then continue reading with another bank, i.e the same line. This will effectively duplicate one line of pixels of camera into two lines of vga. I hope this will solve your problem, but just be careful about the clipping of the camera data after certain number of pixels in each line.Article: 138821
On Mar 11, 2:27 pm, Niklas Holsti <niklas.hol...@tidorum.invalid> wrote: > Antti.Luk...@googlemail.com wrote: > > On Mar 11, 8:01 pm, Jacko <jackokr...@gmail.com> wrote: > > >>Hi > > >>>PS i have hard times understanding your nibz thing, sorry.. > >>>maybe my brain is not screwed enough to understand it ;) > > I too found the description hard to understand, which is a pity > because there may be some interesting ideas hiding there. > > >>A minimal microprocessor for tight logic area constraints. A minimal > >>microprocessor for such large component technologies like optical/ > >>photonic computing. A minimal microprocessor for developing 1000+ core > >>SoC designs. A minimal microprocessor for super low power > >>applications/ A minimal microprocessor for designing/executing highly > >>portable and simple to bootstrap implement languages. In general then > >>a minimal microprocessor. > > Yes, yes, it is clear that these are the goals. But what is the > processor architecture? The description of the registers and > instructions is very hard to understand. For example, you say that > there is an instruction called "BA" and describe its "Details" as > "BA (R)->P - Back". That is far from clear. > > You seem to be using some kind of personal abbreviated notation and > terminology, perhaps based on Forth (in which I am not fluent). If > you want to attract users to this processor, make an effort to > describe its architecture in common prose, and include some > examples with explanations. > > -- > Niklas Holsti > Tidorum Ltd > niklas holsti tidorum fi > . @ . I've tried to understand what this processor is about and I have never been able to "get it". As you indicate, the notation is very cryptic as is a lot of what he says. I remember a qwerty who used to post in some of these groups who would make all sorts of claims, but never seemed to have anything to offer. jacko seems to be doing some interesting work, but it is mostly not intelligible to us mere mortals. jacko, please don't take me wrong. I don't mean to belittle you in any way. I'm just trying to make the point that if you don't communicate well, you have little impact on the rest of the world. If that is ok with you, it doesn't matter to me. I'm just making an observation. Enjoy, RickArticle: 138822
On Mar 11, 12:30=A0pm, bish <bishes...@gmail.com> wrote: > On 5 Mar, 19:58, goo...@twinmail.de wrote: > > > On 5 Mrz., 14:10, deep <infoparaj...@gmail.com> wrote: > > > > hi everyone, > > > tool : xilinx spartan 3a dsp > > > system overview : image taken form digital camera (c3038) connected t= o > > > fpga needs to be stored in simple dual port BRAM (written in one port > > > and read from other)and displayed on vga monitor. > > In default, image size would be 352 X 288 16-bit for ov6630 used by > c3038. And I think its 8.9285 MHz in default mode. > > If you use only 8-bit Y data, that would require around 99KB of > memory. > Using external memory: display one complete stored frame while another > frame gets stored and therefore requiring 2 times the 99KB of memory. > But from your post it seems you need to display without storing the > complete frame!!!, > Hmm, that seems to be a bit more difficult problem. > Just duplicating the each pixel three time to be display in VGA may > look to be simple solution. > But then, there is a problem to map each line with corresponding line > on VGA. > 352 pixels of camera of each line cannot be mapped to multiple lines > of VGA. > Any other people here confronted with the similar problem? > > > > problem statement : digital data given by camera (c3038) written on > > > RAM at 17Mhz,but for VGA monitor display these data needs to be read > > > at 25Mhz, .i want to take the advantage of two independent clocks of > > > dual port bram,but the data should neither be overwritten nor be lost= . > > > any idea regarding the problems are appreciated. > > > hi, > > your read clock is about 3 times faster than necessary > > so there will be gaps during the data transfer that can > > be used for synchronisation of input and output data. > > > Draw a time scheme of incoming data und outgoing data. > > Check how it can be matched without overlapping. > > > Use two memory banks for storing the incoming pics. > > (Thats just one more adress line that toggles on every new picture) > > > Hope that was helpful. > > Regards > > =A0 Eilert The spec is not very clear to me. The data needs to be read out at 25 MHz, but is that continuous or read at the times the data should be sent to the interface with gaps for the horizontal and vertical blanking intervals? Considering the data rates specified, I would speculate that the camera data is being clocked out continuously with no gaps or maybe just a short gap between frames. I also appears that the 25 MHz rate is a gapped rate with pauses in the data. I'm not sure why Eilert thinks the read clock is 3 times faster than necessary. VGA resolution is 640 x 480 =3D 307,200 * 60 Hz =3D 18.432 MHz. I'm not sure how the camera gets its data out at 17 MHz, but maybe it is refreshing at 50 Hz or even 30 Hz. There's just not enough info to know how to solve the problem. If it can be assured that the read out is allways faster than the write, you can get by with two buffers. If the readout is gapped so that a write could catch up with the read, three are needed. RickArticle: 138823
Hi, I am trying to read a byte from a particular address in I2C EEPROM. But the data I get is from a different location. For example, if try to read data from "x05" location, the byte from "x0B" location is read. If try to read data from "x06" location, data from "x0D" is read. If I try to read data from "x07", data from "x0F" is read. If you notice above situation, a fixed pattern is followed. I am using a I2C Master Core controller to read data from I2C EEPROM. Xilinx Post route simulation works fine but when I try to configure the Spartan 3E FPGA, I get the above described results. I2C EEPROM is external to the FPGA and I2C controller goes in to the FPGA. I am confused as to why is this happening. Can any one please help. Thanks.Article: 138824
On Mar 11, 10:32=A0pm, Dirk Koch <dirk.k...@cs.fau.de> wrote: > Dear PR users, > > Our tool ReCoBus-Builder allows easily creating runtime reconfigurable > systems based on Xilinx FPGAs. The tool can generate a highly optimized > bus-based backplane communication infrastructure that may be adapted for > implementing many established protocols including Wishbone, PLB, or > Avalon. In addition, special streaming links can be provided for > connecting I/O or dedicated modules. > > The GUI assists in floorplanning and generating all required constraints > and code templates. > > More details, the ReCoBus-Builder, and lots of documentation are on the > project website: > > www.recobus.de(in English language) > > Best regards > Dirk too bad no S3A are supported :( Antti
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