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On Thu, 05 Mar 2009 19:35:57 -0800, Alex Freed wrote:
>My point is that even this optimized VHDL is 13 lines vs. my 3 lines.
>More than a factor of 4. Does it buy any clarity? I'm not arguing. Just
>trying to understand what is it that atracts people to VHDL if they have
>a choice and start from scratch.
Fair question.
This is the standard, and completely irrelevant, canard that
Verilog bigots use to argue that VHDL is excessively verbose.
It is definitely true that you can write trivial examples
in many fewer lines of Verilog than VHDL. Once you start
doing complicated stuff, however, the VHDL bureacratic
overhead (which does not much increase as the design grows)
rapidly disappears into the noise. And if you use VHDL
correctly, the reuse you can get from packages and, most
particularly, from functions with unconstrained array
arguments, can often make VHDL designs MORE compact,
and definitely more maintainable, than equivalent Verilog.
Verilog also has its own share of bureaucratic noise:
Verilog, 10 lines:
if (condition)
begin
statement1;
statement2;
end
else
begin
statement3;
statement4;
end
VHDL, 7 lines:
if condition = '1' then
statement1;
statement2;
else
statement3;
statement4;
end if;
VHDL and Verilog each have their advantages and
drawbacks. I remain convinced that, even with the
advent of SystemVerilog and its numerous handy
features, VHDL remains a superior language for
RTL design; by contrast, VHDL is weaker for verification
because of its lack of cross-module reference and its
clumsy file I/O and string handling. Verilog's string
handling sucks very hard indeed, but SystemVerilog
completely fixes that.
As general-purpose programming languages, both have
serious deficiencies; but you wouldn't use either
as a general-purpose language, presumably.
Strictly personal opinions, of course :-)
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 138726On Mar 5, 6:42=A0pm, justforpret...@gmail.com wrote: > I hope this isn't terribly inappropriate to post here. =A0I want to buy > three FPGA-related T-shirts. =A0I know that Altera and Xilinx have in > the past given out freebie shirts, and I'm trying to track some down > as gifts for my roommates, who work with FPGAs. =A0I will pay good money > for them!! > > Let me know if you have something lying around that you don't mind > parting with. =A0They primarily use Altera, so that's preferable. > > Thanks! Altera do good mugs, I've got one from a tech seminar thing I went to (as a work thing, I'm not a student any more). I'm not going to sell it to you though :)Article: 138727
Vesh wrote: > I was able to generate a character ROM using the Xilinx 10.1 ISE Core > generator and also a RAM using the same. This is only a part of my > final year project, not the project as a whole. But during > implemetation the following error occurred. > > ERROR:NgdBuild:604 - logical block 'U_TEXT' with type 'mem_text' could > not be > resolved. A pin name misspelling can cause this, a missing edif or > ngc file, > or the misspelling of a type name. Symbol 'mem_text' is not > supported in > target 'spartan3e'. > ERROR:NgdBuild:604 - logical block 'U_FONT' with type 'mem_font' could > not be > resolved. A pin name misspelling can cause this, a missing edif or > ngc file, > or the misspelling of a type name. Symbol 'mem_font' is not > supported in > target 'spartan3e'. > > the 'mem_text' is the generated RAM module and 'mem_font' is the > generated character ROM. U_TEXT and U_FONT are their instants in the > highest level module. > > does anyone have a solution. I consulted the Xilinx website for these > errors but of no use. > If U_text and U_font are instances of the generated ram, you need to make sure that the generated ngc files are found by the place and route tools. If you ran coregen standalone, then you need to copy the ngc files into your Xilinx project. If you ran coregen from within ISE it "should have just worked" :-) Alan P.S. The netlist format might be edf rather than ngc, depending on the options you selected in CoreGen. -- Alan Fitch Doulos http://www.doulos.comArticle: 138728
Ehsan, Sorry for the delay... A few more questions: 1. Could you send the snippet of code for the counter (Iter_No I presume)? 2. Could you confirm that the FSM is coded with 2 process: one combinational process for next_state logic, and one synchronous process to register next_state in to state_reg? If that's the case, then I would highly recommend checking the completeness of sensitivity list for the combinational process. This is a typical place where synthesis and simulation can mismatch. Indeed, synthesis tools tend to ignore incomplete sensitivity list if the intent can be full extracted from the process itself. Simulation, however, is very picky and will not update the value of signals missing from the sensitivity list. Finally, for readability, I prefer coding FSM with 3 processes, where one process is dedicated to generating outputs. Is there an option in StateCad for that coding style? - gaelArticle: 138729
cs_posting@hotmail.com writes: > Not so fast. Listing 3.3v I/O and having it usable in the real world > are not the same thing. You need to check how much allowance there is > for overshoot, which will determine how perfect your impedance match > needs to be to be able to use 3.3v I/O in the real world. Well that's true, but at least the possibility of engineering it right exists :) Cheers, Martin, -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 138730
Hi, I have 2 modules ( 1 UART and another module used to test external SRAMs ). Every single module is working prefectly when alone on the Spartan 3 borad. when i put them together, the UART doesn't work anymore. i have the clock excessive skew problem, and i'm pretty sure it comes from there. The RX module is working perfectly while the TX module is not working. the UART provides in its output a 274 bit signal that serves as an input to the second module. i'm using the same clock for both modules. and that's the only/ common interaction signals i am using. When i don't use the shift register as an input for the second module, and i just use zeros instead, the Tx works !! so i thought it comes from placement/ routing ... Any idea, suggestion will be much appreciated. Best regards, Hassen.Article: 138731
Glen Herrmannsfeldt <gah@ugcs.caltech.edu> writes: > Also, I wasn't sure that the MIG output could be used in > open source projects. > Probably not, but... Given that it's tied to Xilinx, then any end-users will have to have the Xilinx tools. I imagine (but IANAL :) that the XCO file that coregen uses to create the MIG files could be treated as the "source file". This is *probably* something you could distribute. And then the end users can make their own MIG which is the same as "yours" (ie the one you developed with)? Failing that a screenshot walkthrough on clicking their way to "your MIG" :( Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 138732
On Mar 6, 5:53=A0am, hassen.kar...@gmail.com wrote: > Hi, > > when i put them together, the UART doesn't work anymore. i have the > clock excessive skew problem, and i'm pretty sure it comes from there. Not sure what the "clock excessive skew problem" is, but it certainly doesn't sound right...fix it. > > Any idea, suggestion will be much appreciated. > 1. Simulation. Create a testbench, exercise the design and make sure that it is doing exactly what you expect under as many conditions as you can come up with that model how you intend to use the design. 2. Static timing analysis. Make sure the analysis is checking clock domain transfers, specify the setup time, hold time that the PCBA can deliver for all inputs, specify the clock to output and propagation delay that the PCBA requires for all outputs. Verify that the timing analysis reports shows that all timing requirements have been met. 3. Verify pinouts match what the PCBA is expecting. 4. Do not waste your time using the actual Spartan 3 board until steps 1,2 and 3 have been completed successfully. Kevin JenningsArticle: 138733
On Mar 5, 6:01=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > Ise 9.2i will not accept a .ngc file as a source file via the gui, > but it does seem to find and use it if I just copy it > into the project directory with where the .v and .vhd files end up. > > If anyone has a cleaner method, without regenerating the core, > I would like to hear about it. > Thanks. > > =A0 =A0 =A0 -- Mike Treseler If you use Verilog, make a module core_name.v with just the port definitions and no behavioral / structural stuff. Then add the verilog module to your project and ISE will use the .ngc file with the same name. For VHDL you need a black box to do the same thing.Article: 138734
Jan Pech wrote:
> Of course, ISE accepts NGC files as sources but you have to set the
> "Top-Level Source Type" to NGC/NGO instead of HDL.
Thanks.
How can I change the type before I add it?
-- Mike Treseler
Article: 138735Muzaffer Kal wrote: > Add the associated .xco file to your project. Thanks. ISE will accept that, but not the .ngc -- Mike TreselerArticle: 138736
gabor wrote:
> On Mar 5, 6:01 pm, Mike Treseler <mtrese...@gmail.com> wrote:
>> Ise 9.2i will not accept a .ngc file as a source file via the gui,
>> but it does seem to find and use it if I just copy it
>> into the project directory with where the .v and .vhd files end up.
>>
>> If anyone has a cleaner method, without regenerating the core,
>> I would like to hear about it.
>> Thanks.
>>
>> -- Mike Treseler
>
> If you use Verilog, make a module core_name.v with just the
> port definitions and no behavioral / structural stuff. Then
> add the verilog module to your project and ISE will use the
> .ngc file with the same name. For VHDL you need a black box
> to do the same thing.
That makes sense.
Thanks.
-- Mike
Article: 138737
Alex Freed wrote:
> I wonder what drives you towards VHDL
I use both. Each is uniquely annoying.
> assign O = (e == 1) ? I : 4'bz;
I must admit that I had back up the thread
to figure that one out.
-- Mike Treseler
Article: 138738On Mar 3, 10:22=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > Craignell2 and Mulldonnoch2 now listed ubder our board products page > (engineering website www dot enterpoint dot co dot uk). > > John Adair > Enterpoint Ltd. And so what? What does your post tell to C.A.F. about your engineering site? AnttiArticle: 138739
On Fri, 06 Mar 2009 07:33:23 -0800, Mike Treseler <mtreseler@gmail.com> wrote: >Muzaffer Kal wrote: > > >> Add the associated .xco file to your project. > >Thanks. >ISE will accept that, but not the .ngc The xco file serves a purpose similar to the empty verilog definition mentioned in an earlier post. You need something which shows the io definition which makes synthesis happy and a black box embedded in your top level design then during translate/map time the ngc (which has the same name as the empty verilog or the xco file) is linked into your design. I think xco is more convenient as it comes directly from coregen and you don't have to do the empty verilog/vhdl block yourself. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 138740
Dear Huang, We have implemented an easy usable tool that supports 2D reconfiguration based on our ReCoBus communication architecture. In an example system on a Virtex-II-6000-6, we can provide 248 logic tiles (62 x 4) and 16 RAM tiles (4 x 4). Each of the 248 logic tiles have access to a slave bus and modules can connect with up to 48 bit wide data busses. In addition, we can provide connections to a 24 bit RGB video stream that can be accessed in all tiles. Despite its large size, the system runs at 100 MHz and the complete communication architecture requires just 2700 Slices. We do a lot of things different as compared to the "normal Xilinx PR flow" and we are not depending on extra patches. Our project website is: www.recobus.de (in English language) There you get the tool, our papers, and lots of documentation (more than 100 pages for a userguide and tutorials). Happy reconfiguring! DirkArticle: 138741
On Fri, 06 Mar 2009 10:10:39 -0800, Mike Treseler wrote: >> assign O = (e == 1) ? I : 4'bz; > >I must admit that I had back up the thread >to figure that one out. Ah, phooey - he's not even trying. Let's skinny the code a bit more: assign O=e?I:'bz; Those useless spaces never did anyone any good, after all. Verilog is happy to trim off the 28 surplus bits in 'bz (you could even do simply 'z in SystemVerilog) and it's completely pointless to write (e==1) for a single-bit 'e'. Remember, folks: Every keystroke may harbour a bug, so it's obvious that fewer keystrokes mean fewer bugs. Verilog good, VHDL bad. C good, Ada bad. Comments unnecessary, therefore comments bad. Long variable names bad. There used to be obfuscated-C and obfuscated-Perl contests; for all I know, there still are. The sad thing is that there's no need for obfuscated Verilog contests, because people do it all the time anyway. You read it here first :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 138742
Muzaffer Kal <kal@dspia.com> writes: > What would be the fastest way to do a > 32x32 multiplier in Virtex-5? Using four of the 18x18 multipliers out of the DSP48 blocks.Article: 138743
I've got a static library that I'd like to compile from source as part of my project compilation. I was hoping it would be possible to run the custom makefile in the compilation sequence to create mylib.a, much like it does for libdriver.a and libxilkernel.a. However, I wasn't able to find any options in libgen that would allow me to add this. I already have a makefile and all the source, I just need to 'make' it. I'm using Xilinx Webpack and EDK 10.1.03 and a microblaze processor. TIA, AndrewArticle: 138744
On 2=D4=C225=C8=D5, =C9=CF=CE=E75=CA=B111=B7=D6, Luc <l...@logitronica.be> = wrote: > Hello, > > I need to design a system that uses IEEE1588 PTP to synchronize clock > within a couple of 100's of nanosecs. > > Anyone has some experience with it and can share some thoughts? > > Oh, by the way, the FPGA should be an Altera with Nios on board. > > Regards, > Luc The IEEE1588 is not so difficult to implement. You can find a lot of articles on the web,and they are very useful to help you understand the protcol^Article: 138745
On Mar 7, 1:27=A0am, "Andrew W. Hill" <aquaregi...@gmail.com> wrote: > I've got a static library that I'd like to compile from source as part > of my project compilation. =A0I was hoping it would be possible to run > the custom makefile in the compilation sequence to create mylib.a, > much like it does for libdriver.a and libxilkernel.a. =A0However, I > wasn't able to find any options in libgen that would allow me to add > this. =A0I already have a makefile and all the source, I just need to > 'make' it. > > I'm using Xilinx Webpack and EDK 10.1.03 and a microblaze processor. > > TIA, > Andrew It is easy to make own EDK libraries,please look as example http://code.google.com/p/dev-kit/downloads/list there C code from DOSFS is converted to EDK library AnttiArticle: 138746
Hi just uploaded the special EW2009 issue http://groups.google.com/group/antti-brain/files?hl=en it is not the regular issue, so there is very little technical articles or text content, mostly some pictures and very short commentary, but i hope it is little different than the EW coverage in magazines that accept commercial ads. regular issue will be available at end of march. AnttiArticle: 138747
For those that didn't get the marketing email from Doulos, have a look at these videos (they are actually quite good IMHO) http://www.doulos.com/knowhow/video_gallery/ Hans www.ht-lab.comArticle: 138748
On Mon, 02 Mar 2009 22:33:56 -0700, Glen Herrmannsfeldt <gah@ugcs.caltech.edu> wrote: |Vesh wrote: | |> Thanks for ur link. No Mark..its just a part of our project named |> "Wireless Device Manager Using FPGA". Its not that i wasnt bothered to |> search them myself. I have, but most of them are incomplete especially |> without the .vhd file for character rom. I have already used VGA |> graphics controller..n i m just starting this text display. I was |> looking for faster approach. | |I believe the SOL documentation has images of the generated |characters from its generator. | |Otherwise, graph paper in a pen will do it. | |-- glen |------------- If one does not have graphpaper xcell spreadsheet will do about the same. But then that maybe taxing some people's ability also. jamesArticle: 138749
How about Xilinx T-shirt? I have some Xilinx version T-shirt. :) -- fasteq ------------------------------------------------------------------------ fasteq's Profile: http://www.fpgacentral.com/group/member.php?userid=27 View this thread: http://www.fpgacentral.com/group/showthread.php?t=88361
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