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Sylvain Munaut <SomeOne@SomeDomain.com> wrote: > On Feb 27, 9:15 pm, n...@puntnl.niks (Nico Coesel) wrote: >> "Sylvain Munaut <Some...@SomeDomain.com>" <246...@gmail.com> wrote: >> >> >> >>> I'm not that interested in HLL because when I uses theses. But a macro >>> preprocessor would be nice :) >> You can use plain old cpp for that purpose. A few months ago I wrote a >> PLC compiler thingy. I used cpp as a preprocessor for it. > > Mmm, I hadn't tought of that. > That's a nice easy way to get a well known syntax. > > However for an assembler it's nice to have more 'advanced' things. I'm > not an expert in the C preprocessor but making a macro that would > expand : > > STACK_PUSH(s0, s1, s2, s3) > > into > > store s0, (sp)0 > store s1, (sp)1 > store s2, (sp)2 > store s3, (sp)3 > add sp, 4 > > Seems kinda hard ... You mean something like this - #define STACK_PUSH(a,b,c,d) store a, (sp)0 store b, (sp)1 store c, (sp)2 store d, (sp)3 add sp, 4 STACK_PUSH(s0, s1, s2, s3) MarkArticle: 129601
On Feb 28, 10:57=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > On Feb 28, 8:53=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > > > On Feb 28, 5:19=A0am, Tricky <Trickyh...@gmail.com> wrote: > > > > On Feb 28, 4:50 am, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > On Feb 27, 11:38 pm, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > > > I have written a process to generate sin wave as below. > > > > > > -- sine wave constants > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0amp_sin : r= eal :=3D 10.0; > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0phase_sin := real :=3D 0.0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- > > > > > phase in radians > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0samples_sin= : integer :=3D > > > > > 1000; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- number of > > > > > samples > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0incr_sin : = real :=3D 0.001; =A0 =A0 =A0 =A0 =A0 =A0 =A0-- 1/ > > > > > samples > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0period_sin = : time :=3D 0.001 > > > > > ns; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- period of > > > > > sine wave/samples > > > > > > two : process > > > > > variable phase_temp,result : real ; > > > > > begin > > > > > =A0 =A0 =A0 =A0 phase_temp :=3D phase_sin; --phase_sin; > > > > > =A0 =A0 =A0 =A0 l1 : for i in 1 to samples_sin loop --number_of_sa= mples loop > > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 sine_real <=3D ((amp_sin*sin(phase= _temp))); > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phase_temp :=3D phase_temp + incr_= sin; > > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait for period_sin; > > > > > =A0 =A0 =A0 =A0 end loop l1; > > > > > end process two; > > > > > > The problem I am facing is, I get sine wave for some values and fo= r > > > > > some I just get triangulr wave. Is there any limitation to the sin= > > > > > function in math_real. Should I be able to generate any type of > > > > > frequencies with this function. Please help > > > > > Also, the sine wave does not stop after it takes all the samles, I > > > > keep getting a continous sine wave. Would like to add the option of > > > > generating wave from 0 tp 2pi or 4 pi, etc. I want to make this as > > > > generic as possible > > > > It's repeating because you havent told the process to wait when it > > > finishes the loop. Currently the loop finishs, and then the process > > > restarts and does the whole loop again, and this will repeat for ever.= > > > To stop this simply put "wait;" at the end of the process.- Hide quote= d text - > > > > - Show quoted text - > > > I am required to design this using the CORDIC algorithm.- Hide quoted te= xt - > > > - Show quoted text - > > I was able to add the wait statement and the problem was solved. I > modified some of the things and not I am able to get waveforms at > different frequencies. FYI, > incr_phase_sin : real :=3D (2.0*MATH_PI)/(real(samples_sin)); =A0 =A0 =A0 = -- 2pi/ > samples per period > incr_time_sin : time :=3D time(period_sin/samples_sin); =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 -- > period/samples per period- Hide quoted text - > > - Show quoted text - The sine wave function in math_real uses the CORDIC algorithmArticle: 129602
Thanks for the reassuring information, Austin! /Mikhail "austin" <austin@xilinx.com> wrote in message news:47C6DBAE.7040206@xilinx.com... > Mikhail, > > If this is done once: absolutely no problem. > > Even if done a 100 times: no problem. > > The concern is that you accumulate more than a few hundred hours at > elevated temperature in a static (non-switching) condition. > > And, as I said before, we were unable to actually see anything happen to > the DCM. > > MGTs are also affected by NBTI powered on but left unconfigured (on the > V4 FX), and there, you will see variations after hundreds of hours of > static "stress." But, again, it doesn't seem possible to accumulate > such a stress, even for a MGT in your case. > > > Austin >Article: 129603
These approaches seem to work. Thanks.Article: 129604
Xesium wrote: > Hi Ed, > >Thanks. Actually the problem was solved. But the problem was something >else. Previously I used to export my design to ISE and synthesize and >place and route it there and then generate the ace file through >iMPACT. However this time (that worked) I actually did everything >through EDK and used shell commands to generate the ace file. So >basically the design through ISE has some problems some where and I >have not realized where exactly. This indicates that the JTAG chain was not defined correctly in ISE, but EDK understood which board you were using and defined the chain correctly. >I realized that the mode pins >(M2M1M0) are set as 101 (boundary-scan) in EDK but the same in ISE >were set as 111 (slave serial). I'm not sure but I think 101 is the >desired configuration because sysAce is going to reconfigure from >compact flash. Mode pins are physical items and are set on the board. There is no software that can set these for you. >So there is no external clock to the FPGA configuration >unless I'm wrong. (Will you please clarify this issue?) System ACE requires a clock to operate and generates a JTAG TCK clock to the FPGA chain. Slave Serial mode requires an external clock to be provided that is aligned with the serial data stream. >Also the problem with EDK9.2i >is that it doesn't support ML310 board that I'm currently working on, >so that's the reason that I couldn't use it. But I'm considering >moving to ISE 9.1 at least. I do not know why support the ML310 was removed in the latest version of the EDK Base System Builder. EDK can still be used to generate designs for the ML310, but just not through the BSB flow. EDK supports a "rev up" function that should be able to take your old 8.2i design and bring it forward to the 9.2i environment. Ed McGettigan -- Xilinx Inc.Article: 129605
> You mean something like this - > > #define STACK_PUSH(a,b,c,d) > store a, (sp)0 > store b, (sp)1 > store c, (sp)2 > store d, (sp)3 > add sp, 4 > > STACK_PUSH(s0, s1, s2, s3) :) I meant with a variable number of argument, autoadapting itself. SylvainArticle: 129606
> You shouldn't push the limits too far... Your example smells more like > assembler extensions than macro's. Yes ... I seem to recall the Microchip PIC assembler supported things like that ... SylvainArticle: 129607
I got Xilinx free IDE running and even got some simple designs through. But there wasn't any Xilinx programmer/evaluation kit available from Farnell or Elfa. What is the problem. From where I could buy working pair. Xilinx sw seems to work, but any other good free program and low cost demo kit is ok. Regards LMArticle: 129608
The xilinx website has links to several places where you can buy eval boards. You can also buy the boards themselves seperately from digilent. Sparkfun electronic has a spartan 3e fpga board as well. There are numerous places to get boards it just depends what you want on the board. What is your end product? You goal will determine the size of the FPGa and what features the eval/development boards need to have. "LM" <sala.nimi@mail.com> wrote in message news:e0d8af5c-ac23-4305-b709-b40815af75d9@s8g2000prg.googlegroups.com... >I got Xilinx free IDE running and even got some simple designs > through. But there wasn't any Xilinx programmer/evaluation kit > available from Farnell or Elfa. What is the problem. > > From where I could buy working pair. Xilinx sw seems to work, but any > other good free program and low cost demo kit is ok. > > Regards > LMArticle: 129609
On 29 helmi, 00:04, LM <sala.n...@mail.com> wrote: > I got Xilinx free IDE running and even got some simple designs > through. But there wasn't any Xilinx programmer/evaluation kit > available from Farnell or Elfa. What is the problem. > > From where I could buy working pair. Xilinx sw seems to work, but any > other good free program and low cost demo kit is ok. > > Regards > LM Well. I found a link to demo boards in Xilinx wep page. Tomorrow I'll take closer look. If you have some info or ideas about good boards and sw, I'm still happy to see them.Article: 129610
Vagant <vladimir.v.korostelev@rambler.ru> wrote: >Although I am a newbie in FPGA design and have experience only with >some simple designs so far, I am thinking of some more ambitious >project and want to design a FPGA-based PC scope working in Windows >XP. >Let's assume that I know how to program (in VHDL) and implement this >on FPGA. Then I will need to write software for this and I need advice >about it. What software such project will require and what development >tools I will need to write such software? May I write this in C++ >Builder or Visual Basic or I will need some lower level programming? >So, my question is very general and I would appreciate your advice >which I need to start up with this since on my own I just feel stuck >about software for my project. Use bsd/linux, or something with less bloat when dealing with tight latency. C/C++ language is the choice (of weapon). Basic is not an appropriate language.Article: 129611
Tom wrote: > In a situation where it is necessary to cross between two clock > TLDR > > Many thanks > > Tom Hi Tom, From the archive, Rick Collins once said ---> Anyone had big problems with similar async circuits? BTW, here is the simple sync circuit to generate a single pulse in the target clock domain regardless of the relative speed of the clocks. |------- Metastable -------| __________ | | _____ |------O| inverter |-------|---------------| | Pulse | |__________| | | XOR |----> | ______ ______ | ______ |--|_____| Out | | | | | | | | | |---| D Q |-----| D Q |--|--| D Q |--| Strobe | | | | | | /Clock | | | | | | -------|> | ---|> | |---|> | |______| | |______| | |______| | | |___________|___________ Output Clock The pulse out should be clean by the next clock edge as long as the routing is kept short. Or if the clock period is very short another FF can be added to feed the other leg of the XOR gate and assure a clean output. HTH, Syms.Article: 129612
On Wed, 27 Feb 2008 12:42:12 -0800 (PST), "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote: > making a macro that would expand : > >STACK_PUSH(s0, s1, s2, s3) > >into > >store s0, (sp)0 >store s1, (sp)1 >store s2, (sp)2 >store s3, (sp)3 >add sp, 4 > >Seems kinda hard ... I don't know the picoblaze procedure/interrupt conventions, but getting an interrupt between store s1 & store s2 or so looks like trouble. regards, GerhardArticle: 129613
On Feb 29, 10:00=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > > =A0 =A0|------- Metastable -------| > =A0 =A0 =A0 =A0 =A0 =A0 __________ > =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0_____ > =A0 =A0|------O| inverter |-------|---------------| =A0 =A0 | Pulse > =A0 =A0| =A0 =A0 =A0 |__________| =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 =A0 = =A0 | XOR |----> > =A0 =A0| =A0 =A0______ =A0 =A0 =A0 ______ =A0 | =A0 ______ =A0 |--|_____| = Out > =A0 =A0| =A0 | =A0 =A0 =A0| =A0 =A0 | =A0 =A0 =A0| =A0| =A0| =A0 =A0 =A0| = =A0| > =A0 =A0|---| D =A0Q |-----| D =A0Q |--|--| D =A0Q |--| > Strobe | =A0 =A0 =A0| =A0 =A0 | =A0 =A0 =A0| =A0 =A0 | =A0 =A0 =A0| > /Clock | =A0 =A0 =A0| =A0 =A0 | =A0 =A0 =A0| =A0 =A0 | =A0 =A0 =A0| > -------|> =A0 =A0 | =A0---|> =A0 =A0 | |---|> =A0 =A0 | > =A0 =A0 =A0 =A0|______| =A0| =A0|______| | =A0 |______| > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 | > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|___________|___________ =A0Output Cloc= k > > The pulse out should be clean by the next clock edge as long as the > routing is kept short. =A0Or if the clock period is very short another FF > can be added to feed the other leg of the XOR gate and assure a clean > output. Thanks for that Symon - checking the RTL schematic synthesized from my VHDL, the above seems to be what I've ended up with, albeit with extra registers on input and output, which are probably superfluous and just adding delay! Best, Tom.Article: 129614
>>...want to design a FPGA-based PC scope working in Windows XP. >Use bsd/linux... More on how to do this in the next exciting episode, I assume.Article: 129615
>>...want to design a FPGA-based PC scope >>...May I write this in C++ Builder or Visual Basic...? >C/C++ language is the choice (of weapon). Basic is not an appropriate language. I'd love to hear why "Basic is not an appropriate language".Article: 129616
Hi, We want to make Spartan3AN as One Time Programmable. We want to program it once and then disable JTAG. Is it possible to do that? How can we do that? -- GoliArticle: 129617
On 29 Feb., 04:52, Goli <tog...@gmail.com> wrote: > Hi, > > We want to make Spartan3AN as One Time Programmable. We want to > program it once and then disable JTAG. > Is it possible to do that? How can we do that? > > -- > Goli NOArticle: 129618
> >store s0, (sp)0 > >store s1, (sp)1 > >store s2, (sp)2 > >store s3, (sp)3 > >add sp, 4 > > >Seems kinda hard ... > > I don't know the picoblaze procedure/interrupt conventions, but getting > an interrupt between store s1 & store s2 or so looks like trouble. There is no convention ... you just fix what you want for yourself. But indeed, with a classic one, this would be a problem. Solution is to either - Don't use interrupts :) That actually my case for the sw where this snippet comes from - Make it a critical zone : cli store s0, (sp)0 store s1, (sp)1 store s2, (sp)2 store s3, (sp)3 add sp, 4 sti - Use dual pointer : add sp, 4 sub bp, sp, 4 store s0, (bp)0 store s1, (bp)1 store s2, (bp)2 store s3, (bp)3 - Have the interrupts with their own dedicated stack and a dedicated reg used only by them. So the interrupt handler would start by .equ si, s14 .bss __isr_stack: .space 32 .text __isr: load si, __isr_stack store sp, (si) load sp, si add sp, 1 store s0, sp(0) ... ... - Reserve the space 'before' : add sp, 4 store s0, sp(-4) store s1, sp(-3) store s2, sp(-2) store s3, sp(-1) Unfortunatly, I don't think my hw mod can extend to allow negative offset without adding some slices ... I'd have to recheck. SylvainArticle: 129619
On Feb 29, 4:52 am, Goli <tog...@gmail.com> wrote: > Hi, > > We want to make Spartan3AN as One Time Programmable. We want to > program it once and then disable JTAG. > Is it possible to do that? How can we do that? > > -- > Goli You cannot disable the JTAG ! and why do you want to remove the powerful JTAG link from your board application ? One Time Programmable = Not Upgradeable System ! Larry http://www.amontec.comArticle: 129620
Hello all, I am looking for a free DSP Ip core (like the OpenCores C54). Have you some idea to look for ? Best regards, JSLArticle: 129621
ofcourse u can. just ground them! j...@amontec.com schrieb: > On Feb 29, 4:52 am, Goli <tog...@gmail.com> wrote: > > Hi, > > > > We want to make Spartan3AN as One Time Programmable. We want to > > program it once and then disable JTAG. > > Is it possible to do that? How can we do that? > > > > -- > > Goli > > You cannot disable the JTAG ! > > and why do you want to remove the powerful JTAG link from your board > application ? > One Time Programmable = Not Upgradeable System ! > > Larry > http://www.amontec.comArticle: 129622
On 29 Feb., 09:59, waltherz <walther.za...@gmx.de> wrote: > ofcourse u can. just ground them! > > j...@amontec.com schrieb: > > > On Feb 29, 4:52 am, Goli <tog...@gmail.com> wrote: > > > Hi, > > > > We want to make Spartan3AN as One Time Programmable. We want to > > > program it once and then disable JTAG. > > > Is it possible to do that? How can we do that? > > > > -- > > > Goli > > > You cannot disable the JTAG ! > > > and why do you want to remove the powerful JTAG link from your board > > application ? > > One Time Programmable = Not Upgradeable System ! > > > Larry > > http://www.amontec.com that doesnt prevent the JTAG being used if the chip is desoldered... so it really isnt disabling the JTAG just making it harder to access lso when the S3AN are to be programmed before sending to assembly fab? AnttiArticle: 129623
On 27 Feb., 10:42, harisr...@gmail.com wrote: > Hello Techies, > I would like to use an off the shelf FPGA which I would be develpoing > to test an ASIC or other FPGA. My questions is, > 1. How do we connect the Output of FPGAs as Input of the ASIC and vice > versa? > 2. The FPGA has to check various protocols like SPI, UART and other > things? > > I need to know various methods by which this can be done. Any answers > on this will be greatly apprecaited. Jokes aside: You should first find out, how to connect an asic to an asic and how to connect an FPGA to an FPGA. Mabye you can deduce the answer to that question from that. Maybe you can find an example design that uses more than one chip and see how the connections are created. Here are some examples of how ASICs can be connected: 1. Optical http://www.eetimes.com/news/design/showArticle.jhtml;jsessionid=PA2UODNLZHDHMQSNDLOSKHSCJUNN2JVN?articleID=18311314 2. AC coupling http://www.ece.ncsu.edu/erl/html2/papers/paulf/2003/paulf_2003_09_franzon.pdf 3. + 4. + 5. 3D stacking Free Space Optical Interconnects Radio Coupling http://www.eetimes.com/conf/iedm/showArticle.jhtml?articleID=18306693&kc=5012 Kolja SulimmaArticle: 129624
How to convert real to signed. The range of real will be from -1 to 1, -5 to 5, -10 to 10 and so on. I would like to convert this range to a signed vector of bit width bw(generic). The data has to be scaled but I have no idea on how to do it. I have searched on the internet and did not find any valuable information.
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Compare FPGA features and resources
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