Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I need some references of where systolic arrays have actually been used in equipment or instruments. Thanks in advance, Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive OpticsArticle: 129626
- smith waterman algorithm for DNA matching - fully parallel filters, mainly FIR filters - all algorithms without feedback if implemented using pielining (pipelined array multipliers, benes sorters, ...) Kolja Sulimma On 29 Feb., 16:02, "Marc Reinig" <Ma...@newsgroups.nospam> wrote: > I need some references of where systolic arrays have actually been used in > equipment or instruments. > > Thanks in advance, > > MarcoArticle: 129627
FPGA wrote: > How to convert real to signed. The range of real will be from -1 to 1, > -5 to 5, -10 to 10 and so on. I would like to convert this range to a > signed vector of bit width bw(generic). The data has to be scaled but > I have no idea on how to do it. I have searched on the internet and > did not find any valuable information. > Start with modulo arithmetic. http://deadsmall.com/3AEArticle: 129628
On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
> How to convert real to signed. The range of real will be from -1 to 1,
> -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> signed vector of bit width bw(generic). The data has to be scaled but
> I have no idea on how to do it. I have searched on the internet and
> did not find any valuable information.
You will need to know magnitude width and fraction width as you will
be generating a fixed point decimal.
Magnitude width (MW) can be done by taking log2(limit) and adding 1
(to account for the sign bit).
Fraction width (FW) is then bw-MW.
Then you scale the result by 2**FW and convert it to an integer (which
then gives you your signed number).
Remember Integer(my_real) always rounds to nearest. If you dont want
to round to nearest, you have to write a function that rounds to zero,
otherwise removing the LSBs will always round down. (towards 0 for
+ve, away from 0 for -ve).
From puiterl@notaimvalley.nl Fri Feb 29 08:32:29 2008
Path: newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!feeder.news-service.com!newsgate.cistron.nl!xs4all!transit2.news.xs4all.nl!post.news.xs4all.nl!not-for-mail
Message-Id: <47c8339e$0$14345$e4fe514c@news.xs4all.nl>
From: Paul Uiterlinden <puiterl@notaimvalley.nl>
Subject: Re: real to signed
Newsgroups: comp.lang.vhdl,comp.arch.fpga
Followup-To: comp.lang.vhdl
Date: Fri, 29 Feb 2008 17:32:29 +0100
References: <013f9fad-e025-4dbb-b38c-237344f51e25@e25g2000prg.googlegroups.com>
Organization: AimValley
User-Agent: KNode/0.10.5
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Lines: 37
NNTP-Posting-Host: 80.127.156.247
X-Trace: 1204302751 news.xs4all.nl 14345 [::ffff:80.127.156.247]:41255
X-Complaints-To: abuse@xs4all.nl
Xref: prodigy.net comp.lang.vhdl:74011 comp.arch.fpga:141952
FPGA wrote:
> How to convert real to signed. The range of real will be from -1 to 1,
> -5 to 5, -10 to 10 and so on.
I don't understand this.
> I would like to convert this range to a
> signed vector of bit width bw(generic). The data has to be scaled but
> I have no idea on how to do it.
What do you mean by scaling?
> I have searched on the internet and did not find any valuable information.
If it is only about converting from real to signed, then first convert the
real to integer, and then to signed with the to_signed function from
ieee.numeric_std.
Something like this:
LIBRARY ieee;
USE ieee.numeric_std.ALL;
...
FUNCTION real2signed
(
r: real;
return_width: positive
) RETURN signed IS
BEGIN
RETURN to_signed(integer(r), return_width);
END FUNCTION real2signed;
--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
Article: 129629On Feb 29, 4:29 pm, Tricky <Trickyh...@gmail.com> wrote: > On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote: > > > How to convert real to signed. The range of real will be from -1 to 1, > > -5 to 5, -10 to 10 and so on. I would like to convert this range to a > > signed vector of bit width bw(generic). The data has to be scaled but > > I have no idea on how to do it. I have searched on the internet and > > did not find any valuable information. > > You will need to know magnitude width and fraction width as you will > be generating a fixed point decimal. > Magnitude width (MW) can be done by taking log2(limit) and adding 1 > (to account for the sign bit). > Fraction width (FW) is then bw-MW. > > Then you scale the result by 2**FW and convert it to an integer (which > then gives you your signed number). > Remember Integer(my_real) always rounds to nearest. If you dont want > to round to nearest, you have to write a function that rounds to zero, > otherwise removing the LSBs will always round down. (towards 0 for > +ve, away from 0 for -ve). PS. None of this is synthesisable, as it bases all working on reals, which you cannot synthesise in any way. Reals are only allowed to create constants (which then have to be of a synthesizable type). If you are trying now to synthesize your sine wave generator, you are going about it the wrong way.Article: 129630
Looks interesting. On Feb 25, 9:59 am, "Sylvain Munaut <Some...@SomeDomain.com>" <246...@gmail.com> wrote: > Hi, > > I wasn't very satisfied with the available assembler, so a few month > ago I wrote a new compiler for the Picobaze during my spare > weekends ... > > I just though I'd share it if anyone is interested .... > > It's available there : > http://www.246tnt.com/files/PBAsm_20080225.tar.bz2 > > Example usage: > python ./Codegen.py example.S out.mem > > WARNING: The last file on the command line is the output ... so if you > forget it, it will overwrite your last source file ... This may seem like a minor annoyance to you, but it is one of those things that a user will tire of very quickly... after about one lost file in fact. Couldn't you fix that so the output file is first or use option flags to indicate the output file such as -o name?Article: 129631
Thanks, I know the applications. I'm actually looking for specific equipment in which they have been used. i.e. XY corp. uses them in their ..., Univ. of X uses them in the XXX instrument, etc. Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive Optics "Kolja Sulimma" <ksulimma@googlemail.com> wrote in message news:8c68db12-c1d0-4f0d-9ec2-acf42e049107@u10g2000prn.googlegroups.com... >- smith waterman algorithm for DNA matching > - fully parallel filters, mainly FIR filters > - all algorithms without feedback if implemented using pielining > (pipelined array multipliers, benes sorters, ...) > > Kolja Sulimma > > On 29 Feb., 16:02, "Marc Reinig" <Ma...@newsgroups.nospam> wrote: >> I need some references of where systolic arrays have actually been used >> in >> equipment or instruments. >> >> Thanks in advance, >> >> MarcoArticle: 129632
On Feb 29, 11:50=A0am, Tricky <Trickyh...@gmail.com> wrote: > On Feb 29, 4:29 pm, Tricky <Trickyh...@gmail.com> wrote: > > > > > > > On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote: > > > > How to convert real to signed. The range of real will be from -1 to 1,= > > > -5 to 5, -10 to 10 and so on. I would like to convert this range to a > > > signed vector of bit width bw(generic). The data has to be scaled but > > > I have no idea on how to do it. I have searched on the internet and > > > did not find any valuable information. > > > You will need to know magnitude width and fraction width as you will > > be generating a fixed point decimal. > > Magnitude width (MW) can be done by taking log2(limit) and adding 1 > > (to account for the sign bit). > > Fraction width (FW) is then bw-MW. > > > Then you scale the result by 2**FW and convert it to an integer (which > > then gives you your signed number). > > Remember Integer(my_real) always rounds to nearest. If you dont want > > to round to nearest, you have to write a function that rounds to zero, > > otherwise removing the LSBs will always round down. (towards 0 for > > +ve, away from 0 for -ve). > > PS. None of this is synthesisable, as it bases all working on reals, > which you cannot synthesise in any way. Reals are only allowed to > create constants (which then have to be of a synthesizable type). > > If you are trying now to synthesize your sine wave generator, you are > going about it the wrong way.- Hide quoted text - > > - Show quoted text - I dont want to synthesize this.Article: 129633
On Feb 29, 11:29=A0am, Tricky <Trickyh...@gmail.com> wrote: > On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote: > > > How to convert real to signed. The range of real will be from -1 to 1, > > -5 to 5, -10 to 10 and so on. I would like to convert this range to a > > signed vector of bit width bw(generic). The data has to be scaled but > > I have no idea on how to do it. I have searched on the internet and > > did not find any valuable information. > > You will need to know magnitude width and fraction width as you will > be generating a fixed point decimal. > Magnitude width (MW) can be done by taking log2(limit) and adding 1 > (to account for the sign bit). MW and FW of output real changes with change in amplitude. What is 'limit'? > Fraction width (FW) is then bw-MW. > > Then you scale the result by 2**FW and convert it to an integer (which > then gives you your signed number). > Remember Integer(my_real) always rounds to nearest. If you dont want > to round to nearest, you have to write a function that rounds to zero, > otherwise removing the LSBs will always round down. (towards 0 for > +ve, away from 0 for -ve).Article: 129634
On Feb 28, 3:52=A0pm, Skogul <etork...@gmail.com> wrote: > These approaches seem to work. Thanks. Yes, it works but the whole project will be re synthesized which is time consuming. Instead, you can change a parameter of your IP in mhs - and that IP only will be re synthesized and merged with the rest of the project. Another option is to use OPTION CORE_STATE =3D DEVELOPMENT in the IP's mpd and the core will be synthesized every time you run platgen. More detail in C:\EDK\doc\usenglish\psf_rm.pdf page 38Article: 129635
Excellent! Jonathan.
I was wondering what those strange initial numbers were.
I tried to divide the memory into two parts, mem_hi and
mem_lo, but got errors when mem_lo was 31 downto 0
in length. Dividing it half-half like you suggeted seems
OK, but the objective was to see the memory data in its
entirety.
The std_logic_vector approach works much cleaner. How
inefficient is it? Does it use burn an integer for
each bit of simulated memory? Or 36 to 1 inefficiency?
The code is shown below.
Thanks again,
Brad Smallridge
AiVision
The code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_tri is
port(
clk : in std_logic;
mem_wr_n : in std_logic; -- active low memory write
mem_addr : in std_logic_vector(17 downto 0); --18 bits 256K
mem_data : inout std_logic_vector(35 downto 0) );
end mem_tri;
architecture beh of mem_tri is
signal mem_wr_1 : std_logic;
signal mem_wr_2 : std_logic;
signal mem_addr_1 : std_logic_vector(17 downto 0);
signal mem_addr_2 : std_logic_vector(17 downto 0);
signal mem_rd_data : std_logic_vector(35 downto 0);
-- keep the size of the memory small here
-- to keep ModelSim simulation convenient
constant size : integer := 128;
type mem_array_type is array(0 to size-1) of std_logic_vector(35 downto
0);
signal mem_array : mem_array_type;
begin
memory_proc:process(clk)
variable addr1 : integer;
variable addr2 : integer;
begin
if(clk'event and clk='1')then
mem_wr_1 <= mem_wr_n;
mem_wr_2 <= mem_wr_1;
mem_addr_1 <= mem_addr;
mem_addr_2 <= mem_addr_1;
addr1 := to_integer(unsigned(mem_addr_1));
addr2 := to_integer(unsigned(mem_addr_2));
if( addr2 <= size and mem_wr_2='0' )then
mem_array(addr2) <= mem_data;
end if;
if( addr1 <= size-1 )then
if( mem_wr_2='1' )then
mem_rd_data <= mem_array(addr1);
else
mem_rd_data <= (others=>'0');
end if;
else
-- 82 for out-of-range memory locations
mem_rd_data <= std_logic_vector(to_unsigned(82,36));
end if;
end if;
end process;
tri_state:process(mem_rd_data,mem_wr_2)
begin
if(mem_wr_2='1')then -- read command, memory outputs
mem_data <= mem_rd_data;
else
mem_data <= (others=>'Z');
end if;
end process;
end beh;
Article: 129636
On Fri, 29 Feb 2008 11:03:42 -0800, Brad Smallridge wrote:
> the objective was to see the memory data in its entirety.
Then it is probably best to represent it as a vector.
On the other hand, if you represent it as a pair (or more)
of integers, you will surely convert it to/from a vector
on read and write, so you will get to see it "whole"
at that point.
If you want to see it *whilst it's in the memory*, then
consider storing it in 16-bit pieces (in integers). You
can then display each location in hex, and it will look
something like this in the wave and list views:
{0004 8fe7 327e}
so you can see your 36-bit value easily enough. It'll
still cost you some messy conversion functions, though.
>The std_logic_vector approach works much cleaner. How
>inefficient is it? Does it use burn an integer for
>each bit of simulated memory? Or 36 to 1 inefficiency?
I don't know. On the face of it you'd expect the
simulator to spend one byte (or, perhaps, one word)
for each std_logic bit. But the std_logic and
numeric_std packages have highly optimised implementations
in the simulator, so I wouldn't be so sure. In any case,
you are restricting the size of your memory - so its
total footprint will be insignificant. If you really
need lots of modelled memory, take a look at the docs
on "sparse memories" - that's now implemented in at
least some variants of Modelsim/Questa.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 129637
Hi Amir,
What you do is quite interesting! We have gone through a similar
process and i must say that
although it is a painful one it is a fun work as well!
On Feb 27, 10:54 pm, Xesium <amirhossein.gholamip...@gmail.com> wrote:
> Hi everybody,
> I'm trying to partially reconfigure my device (XC2VP30 on ML310 board)
> through ICAP. I have my ICAP attached to OPB which is attached to
> Microblaze. In bitgen.ut file I have set the value of mode pins
> (M2M1M0) to 1 (PULLUP). So it is not set on 101 which is JTAG mode. As
This is correct. Also be aware that the Persist bit shouldn't be set;
otherwise ICAP
will be disabled.
> well the base address and high address of my HWICAP is 0x42000000 and
> 0x42000fff as mentioned in the datasheet of HWICAP. Initially my OPB
> clock frequency was 100 MHz but now I have reduced it to 25MHz. The
> system contains a timer, a SysAce, a hwicap, a uartlite and an opb-mdm
> (for debugging) all attached to the opb. The microblaze has some local
> memory too. I'm also using EDK, ISE 8.2. That's the whole setting
I would suggest you to transit to the EDK, ISE 9.1+SP2. Moreover, EAPR
tools
would help you boosting your design. Check the link
http://www.xilinx.com/support/prealounge/protected/index.htm
> about my system. Now here is the problem:
>
> I just need to measure the delay of reconfiguration through ICAP. The
> following is a very simple C code I have implemented to read a frame
> and print the content on the screen. Later I want to write something
> to a frame and again read it back just to make sure that in fact it
> changed the reconfiguration. Firstly I initialize the ICAP module and
> then invoke XHwIcap_DeviceReadFrame() and then I read the
> configuration through XHwIcap_StorageBufferRead().
>
> XHwIcap my_icap;
>
> XStatus icap_stat;
>
> icap_stat = XHwIcap_Initialize(&my_icap,
> XPAR_OPB_HWICAP_0_DEVICE_ID, XHI_READ_DEVICEID_FROM_ICAP);
>
> if(icap_stat != XST_SUCCESS)
> print("\n There is something wrong in initializing the ICAP!!
> \n");
>
> Xuint32 frame_content;
>
> icap_stat = XHwIcap_DeviceReadFrame(&my_icap, XHI_FAR_CLB_BLOCK,
> 32, 32);
>
> if(icap_stat != XST_SUCCESS)
> print("\n There is something working in reading a frame with col
> = 5 and lut_bit = 3!!!!!\n");
>
> for(i = 0; i < my_icap.WordsPerFrame; i++)
> {
> print("word number");
> putnum(i+1);
> print(" is equal to: ");
> frame_content = XHwIcap_StorageBufferRead(&my_icap, i);
> putnum(frame_content);
> putchar('\n');
> }
>
> The problem is when I read back the frame except for the first 7 words
> everything is 0, no matter what frame it is.
> I have carefully studied ICAP's driver's functions and their
> implementation. I know that the driver writes the first 7 words in the
> storage buffer but even the 7 words that I read from the storage
> buffer is not the same as the ones that the driver's deviceRead
> function writes to the storage buffer. So I don't get what the problem
> is.
> The seven words that I read are as follows:
>
> 30008001
> 0000000d
> ffffffff
> ffffffff
> 30002001
> 00404000
> 2800619c
>
> However for example based on the driver's implementation the first
> word should be 0xFFFFFFFF which is an XHI_DUMMY_PACKET.
>
> So as I mentioned, my problem is I can't basically read a frame of
> configuration correctly. Do you have any idea where I'm doing wrong or
> what the problem is?
>
We have not tried the readback operation but...are you sure that you
read the correct address
the XHI_DUMMY_PACKET is stored in?
Why don't you first try to write and then read what you wrote?
Use the functions XHwIcap_StorageBufferWrite() and
XHwIcap_DeviceWrite().
Also notice that if you use JTAG to initially program the device, and
then ICAP you can use them on the same design but, between each mode
the configuration logic has to be desynchronized. In order to use the
ICAP port you should use the XhwIcap_CommandDesync() function.
> As well I have some doubts and questions. Firstly why should we first
> read a frame, modify it and then write it back to the configuration?
> Can't we just write something to the device? I haven't still worked
> with difference-based reconfiguration and it might have something to
> do with that. But if I just want to write configuration to one frame
> that doesn't implement any other part of any other circuit, can't I
> just write something to that frame without first reading it and
> modifying it?
The on-chip reconfiguration operates in a read-modify-write manner.
The date frame
is read back from the ICAP port and stored in the BRAM of the HWICAP
(see below)
in which the processor modifies the data. Afterwards, the HWICAP
downloads
the new data back to the configuration memory through the ICAP port.
>
> The second question that I have is about the storage buffer of the
> HWICAP module. Firstly I thought that I have to set an opb_bram so
> that HWICAP can use it. However later through studying the driver I
> realized that the base address for HWICAP is the same as storage
> buffer (which is the BRAM) so I concluded that when I use a HWICAP I
> implicitly assign a BRAM to it. Is this so? If not please let me know.
The "xhwicap_i.h" header file contains the XHI_MAX_BUFFER_INTS
constant which defines the size of the ICAP BRAM . The HWICAP BRAM,
i.e. storage buffer,
is implemented with a BRAM of which the 512 words at maximum are used
(at least the above
stands for EDK 7.1.i in which we conducted the experiments).
>
> The third question is the clock frequency that ICAP operates! I have
> read somewhere that the highest is 66MHz. Is it correct or we can set
> the clock higher than that?
Yes, this is the ICAP's frequency for the Virtex-2 when BUSY signal is
checked
(50 MHz when not checked). New devices like Virtex-4 embed an 100 Mhz
ICAP.
>
> This message became very long, but I really appreciate it if you could
> kindly help me out with it. I have read many of the previous posts
> about ICAP but couldn't find enough information to solve my problems.
> So perhaps this post can be a complement to them.
>
> Thanks a lot beforehand,
>
> Amir
I hope this helps. Keep up the good work and let me know about the
result.
Besides PR entails a hell of details!:)
Take care,
Kyprianos
Article: 129638> >Microblaze. In bitgen.ut file I have set the value of mode pins > > (M2M1M0) to 1 (PULLUP). So it is not set on 101 which is JTAG mode. As > >well the base address and high address of my HWICAP is 0x42000000 and > >0x42000fff as mentioned in the datasheet of HWICAP. Initially my OPB Amir, In which way to you load the initial configuration? Do you load it through the ICAP and you don't use ICAP at all?Did you check the Persist option? As a second thought check the ICAP configuration. Has it been configured appropriately? Have the base address and the high address been added in the xparameters.h file? Take care, KyprianosArticle: 129639
Hi all I want to implement face detection on fpga Is there any free code available Or is there any code for edge detection available. Plz help I need ity very much.Article: 129640
Hi. I have Quartus 7.2sp2, MS Vista , and I have a project where I define ROM memory (with size 4096*32 bits). I define it in verilog file in "initial" section. When synthesing, quartus_map.exe allocates as much as 1.5Gb of memory and going into swapping. My computer has 2Gb of physical RAM. So, how ROM block in verilog should be defined correctly? Am I correct? If so, should I check some option in Quartus so it will not to optimize that ROM block? In general, is there any option which can disable Quartus to allocate such huge memory chunks and so on?Article: 129641
The problem is, that in many cases the publications do not clearly state whether a systolic algorithm is used. You can only assume that any problem that can be solved by systolic algorithms will be solved by systolic algortithms if done in hardware. A recent one: http://www.sgi.com/company_info/newsroom/press_releases/2007/november/fpga.html Kolja On 29 Feb., 18:41, "Marc Reinig" <Ma...@newsgroups.nospam> wrote: > Thanks, > > I know the applications. > > I'm actually looking for specific equipment in which they have been used. > i.e. XY corp. uses them in their ..., Univ. of X uses them in the XXX > instrument, etc. >Article: 129642
Hi recent events: 1) trying to use Xilinx Cable III (actually Amontec chameleon) to program actel PA3 on protoboard using DirectC 2) with big fights i got "random" results sometimes reading first IDCODE ok, but NEVER passing any further 3) after disconnecting GND it looked to be better (% of succes IDCODE reads increased a little) 4) now i disconnected 2 wires that delivered power to the Actel FPGA 5) measured at one side of those wires 3.3V (at power source) 6) measured other side 4V !!! (just plain 2 wires open in my hands, no load connected, fingers not touching) ? 7) now I called my wife to check out my doings (to prevent any other CAN NOT BE THINGS...) 8) look here, i measure here, we have 3.3V right? yes she says 9) and now look the same wires, i measure here it will be 4V I say, i connect the multimeter and we both see 3.3V 10) now I connected the 2 power wires back to actel FPGA board 11) and start the directC, and it works 100%, it does flash the FPGA and reports FULL success! I had checked the connectors before myself several times with no luck, now she is just close and looking... and it all just starts to work! No explanation. But yes, DVB anttennas, WIFI sticks, are also afraid of her...maybe she should start business of scaring things to work ;) http://www.truedream.org/smile/KnittingWifeSigned.pdf smile, smile, smile :) AnttiArticle: 129643
Antti wrote: > Hi > > recent events: > > 1) trying to use Xilinx Cable III (actually Amontec chameleon) to > program actel PA3 on protoboard using DirectC > 2) with big fights i got "random" results sometimes reading first > IDCODE ok, but NEVER passing any further > 3) after disconnecting GND it looked to be better (% of succes IDCODE > reads increased a little) > 4) now i disconnected 2 wires that delivered power to the Actel FPGA > 5) measured at one side of those wires 3.3V (at power source) > 6) measured other side 4V !!! (just plain 2 wires open in my hands, no > load connected, fingers not touching) ? > 7) now I called my wife to check out my doings (to prevent any other > CAN NOT BE THINGS...) > 8) look here, i measure here, we have 3.3V right? yes she says > 9) and now look the same wires, i measure here it will be 4V I say, i > connect the multimeter and we both see 3.3V > 10) now I connected the 2 power wires back to actel FPGA board > 11) and start the directC, and it works 100%, it does flash the FPGA > and reports FULL success! > > I had checked the connectors before myself several times with no luck, > now she is just close and looking... and it all just starts to work! > No explanation. But yes, DVB anttennas, WIFI sticks, are also afraid > of her...maybe she should start business of scaring things to work ;) > > http://www.truedream.org/smile/KnittingWifeSigned.pdf > > smile, smile, smile :) > Antti Perhaps the power supply was oscillating... Are you using an LDO regulator ? These can be unstable with low ESR capacitive loading.Article: 129644
Antti schrieb: > http://www.truedream.org/smile/KnittingWifeSigned.pdf > > smile, smile, smile :) > Antti Nice. But just in case you did'nt notice, valentines are over for this year. ;-) Reagrds FalkArticle: 129645
On 1 Mrz., 21:34, Arlet Ottens <usene...@c-scape.nl> wrote: > Antti wrote: > > Hi > > > recent events: > > > 1) trying to use Xilinx Cable III (actually Amontec chameleon) to > > program actel PA3 on protoboard using DirectC > > 2) with big fights i got "random" results sometimes reading first > > IDCODE ok, but NEVER passing any further > > 3) after disconnecting GND it looked to be better (% of succes IDCODE > > reads increased a little) > > 4) now i disconnected 2 wires that delivered power to the Actel FPGA > > 5) measured at one side of those wires 3.3V (at power source) > > 6) measured other side 4V !!! (just plain 2 wires open in my hands, no > > load connected, fingers not touching) ? > > 7) now I called my wife to check out my doings (to prevent any other > > CAN NOT BE THINGS...) > > 8) look here, i measure here, we have 3.3V right? yes she says > > 9) and now look the same wires, i measure here it will be 4V I say, i > > connect the multimeter and we both see 3.3V > > 10) now I connected the 2 power wires back to actel FPGA board > > 11) and start the directC, and it works 100%, it does flash the FPGA > > and reports FULL success! > > > I had checked the connectors before myself several times with no luck, > > now she is just close and looking... and it all just starts to work! > > No explanation. But yes, DVB anttennas, WIFI sticks, are also afraid > > of her...maybe she should start business of scaring things to work ;) > > >http://www.truedream.org/smile/KnittingWifeSigned.pdf > > > smile, smile, smile :) > > Antti > > Perhaps the power supply was oscillating... > > Are you using an LDO regulator ? These can be unstable with low ESR > capacitive loading. 1) I borrow 3.3V from Xilinx starterkit boards user connectors, this is OK, another actel PCB powered from can be flashed with flashpro3 OK 2) the TARGET board is just protoboard with A3P250 on it, JTAG and DIODES to drop voltage 3.3V-->1.545V + caps of course now, the WORKS OK result was unfortunatly just ONE time event, that is 50 times before it did not work, 51 my wife looked WORK FULL SUCCESS 52 ..100.. not work (also when she comes to look) what is strange is that there is dependancy on the failure if the DirectC code is compiled with Release or Debug setting in VC2005 !! similar things are visible with impact where the access to actel JTAG is different when using SVF vs XSVF (execution speed issues) most stable is my own SVF player, that passes beyond the place where the directC failes with no random errors, but I also had "execution speed" related issues with actel jtag I wish someone could explain me why Actel uses IRPAUSE/DRPAUSE an not RTI/IDLE as "parking state"... maybe it is not all related, but still curious oh yes, I should get another target board, and another cable, etc.. Antti PS I did not notice valentines this year (that is I did not know the date when it was the day)Article: 129646
On Feb 28, 10:18 pm, MikeShepherd...@btinternet.com wrote: > >>...want to design a FPGA-based PC scope > >>...May I write this in C++ Builder or Visual Basic...? > >C/C++ language is the choice (of weapon). Basic is not an appropriate language. > > I'd love to hear why "Basic is not an appropriate language". Programming in Visual Basic is known to cause severe brain-damage. Use C and you only learn one language and one compiler (gcc) for Windows, Linux, Mac, 32-bit ARMs, and even 8-bit AVR CPUs. Even many of the API's are the same from AVR to Windows You can do all this under Ubuntu Linux: http://iso.linuxquestions.org/ You can install it dual boot on your PC or a virtual machine if the pc is fast enough. Don't worry the resize Windows NTFS feature is magical and harmless. as root: install gcc and automake tools as well as any development library headers. Unlike downloading and installing exe's under windows, under linux you can anything, all headers, programs, etc from the gui tool synaptic or the command line tool aptitude. This tool is called a package manager. Windows lacks one of these and is on of the many reasons I avoid using MS. A great library in C for displaying data, even in real time: http://www.eudoxos.net/gtk/gtkdatabox/ Examples are included with the tar-ball. Use glade-3: http://glade.gnome.org/ to design the user interface UDP Socket programmings example from: http://beej.us/guide/bgnet/output/html/multipage/clientserver.html The code: http://beej.us/guide/bgnet/examples/listener.c http://beej.us/guide/bgnet/examples/talker.c The Socket guide is at: http://beej.us/guide/bgnet/output/html/multipage Personally I use the FT232RL for most of my embedded stuff. No need for a 232 level shifter, it goes straight from USB to UART: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=604-00043-ND You could also go straight USB w/ the FPGA, but thats a bit of a pain and isn't perfect USB either. Check out opencores.org if you go the UDP route for Verilog/VHDL cores so you don't reinvent the wheel or any other widgets. There are tons of C examples on the net to pull from. Just google. -BrianArticle: 129647
Thanks Kolja, Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive Optics "Kolja Sulimma" <ksulimma@googlemail.com> wrote in message news:7288fa8d-1318-4ef1-95eb-ea6c374c1ed0@u72g2000hsf.googlegroups.com... > The problem is, that in many cases the publications do not clearly > state whether a systolic algorithm is used. > You can only assume that any problem that can be solved by systolic > algorithms will be solved by systolic algortithms if done in hardware. > > A recent one: > http://www.sgi.com/company_info/newsroom/press_releases/2007/november/fpga.html > > Kolja > > On 29 Feb., 18:41, "Marc Reinig" <Ma...@newsgroups.nospam> wrote: >> Thanks, >> >> I know the applications. >> >> I'm actually looking for specific equipment in which they have been used. >> i.e. XY corp. uses them in their ..., Univ. of X uses them in the XXX >> instrument, etc. >> > >Article: 129648
Hi Kyprianos,
Thanks a lot for your comments. I checked to make sure that persist
bit is also not set. I also checked the base and high address in
xparameters.h file and they are as I had set them before. I'm actually
configuring my device using parallel cable 4 and through JTAG (I
guess!). I wasn't desynchronizing before using ICAP but now I tried
doing that to make sure that I'm not doing anything wrong. I'm not
sure how I can verify ICAP's correct configuration, but I actually
print ICAP's base address (using putnum(my_icap.BaseAddress);
statement) to make sure that it is the same as what I'd set before and
it is actually the same! However the result for me is still the same!
I tried changing the Major and Minor address that I'm writing to.
Nothing really changes if I just read it. But when I try writing to it
(just writing an arbitrary value (0xFFFFFFFF) to some address in the
storage buffer!) and then reading it exactly as the following code,
sometimes the output of DeviceReadFrame method is that the device is
busy and just then it gives me some numbers that some of them actually
are not 0. However it never happens that I actually read the same
value that I'm writing! I'm wondering, for example in your case, how
is the content of the storage buffer when you read back the
configuration? Is it mostly 0 and a few of them are non-zero?
Should I be reading words or bytes? Because I realized that when I'm
reading from compact flash I'm actually reading in bytes not words! So
when I'm writing to the storage buffer of ICAP should I be writing in
bytes or in words? If it should be in words then it means that I have
manipulate the data I'm reading from Compact Flash!
Well that's another problem but for now I can't get the ICAP work and
appreciate any suggestion and comment!
For now I'll try installing ISE and EDK 9.2 instead of 8.2 and am
keeping my fingers crossed that may work!
Thanks a lot,
Amir
My code is as follows:
XHwIcap my_icap;
XStatus icap_stat;
icap_stat = XHwIcap_Initialize(&my_icap,
XPAR_OPB_HWICAP_0_DEVICE_ID, XHI_READ_DEVICEID_FROM_ICAP);
if(icap_stat != XST_SUCCESS)
print("\n There is something wrong in initializing the ICAP!!
\n");
icap_stat = XHwIcap_CommandDesync(&my_icap);
if(icap_stat != XST_SUCCESS)
print("\n Desynchronization was not successful!\n");
XHwIcap_StorageBufferWrite(&my_icap, 25, 0xffffffff);
icap_stat = XHwIcap_DeviceWriteFrame(&my_icap, XHI_FAR_CLB_BLOCK,
20, 32);
print("A frame has been written to the device\n");
if(icap_stat != XST_SUCCESS)
print("There is something wrong in writing to the device!");
Xuint32 frame_content;
icap_stat = XHwIcap_DeviceReadFrame(&my_icap, XHI_FAR_CLB_BLOCK,
20, 32);
print("The same frame is read from the configuration\n");
if(icap_stat != XST_SUCCESS)
print("\n There is something wrong in reading a frame with col =
5 and lut_bit = 3!!!!!\n");
if(icap_stat == XST_DEVICE_BUSY)
print("\n Device is busy right now!\n");
if(icap_stat == XST_BUFFER_TOO_SMALL)
print("BUFFER is TOO SMULL!\n");
if(icap_stat == XST_INVALID_PARAM)
print("XST_INVALID_PARAM!\n");
for(i = 0; i < my_icap.WordsPerFrame; i++)
{
print("word number");
putnum(i+1);
print(" is equal to: ");
frame_content = XHwIcap_StorageBufferRead(&my_icap, i);
putnum(frame_content);
putchar('\n');
}
On Feb 29, 8:29 pm, kyprianos <kpapa...@mhl.tuc.gr> wrote:
> > >Microblaze. In bitgen.ut file I have set the value of mode pins
> > > (M2M1M0) to 1 (PULLUP). So it is not set on 101 which is JTAG mode. As
> > >well the base address and high address of my HWICAP is 0x42000000 and
> > >0x42000fff as mentioned in the datasheet of HWICAP. Initially my OPB
>
> Amir,
>
> In which way to you load the initial configuration? Do you load it
> through the ICAP and you don't use
> ICAP at all?Did you check the Persist option?
> As a second thought check the ICAP configuration. Has it been
> configured appropriately? Have the base address and the high address
> been added in the xparameters.h file?
>
> Take care,
> Kyprianos
Article: 129649
Hi,
Has anyone used this card with Xilinx System Generator to do hardware in
the loop simulation. I can not find a board description file for it in the
form that the System Generator wants. There is a utility in System
Generator called xlSBDBuilder;or something like that helps one create the
needed files to do hardware in the loop simulation over the JTAG, but you
need to know the pinouts of all the ports used on the card.
If someone has already done this I'd greatly appreciate a copy of the needed
files.
Thanks,
CTW
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z