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> - ran a small, simple test case on the CPU, and recorded changes in > the program counter (PC) > - fed the recorded PCs back into my desktop computer ... (for this > particular design, I was able to use an existing serial connection) > - I wrote a small C program to gather the results coming in the serial > port and analyze the PCs that were output by the CPU (to compare it to > expected results) Interesting approach I have to admit. But is in my case probably not applicable as I execute programs that include almost no jmp or branch instructions. So for me it is essential that I could read out the register content or maybe the RAM content at the end of the computation. Would be thankful for more such ideas ;)Article: 128051
On Jan 14, 7:47 am, FPGA <FPGA.unkn...@gmail.com> wrote: > Could you please explain in more detail http://www.actel.com/documents/Fusion_Waveform_TB.pdf K.Article: 128052
> What about adding a simple UART or low-cost HD44780 (or compatible) LCD > displays to your processor. Hm LCD Display would be interesting. The problem is, that I have zero experience with this kind of approach. So I dont know how difficult it would be to connect such a LCD display.. is it straightforward?Article: 128053
On Jan 14, 7:48=A0am, Zorjak <Zor...@gmail.com> wrote: > Hi everyone > > Can someone please help me. If I have to connect two FPGA circuits on > the same board and their pins are not compatible waht should I do? > If someone knows some good link about this, anything that you think > that will be useful, please tell me. > > Thanks > Zoran Is the problem that one FPGA has balls and the other has pins? Is the problem that one FPGA development board has 2mm connectors and the other 0.1 inch? Is the problem that one FPGA has TTL lines and the other has LVDS? Ask a question that someone can answer as opposed to simply a question that you can ask and you may get better help. With FPGAs, the I/O standards are typically controlled by the designer so it is NOT obvious what your situation is.Article: 128054
On 14 Jan., 16:36, FPGA <FPGA.unkn...@gmail.com> wrote: > Can anyone give guidelines on how to generate sine and cosine wave in > VHDL? You can build a numerical oscillator: Initialization: sin[0] = 1; cos[0] = 0; Iteration: sin[t] = sin[t-1]-cos[t-1]*k; cos[t] = cos[t-1]+sin[t-1]*k; The Frequency depends on k. If k is 1/2**k you do not even net a multiplier. This only works for a continues sequence of values. If you need values in random order you must use a lookup table or CORDIC. Both are available as cores in ISE. Kolja Sulimma cronologic ohgArticle: 128055
On Jan 11, 8:09 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Fri, 11 Jan 2008 05:22:48 -0800 (PST), > > Pablo <pbantu...@gmail.com> wrote: > > hi Pablo > > >variable int : integer range 0 to 64:=0; > >begin > >process > > begin > >int := int + 1; > >end process; > > >And the values: 0 1 2 3 4... 64 0 1 2 3 4 5.... > > You want wrap-around at some upper limit. > > > But the real case is that : 0 1 2 3 4 ... 64 64 64 64 64 64 64 > > Really? That seems strange. You should get a runtime error when > you try to increment from 64 to 65, because 65 is outside the range of > the variable. > > You can easily do it... > > if int < LIMIT then > int := int + 1; > else > int := 0; > end if; > > However, if your limit is "all ones" in a binary number > (e.g. 31, 63, 127, 255) it may be simpler to use UNSIGNED > data instead of integer data. UNSIGNED values are a > vector of std_logic bits, and arithmetic will wrap around > from (2**N)-1 to 0. > > You may get more help on comp.lang.vhdl. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. If the limit were "all ones" (2**N-1, which it is not in this case), then you could just: int := (int + 1) mod LIMIT+1; And it will synthesize without additional hardware. If LIMIT+1 /= 2**N, the the above will still simulate correctly in a test bench, but most synthesis tools will not accept it (rem, mod or divide by non-integral power of two). Again, this is a rollover, not a saturate behavior. AndyArticle: 128056
"pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmg17p$1ur$1@aioe.org... >> What about adding a simple UART or low-cost HD44780 (or compatible) LCD >> displays to your processor. > > Hm LCD Display would be interesting. The problem is, that I have zero > experience with this kind of approach. So I dont know how difficult it > would be to connect such a LCD display.. is it straightforward? Have a look on the web, there are lots of projects that use the Hitachi HD44780 (or compatible) controller chip. The interface is a simple 4/8 bits bus with some strobe signals. http://en.wikipedia.org/wiki/HD44780_Character_LCD You can hook one up to your parallel port (assuming you still have one) and experiment with it first before you connect it to your processor. http://www.beyondlogic.org/parlcd/parlcd.htm You can find these modules on ebay for very little money. Hans www.ht-lab.comArticle: 128057
I have heard that FPGA's can have a much larger throughput, dollar per dollar, than a special purpose DSP chip because of their parallelism. Anyone here have any experience or pointers on this topic?Article: 128058
"FPGA" <FPGA.unknown@gmail.com> wrote in message news:9219f61f-678d-4ed3-801c-3a873f2a467b@k39g2000hsf.googlegroups.com... > Can anyone give guidelines on how to generate sine and cosine wave in > VHDL? library IEEE; use IEEE.MATH_REAL.all; signal x,y : real;begin x <= sin(y);end;HTH., Syms.Article: 128059
http://www.xilinx.com/products/design_resources/dsp_central/grouping/index.htm It depends. If the processing requirement can be met with the use of a DSP uC (like TI's family of DSP micros), then those microprocessor based DSP engines are lower power, and lower cost. If the processing can not be done by a microprocessor (they are too slow), then using the massively parallel capabilities of the FPGA is often the ONLY solution. As well, being massively parallel, and fast, sometimes the FPGA can process many different streams of lower speed data, and replace multiple DSP microprocessors, also resulting in a better cost tradeoff. Often, the FPGA will save a lot of power in replacing hundreds of microprocessor DSP chips. AustinArticle: 128060
ratemonotonic wrote: > Hi all , > > I am new to xilinx tool and currently I am working with a project > constructed using EDK 7.1. I am using EDK 9.2. > > In this old project Xilnet is used for a webserver demo talking to an > external MAC/PHY chip (SMSC 91C111). > > Where can I get this library ? > xilnet was deprecated for the last few releases. It is still there in 9.2, but will go away in 10.1. The preferred solution is to use lwIP. /SivaArticle: 128061
comp.arch.fpga wrote: > On 14 Jan., 16:36, FPGA <FPGA.unkn...@gmail.com> wrote: >> Can anyone give guidelines on how to generate sine and cosine wave in >> VHDL? > > You can build a numerical oscillator: > > Initialization: > sin[0] = 1; > cos[0] = 0; > > Iteration: > sin[t] = sin[t-1]-cos[t-1]*k; > cos[t] = cos[t-1]+sin[t-1]*k; > > The Frequency depends on k. If k is 1/2**k you do not even net a > multiplier. > > This only works for a continues sequence of values. If you need values > in random > order you must use a lookup table or CORDIC. Both are available as > cores in ISE. > > Kolja Sulimma > cronologic ohg If you slightly modify the iteration, like this: sin[t] = sin[t-1] - cos[t-1] * k; cos[t] = cos[t-1] + sin[t] * k; then the solution doesn't suffer from accumulating rounding errors, at the cost of some distortion.Article: 128062
On 14 Jan., 19:02, lm317t <lm3...@gmail.com> wrote: > I have heard that FPGA's can have a much larger throughput, dollar per > dollar, than a special purpose DSP chip because of their parallelism. > Anyone here have any experience or pointers on this topic? What about googling ? http://www.google.de/search?hl=de&q=%22fpga+vs+dsp%22&meta= I quess a important difference between FPGA and DSP is programming. DSP is more for the "procedural" Software Engineer. FPGA is more for the "parallel" Hardware/Logic design engineer. And yes, you may get much more MACs(Multiplyaccumulate/second)/dollar in a FPGA, but at higher development effort. You dont't write a procedural signal processing routine then, you design a parallel running logic circuit and also need to care about timing. Although utilizing a modern DSP may also get difficult and you have to care much about pipelining. And with a DSP you get lot's of IP already on chip like DMA Controller, SDRAM interface etc. With a FPGA you need to do much more than reading the DMA doc and setting up it's registers to have a SDRAM/DMA interface making use of the FPGA's power, although there may be also some IP. I guess dedicated DSP chips will specialize to niches where they are surrounded by application specific mixed signal (like A/D) and specialized circuits (like FLASH) to give a low cost system on chip solution. FPGA's with DSP capabilities will take over the high performance more general purpose DSP maket like for example video processing when the extra effort in development pays off or IP and development tools enables it. All this for the lower Quantities where it is not covered by ASICS or Custom IC's.Article: 128063
Are you using one of the xilinx development boards? IF so you could make use of the on-board LCD or if you have an older model board the 7 segment LED display. "pg4100" <pg4100@yahoo.co.uk> wrote in message news:fmg17p$1ur$1@aioe.org... >> What about adding a simple UART or low-cost HD44780 (or compatible) LCD >> displays to your processor. > > Hm LCD Display would be interesting. The problem is, that I have zero > experience with this kind of approach. So I dont know how difficult it > would be to connect such a LCD display.. is it straightforward? >Article: 128064
In this case the VHDL is working the same way a piece of Verilog code would. The signal does change just as it would in verilog but the value change occurs in 0 time. You are quite right that the previous code needs a state machine controling it inoder to have data_buffer<="0000_0000_0000_0000_1111" written. "Ben Jackson" <ben@ben.com> wrote in message news:slrnfom4gj.25b0.ben@saturn.home.ben.com... > On 2008-01-14, Nick <tklau@cuhk.edu.hk> wrote: >> data_buffer <= "00000000000001111"; --A >> sram_io <= data_buffer; >> data_buffer <= "00000000000000000101"; --B > > I don't speak VHDL, but in Verilog if you wrote something like that > in a process that happened on every clock, the first assignment of > data_buffer would be overridden by the second. If you want a series > of steps (outside of simulation) you're going to have to do it with > some kind of counter or state machine. > > Eg: > > data_buffer <= phase_a ? 20'b1111 : 20'b0101; > > (in Verilog, but you get the idea) > > -- > Ben Jackson AD7GD > <ben@ben.com> > http://www.ben.com/Article: 128065
I am trying to write a sunction for complex multiplication of 2 complex numbers function complex_multiply(a : signed; b: signed; c : signed; d: signed) return signed; (a + bi)(c + di) = [ac - bd] + [ad + bc]i. I am not sure on how I would return the real and imaginary part of the result. As per my understanding functions can return only one value. How do i represent the inputs and outputs? I want to write code in VHDL to be implemented on an FPGA.Article: 128066
Ann a écrit : > I am trying to write a sunction for complex multiplication of 2 > complex numbers > > function complex_multiply(a : signed; b: signed; c : signed; d: > signed) return signed; > (a + bi)(c + di) = [ac - bd] + [ad + bc]i. > > I am not sure on how I would return the real and imaginary part of the > result. As per my understanding functions can return only one value. > How do i represent the inputs and outputs? I want to write code in > VHDL to be implemented on an FPGA. Hi Define your complex number as an array of two signed numbers type complex is array(0 to 1) of signed(your_range); function complex_multiply(a : complex; b : complex) return complex; (a(0) + a(1).i)(b(0) + b(0).i) = [a(0)b(0)-a(1)b(1)] + [a(0)b(1) + a(1)b(0)]i You could even overload the '*' operator for type complex NicolasArticle: 128067
On Jan 14, 3:04=A0pm, Ann <thakkar.an...@gmail.com> wrote: > I am trying to write a sunction for complex multiplication of 2 > complex numbers > > function complex_multiply(a : signed; b: signed; c : signed; d: > signed) return signed; > (a + bi)(c + di) =3D [ac - bd] + [ad + bc]i. > > I am not sure on how I would return the real and imaginary part of the > result. As per my understanding functions can return only one value. > How do i represent the inputs and outputs? I want to write code in > VHDL to be implemented on an FPGA. Define a new complex record type... type t_My_Complex_Type is record Real: signed; Imag: signed; end record; Now your function would be defined as function complex_multiply(a, b : t_My_Complex_Type) return t_My_Complex_Type is variable RetVal: t_My_Complex_Type; begin RetVal.Real :=3D a.real * b.real - a.imag * b.imag; RetVal.Imag :=3D a.real * b.imag + b.real * a.imag; return(RetVal); function complex_multiply; If you're really feeling gutzy, you can instead call the function "*" (with the double quotes) and you'll be defining an override for the multiply operator so you could use your function like this... C <=3D A * B; instead of C <=3D complex_multiply(A,B); But I would suggest getting it working with the new type and seeing how that all works first. Record types are synthesizable. Kevin JenningsArticle: 128068
Hello all, I am trying to use some of the proposed functions by IEEE which are still awaiting approval. http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/float_pkg_c.vhdl I am getting the following errors **Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(58): Library ieee_proposed not found. ** Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(59): (vcom-1136) Unknown identifier "ieee_proposed". ** Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(60): (vcom-1136) Unknown identifier "ieee_proposed". ** Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(67): VHDL Compiler exiting I have copied the zip file vhdl-200x-pkgs_18 available at http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html. I now have a folder vhdl-200x-pkgs_18 which is the unzipped version. How do I include this as a library? I have renamed the folder to ieee_proposed and it still gives me the same errors. I am using ModelsimPE Student Edition 6.3c ThanksArticle: 128069
KJ a écrit : > On Jan 14, 3:04 pm, Ann <thakkar.an...@gmail.com> wrote: >> I am trying to write a sunction for complex multiplication of 2 >> complex numbers >> >> function complex_multiply(a : signed; b: signed; c : signed; d: >> signed) return signed; >> (a + bi)(c + di) = [ac - bd] + [ad + bc]i. >> >> I am not sure on how I would return the real and imaginary part of the >> result. As per my understanding functions can return only one value. >> How do i represent the inputs and outputs? I want to write code in >> VHDL to be implemented on an FPGA. > > Define a new complex record type... > type t_My_Complex_Type is record > Real: signed; > Imag: signed; > end record; Right, that's cleaner (more readable) than my solution with an array. NicolasArticle: 128070
On Jan 14, 3:34=A0pm, KJ <kkjenni...@sbcglobal.net> wrote:
> On Jan 14, 3:04=A0pm, Ann <thakkar.an...@gmail.com> wrote:
>
> > I am trying to write a sunction for complex multiplication of 2
> > complex numbers
>
> > function complex_multiply(a : signed; b: signed; c : signed; d:
> > signed) return signed;
> > (a + bi)(c + di) =3D [ac - bd] + [ad + bc]i.
>
> > I am not sure on how I would return the real and imaginary part of the
> > result. As per my understanding functions can return only one value.
> > How do i represent the inputs and outputs? I want to write code in
> > VHDL to be implemented on an FPGA.
>
> Define a new complex record type...
> type t_My_Complex_Type is record
> =A0 =A0Real: =A0signed;
> =A0 =A0Imag: signed;
> end record;
>
> Now your function would be defined as
>
> function complex_multiply(a, b : t_My_Complex_Type) return
> t_My_Complex_Type is
> =A0 =A0variable RetVal: t_My_Complex_Type;
> begin
> =A0 RetVal.Real :=3D a.real * b.real - a.imag * b.imag;
> =A0 RetVal.Imag :=3D a.real * b.imag + b.real * a.imag;
> =A0 return(RetVal);
> function complex_multiply;
>
> If you're really feeling gutzy, you can instead call the function
> "*" (with the double quotes) and you'll be defining an override for
> the multiply operator so you could use your function like this...
>
> C <=3D A * B;
>
> instead of
>
> C <=3D complex_multiply(A,B);
>
> But I would suggest getting it working with the new type and seeing
> how that all works first. =A0Record types are synthesizable.
>
> Kevin Jennings
It gave me errors. The result would be twice as long as the lengths of
a or b. So RetVal cannot be of type t_My_Complex_Type. I did the
following and it is compiling fine.
type t_My_Complex_Type is record
Real: signed(31 downto 0);
Imag: signed(31 downto 0);
end record;
type Result_Complex_Type is record
Real: signed(63 downto 0);
Imag: signed(63 downto 0);
end record;
function complex_multiply(a, b : t_My_Complex_Type) return
Result_Complex_Type is
variable RetVal: Result_Complex_Type;
begin
RetVal.Real :=3D a.real * b.real - a.imag * b.imag;
RetVal.Imag :=3D a.real * b.imag + b.real * a.imag;
return(RetVal);
end function complex_multiply;
How do i simulate this? What should be the type of a and b in the
simulation file. Should they be 64 bit vectors each ?
Article: 128071On Jan 14, 1:38=A0pm, Arlet Ottens <usene...@c-scape.nl> wrote: > comp.arch.fpga wrote: > > On 14 Jan., 16:36, FPGA <FPGA.unkn...@gmail.com> wrote: > >> Can anyone give guidelines on how to generate sine and cosine wave in > >> VHDL? > > > You can build a numerical oscillator: > > > Initialization: > > sin[0] =3D 1; > > cos[0] =3D 0; > > > Iteration: > > sin[t] =3D sin[t-1]-cos[t-1]*k; > > cos[t] =3D cos[t-1]+sin[t-1]*k; > > > The Frequency depends on k. If k is 1/2**k you do not even net a > > multiplier. > > > This only works for a continues sequence of values. If you need values > > in random > > order you must use a lookup table or CORDIC. Both are available as > > cores in ISE. > > > Kolja Sulimma > > cronologic ohg > > If you slightly modify the iteration, like this: > > sin[t] =3D sin[t-1] - cos[t-1] * k; > cos[t] =3D cos[t-1] + sin[t] * k; > > then the solution doesn't suffer from accumulating rounding errors, at > the cost of some distortion.- Hide quoted text - > > - Show quoted text - Thanks all for your help.Article: 128072
On Jan 14, 1:53=A0pm, filter...@desinformation.de wrote: > On 14 Jan., 19:02, lm317t <lm3...@gmail.com> wrote: > > > I have heard that FPGA's can have a much larger throughput, dollar per > > dollar, than a special purpose DSP chip because of their parallelism. > > Anyone here have any experience or pointers on this topic? > > What about googling ? > > http://www.google.de/search?hl=3Dde&q=3D%22fpga+vs+dsp%22&meta=3D > > I quess a important difference between FPGA and DSP is programming. > DSP is more for the "procedural" Software Engineer. > FPGA is more for the "parallel" Hardware/Logic design engineer. > > And yes, you may get much more MACs(Multiplyaccumulate/second)/dollar > in a FPGA, but at higher development effort. You dont't write a > procedural signal processing routine then, you design a parallel > running logic circuit and also need to care about timing. Although > utilizing a modern DSP may also get difficult and you have to care > much about pipelining. > > And with a DSP you get lot's of IP already on chip like DMA > Controller, SDRAM interface etc. > With a FPGA you need to do much more than reading the DMA doc and > setting up it's registers to have a SDRAM/DMA interface making use of > the FPGA's power, although there may be also some IP. > > I guess dedicated DSP chips will specialize to niches where they are > surrounded by application specific mixed signal (like A/D) and > specialized circuits (like FLASH) to give a low cost system on chip > solution. > FPGA's with DSP capabilities will take over the high performance more > general purpose DSP maket like for example video processing when the > extra effort in development pays off or IP and development tools > enables it. > > All this for the lower Quantities where it is not covered by ASICS or > Custom IC's. My MS thesis was based on FPGA's which give a very high throughput for compute intensive applications. I designed double precision floating point division and square root units which gave me throughtputs > 100 MFLOPS after pipelining extensively. The sequential version would run with an approx. throughput of 1 MFLOP. It really depends on what your application is.Article: 128073
On Jan 14, 1:53 pm, filter...@desinformation.de wrote: > On 14 Jan., 19:02, lm317t <lm3...@gmail.com> wrote: > > > I have heard that FPGA's can have a much larger throughput, dollar per > > dollar, than a special purpose DSP chip because of their parallelism. > > Anyone here have any experience or pointers on this topic? > > What about googling ? > > http://www.google.de/search?hl=de&q=%22fpga+vs+dsp%22&meta= I did, I wanted to see if anyone here had experience in that field. I had to design fixed point IIR and FIR filters in hardware in a DSP arch class. It was able to run at over 50 MHz. > > I quess a important difference between FPGA and DSP is programming. > DSP is more for the "procedural" Software Engineer. > FPGA is more for the "parallel" Hardware/Logic design engineer. > > And yes, you may get much more MACs(Multiplyaccumulate/second)/dollar > in a FPGA, but at higher development effort. You dont't write a > procedural signal processing routine then, you design a parallel > running logic circuit and also need to care about timing. Although > utilizing a modern DSP may also get difficult and you have to care > much about pipelining. > With the performance per dollar gains, there must be a way to use some of this parallelism in a higher level way that would be useful in DSP applications. > And with a DSP you get lot's of IP already on chip like DMA > Controller, SDRAM interface etc. > With a FPGA you need to do much more than reading the DMA doc and > setting up it's registers to have a SDRAM/DMA interface making use of > the FPGA's power, although there may be also some IP. > How about the ones at opencores.org, I have only used one of their cores, but it did its job. > I guess dedicated DSP chips will specialize to niches where they are > surrounded by application specific mixed signal (like A/D) and > specialized circuits (like FLASH) to give a low cost system on chip > solution. > FPGA's with DSP capabilities will take over the high performance more > general purpose DSP maket like for example video processing when the > extra effort in development pays off or IP and development tools > enables it. > I guess it really boils down to development tools and IP availability. There is just all this parallelism availible in an FPGA. It would be interesting to be able to use it. I guess its just easier to buy a blackfin and use some of the free libraries. > All this for the lower Quantities where it is not covered by ASICS or > Custom IC's. There are quite a few niche markets where I think the dollar gains may be there like in the realm of professional audio and video processing, where there the item sells for large $$ but quantity is less than 2k. I'd have to do some number crunching to see just how much.Article: 128074
FPGA wrote:
> **Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(58):
> Library ieee_proposed not found.
vlib ieee_proposed
vcom -work ieee_proposed somefile.vhd
vcom -work ieee_proposed someotherfile.vhd
...
etc
-- Mike Treseler
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