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> I would like to know if VHDL already has functions defined to generate > Random Numbers. google is your friend :) http://www.velocityreviews.com/forums/t22430-random-number-generator.html > If not, which would be the best algorithm for generating random > numbers for implementation on an FPGA. The answer to this question will depend on the FPGA architecture that you're using, as well as your needs for cryptographic security. This is because, when it comes to pseudo-random number generation, "best" can be subjective. e.g., "best" speed? "best" area? "best" power consumption? "best" random numbers (cryptographically secure)? This is a well-studied area; I recommend that you do some reading to see what suits you ... http://en.wikipedia.org/wiki/Random_number_generator KrisArticle: 128401
jaymode@gmail.com wrote: > I know Xilinx does not officially support anything other than RedHat > Enterprise Linux, yet so many people have installed it on other > versions such as Ubuntu, Gentoo, etc. I am trying to install it on > openSuse 10.3 and am having a very difficult time. The instructions I > have say to run ./setup in the root of the CD. It runs but very > quickly and no error messages are given either. Cd into <EDKDVD>/bin/ > lin and try to run ./setup there and it runs quickly and nothing > happens either. Try running ./_setup and get errors about missing > libraries, so I manually add the path to LD_LIBRARY_PATH. Then try > again and I get errors about the XILINX environment variable not being > set. I have no clue what to set this too and have tried many different > places. Right now I just have it pointing to /opt/Xilinx/. You need to have ISE (or Webpack) installed before you can install EDK. If that is not installed, then install it first. Then point the XILINX variable at that when you are installing EDK.Article: 128402
On Jan 24, 9:28 am, taco <trala...@joepie.nl> wrote: > I'm investigating if the microblaze is an option for a project where > physical space is extremely limited. Perhaps somebody can answer the > following: > 1.Is it possible to use the microblaze in a spartan3E 500? If yes, how much > will it eat from this device? i have a microblaze in a spartan 3e 250 and it takes about 50% > 2.if yes, is it possible to use the microblaze without any other memory > chips (except one serial bootrom) and still running a standalone program > which is not super large and does not need lots of memory? yes. you can run from block ram. you can't include a bunch of libraries (for example, printf won't fit). alan nishioka alan@nishioka.comArticle: 128403
On 24 Jan., 18:54, FPGA <FPGA.unkn...@gmail.com> wrote: > Hello members, > > I would like to know if VHDL already has functions defined to generate > Random Numbers. > > If not, which would be the best algorithm for generating random > numbers for implementation on an FPGA. > > Thank you Hello FPGA, Maybe it's off-topic for you, because you want to implement in FPGA rather than simulating your design, but have you seen this package : http://www.janick.bergeron.com/wtb/packages/random1.vhd ? EdArticle: 128404
On Jan 24, 3:29 pm, jaym wrote: > [...] It runs but very > quickly and no error messages are given either. [...] I had run previous versions of WebPack on Gentoo without too much trouble, but when it came time to replace that distribution I selected Fedora Core 7 hoping things would go even smoother due to its relation with Red Hat. Unfortunately I had the problem with the installation programs quitting without any errors. After searching a lot I found one instruction about changing the configuration for SELinux to allow everything. Doing that did indeed solve the problem. -- JecelArticle: 128405
Hello,
I am now using DeviceReadFrame function on Xilinx EDK9.1 sp2.
But it returns "XST_BUFFER_TOO_SMALL".
According to the reference, it says that Reads one frame from the
device and puts it in the storage buffer.
What is the storage buffer? BRAM?
Please tell me how to solve this.
My environment is an XUP (XC2VP30) board.
--------------------------------------------------------------------------
////////////////////////////////////////
// read Frame
////////////////////////////////////////
Status = XHwIcap_DeviceReadFrame(&HwIcap, XHI_EX_BLOCK,
XHI_EX_MAJOR, XHI_EX_MINOR);
if (Status != XST_SUCCESS)
{
Print("Error : %d \n\r", Status);
return XST_FAILURE;
}
else
{
Print("Data have been read successfully\n\r");
}
---------------------------------------------------------------------------------
Thank you,
Hiroyuki
Article: 128406Hi all, I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything wrong with simply using a pullup to 5V? The speed doesn't matter. Thanks.Article: 128407
fpgauser <nospam@nospam.com> wrote: > Hi all, > I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there > anything wrong with simply using a pullup to 5V? The speed doesn't > matter. The output transistors are not rated for 5 Volt. Look for thre zillions of articles about level translation... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 128408
fpgauser wrote: > Hi all, > > I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything > wrong with simply using a pullup to 5V? The speed doesn't matter. > > > Thanks. Depends - is that 5V device rated with TTL thresholds, or CMOS ones ? A virtex OP will not go to 5V, but an open drain one will pull one diode-clamp above 2.5V, and a TTL pin usually has a span of < 0.8V and > 2.0V, with a typical actual threshold of ~1.3V -jgArticle: 128409
Hi There, I am getting the following error in modelsim when I try to simulate some thing. # Loading C:\Xilinx92i\smartmodel\nt\installed_nt/lib/pcnt.lib/ swiftpli_mti.dll # ** Error: (vsim-3193) Load of "C:\Xilinx92i\smartmodel\nt \installed_nt/lib/pcnt.lib/swiftpli_mti.dll" failed: DLL dependent library not found. # ** Error: (vsim-PLI-3002) Failed to load PLI object file "C: \Xilinx92i\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll". # Region: / I have no idea why this is coming up....any help please! Thanks Kris PS: I am using Modelsim PE and Xilinx ISE.Article: 128410
On Thu, 24 Jan 2008 15:10:32 -0800 (PST), -jg <Jim.Granville@gmail.com> wrote: >fpgauser wrote: >> Hi all, >> >> I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything >> wrong with simply using a pullup to 5V? The speed doesn't matter. >> >> >> Thanks. > >Depends - is that 5V device rated with TTL thresholds, or CMOS ones ? >A virtex OP will not go to 5V, but an open drain one will pull one >diode-clamp >above 2.5V, and a TTL pin usually has a span of < 0.8V and > 2.0V, >with >a typical actual threshold of ~1.3V > >-jg Most 5-volt cmos parts will draw input-stage shoot-through current if the input isn't close to the 5-volt rails. Some 5-volt parts will get quite hot if Vhigh is, say, 3.3. JohnArticle: 128411
hey, there. do you have the IP code for Ultra DMA with FPGA. I am doing the project for this implementation.. hope you would be kind to help. thank you. XiaoXiao -- Message posted using http://www.talkaboutelectronicequipment.com/group/comp.arch.fpga/ More information at http://www.talkaboutelectronicequipment.com/faq.htmlArticle: 128412
Check out: http://toolbox.xilinx.com/docsan/xilinx9/help/platform_studio/html/ps_p_sim_setting_up_modelsim_for_using_smartmodels.htmArticle: 128413
On Jan 24, 1:01 pm, kiransr....@gmail.com wrote: > Hi all, > I want to choose an FPGA for a High speed appliction so which one to > go for either for Xilinx or Altera. > But i am vey much familiar with xilinx devices. > And in the design the gate array will be ineracting with a host PC and > two SRAM and with an HDD > Inside the FPGA two FIFO are to be implemented. > Later on the ASIC of this has to be obtained. > so, kindly help me out in this regard > > Thanks in advance > Kiran I completely agree to Sean, I have used both altera and Xilinx and practically there is not much difference, most of the features and capabilities are same. I would rather base the decision on the support structure and IP/reference design that is available from each of these vendors in your geographic area and work with the one which has the best support. -- GoliArticle: 128414
FPGA wrote: > I would like to know if VHDL already has functions defined to generate > Random Numbers. > If not, which would be the best algorithm for generating random > numbers for implementation on an FPGA. LFSR are pretty popular for random numbers, and very easy to implement in an FPGA. -- glenArticle: 128415
On Jan 25, 10:52 am, Goli <tog...@gmail.com> wrote:
> On Jan 24, 1:01 pm, kiransr....@gmail.com wrote:
>
> > Hi all,
> > I want to choose an FPGA for a High speed appliction so which one to
> > go for either for Xilinx or Altera.
> > But i am vey much familiar with xilinx devices.
> > And in the design the gate array will be ineracting with a host PC and
> > two SRAM and with an HDD
> > Inside the FPGA two FIFO are to be implemented.
> > Later on the ASIC of this has to be obtained.
> > so, kindly help me out in this regard
>
> > Thanks in advance
> > Kiran
>
> I completely agree to Sean, I have used both altera and Xilinx and
> practically there is not much difference, most of the features and
> capabilities are same. I would rather base the decision on the support
> structure and IP/reference design that is available from each of these
> vendors in your geographic area and work with the one which has the
> best support.
>
> --
> Goli
Hi,
Selecting an FPGA for a specific application you may want to answer
this questions yourself
1. Do we have the right expertise (Know how of tool set, FPGA
architecture etc)
2. Does the FPGA have enough slices to support your RTL
3. Does it support all the IO's required (Mostly Altera and Xilinx
supported all the known IO standards)
4. Part availability, pricing and support and maybe cost
5. Required silicon speed, will determine the FPGA speed grade
requirement
6. You may have to account for atleast 60% of routing delay for any
FPGA (Xilinx or Altera) to get the final P&R
frequency estimation. Remember routing plays a major role in the
final frequency achieveable
Rajkumar...
Article: 128416Generally ir won't work because the clamp diode on the I/O will limit the pullup to a diode drop above the 2.5V i.e. circa 3.2V. You could put a series resistor to the I/O and then pullup but you will need to be careful of the values as they will form a potential divider network. but provided the current through the clamp diode is limited it is usually ok. I think Xilinx have one or more applications note on this. Alternatively put a FET, or single gate logic chip, or bus switch in the way as they are nicer ways to achieve the result. You can see lots examples of bus switches used for this function in a number of our products. John Adair Enterpoint Ltd. - Home of Darnaw1. The PGA FPGA Solution. On 24 Jan, 22:58, "fpgauser" <nos...@nospam.com> wrote: > Hi all, > > I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything > wrong with simply using a pullup to 5V? The speed doesn't matter. > > Thanks.Article: 128417
Herbert Kleebauer wrote: > taco wrote: > >> I'm investigating if the microblaze is an option for a project where >> physical space is extremely limited. Perhaps somebody can answer the >> following: >> 1.Is it possible to use the microblaze in a spartan3E 500? If yes, how >> much will it eat from this device? >> 2.if yes, is it possible to use the microblaze without any other memory >> chips (except one serial bootrom) and still running a standalone program >> which is not super large and does not need lots of memory? > > If you need a real small CPU, take a look at > > ftp://137.193.64.130/pub/mproz/mproz3_e.pdf > > Only a few dozen flip-flops and a few hundred gates. Mmm, and only to be programmed in assembler, I assume. Picoblaze is even smaller... Right now I'm running an opencore 8051 which works fine and can be programmed in C, but for the project I'm doing it could be that this runs too slow and cannot handle to dataflow entering a FIFO. microblaze would certainly solve it unless I have to add hardware. Thanks anyway. TacoArticle: 128418
Alan Nishioka wrote: > On Jan 24, 9:28 am, taco <trala...@joepie.nl> wrote: >> I'm investigating if the microblaze is an option for a project where >> physical space is extremely limited. Perhaps somebody can answer the >> following: >> 1.Is it possible to use the microblaze in a spartan3E 500? If yes, how >> much will it eat from this device? > > i have a microblaze in a spartan 3e 250 and it takes about 50% > > >> 2.if yes, is it possible to use the microblaze without any other memory >> chips (except one serial bootrom) and still running a standalone program >> which is not super large and does not need lots of memory? > > yes. you can run from block ram. you can't include a bunch of > libraries (for example, printf won't fit). > > alan nishioka > alan@nishioka.com Thanks a lot, that's exactly what I needed to know. tacoArticle: 128419
Craignell user manual is now available http://www.enterpoint.co.uk/component_replacements/CraignellUserManualIssue1_00.pdf. We also have UCF file available for the CR40 and the other sizes to follow shortly. John Adair Enterpoint Ltd.Article: 128420
Hi all. I am making a design for an IGLOO FPGA from Actel and I have have added a Two Port RAM component in Libero (the development tool). Here I can choose to "Customize RAM Content" and have imported an Intel Hex File. This works perfectly in simulation, but not post-synthesis and layout simulation. Can anyone help me with how I can make this part of the RAM (from address 0 and forward) initialized with the content of my Intel Hex File even after synthesis? If the program does not support this, has anyone experience on how to do/code this in VHDL? The Intel Hex File is generated from a compiler, so I have to read the file in as my compiled design evolves. I can not just hard code it once and for all. Best Regards RgrArticle: 128421
On 25 Jan., 13:47, "Rgr" <rgrwork...@hotmail.com> wrote: > Hi all. > > I am making a design for an IGLOO FPGA from Actel and I have have added a > Two Port RAM component in Libero (the development tool). Here I can choose > to "Customize RAM Content" and have imported an Intel Hex File. > > This works perfectly in simulation, but not post-synthesis and layout > simulation. > > Can anyone help me with how I can make this part of the RAM (from address 0 > and forward) initialized with the content of my Intel Hex File even after > synthesis? > > If the program does not support this, has anyone experience on how to > do/code this in VHDL? > > The Intel Hex File is generated from a compiler, so I have to read the file > in as my compiled design evolves. I can not just hard code it once and for > all. > > Best Regards > Rgr IGLOO does NOT support RAM initialization the init is only provided for simulation, the FPGA itself can not have inited rams AnttiArticle: 128422
Hi, am a little confused as far as the capabilities of the DSP48 go. I would like to implement a 18x35 MACC in (hopefully) only two DSP48. The 18 bit coefficient is a 0.18 fixed point number. I.e. what I really want to implement is ((A18 x B36)>>17)+C48 Apparently I overlooked that the DSP48 slice only allows for common C inputs which means that I can not split C appropriatly accross the two adders. What am I missing? Do I really need to implement the adder in LUTs? Kolja SulimmaArticle: 128423
> Can anyone help me with how I can make this part of the RAM (from address 0 > and forward) initialized with the content of my Intel Hex File even after > synthesis? SRAM blocks in PA3/Fusion/Igloo are initialized via the UJTAG interface or from the design logic. You might find this helpful: http://www.actel.com/documents/Fusion_RAM_FIFO_AN.pdf Although I've never tried, it may be possible to use the Igloo's FlashROM (along with a bit of design logic) to initialize the RAM (although, this may or may not be enough data for what you want to initialize). regards, KrisArticle: 128424
On Jan 25, 1:01=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > FPGA wrote: > > I would like to know if VHDL already has functions defined to generate > > Random Numbers. > > If not, which would be the best algorithm for generating random > > numbers for implementation on an FPGA. > > LFSR are pretty popular for random numbers, and very easy to > implement in an FPGA. > > -- glen I just found out that I need random number generator just for simulation. I do not need to synthesize it. Some feedback on this would be helpful. I am having a look at some of the links posted here. Thanks
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