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On 28 Jan., 21:45, "Maki" <veselic...@eunet.yu> wrote: > >http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf > > > eh, I wanted todo this, so now already instantly feeling better! > > and I do have a smile :) on my face right now. > > Hi Antti, > :) from me. > Is it Actel FPGA on the last page? > > Regards, > -- > M.Veselic > Sigma Lab. YESArticle: 128501
On 28 Jan., 21:34, Ben Jackson <b...@ben.com> wrote: > On 2008-01-28, Antti <Antti.Luk...@googlemail.com> wrote: > > > > >http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf > > ...you got FIRED for missing 3 days of work due to a mixup in vacation > scheduling? =A0Wow. > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/ Yes Ben, got fired in such way that I "earned" additional 3 months jobless aid penalty (i.e. nothing paid) At the moment when i got fired i had 27 unused vaccation days, lost them as well. but a :) smile can help, I have had some time to think about organizing my past projects (not yet doing it, its way too much)... AnttiArticle: 128502
Symon wrote: > Please let us know how you resolve this, I've used this on designs also. > ISTR I usually lie to it about the bank's VCCO. OK, my bad, I take everything back. The line setting the magical environment variable PL_NO_SIO_DRC=1 was commented out in my synthesis script. So ISE was complaining about the DIFF_TERM-issue, just like before, not because of LVDS-IOs mixed with LVTTL-IOs. Still, the error message you get doesn't say anything about DIFF_TERM, just that LVDS inputs and LVTTL outputs cannot be mixed, which is a bit misleading... But I found something new originating from changing documentation... I use some ISERDES-primitives as well, in NETWORKING-mode. Turns out that since ISE9.2 you can only use NETWORKING mode if you enable the bitslip mode (see AR #25507), otherwise you have to use MEMORY-mode. So I now have a design that runs through ISE8.2 without warnings, and fails in ISE9.2. Works perfectly on the hardware, i.e. "real life". *IF* I can get it to finish synthesizing, that is :) cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 128503
>> >http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf >> >> > eh, I wanted todo this, so now already instantly feeling better! >> > and I do have a smile :) on my face right now. >> >> Hi Antti, >> :) from me. >> Is it Actel FPGA on the last page? >> >> Regards, >> -- >> M.Veselic >> Sigma Lab. > > YES It must be Fusion. I've never seen pricing for this family. The board is very cheap... Regards, -- M.Veselic Sigma LabArticle: 128504
Has anyone succesfully used Aldec Active HDL 7.3 (web-eval) with a (Verilog) Smartmodel simulation? I'm using Xilinx Webpack 9.2i.04 (IP-Update#2), and I separately downloaded and installed the Aldec Verilog library-update for 9.2i.04. In Coregen 9.2i.04 (IPUpdate#2), I created a Verilog Virtex5/LXT50 TEMAC. I compiled the core-generated testbench, then added it to my Aldec design-space. I followed the directions at http://support.aldec.com/KnowledgeBase/Article.aspx?aid=000713 I can compile everything successfully, but when i goto initialize simulation, it fails: # : SWIFT: Session terminated. # PLI: SWIFT: Template TEMAC_SWIFT_lmtv not found in SmartModel Library!!!: $lm_model (0) # RUNTIME: RUNTIME_0068 $finish called. # KERNEL: Time: 0 ps, Iteration: 0, Instance: /testbench/dut/v5_emac_ll/v5_emac_block/v5_emac_wrapper/v5_emac/temac_swift_1/I1, Process: #INTERNAL#0_391. I've double-checked to make sure Smartmodel-library was installed correctly, I recompiled the swift_lmtv.dll -- basically I tried everything I could think of, but it doesn't work. I tried a different simulation-design -- RocketIO GTP (from Xilinx core-generator) It fails the same way: # PLI: SWIFT: Template GTP_DUAL_SWIFT_lmtv not found in SmartModel Library!!!: $lm_model (0 similar failure. Here's a more complete logfile: asim -pli "$aldec\BIN\swift.dll" -pli "$aldec\BIN\swift_lmtv.dll" -pli "C:\Xilinx92i\smartmodel\nt\installed_nt\lib\pcnt.lib\swiftpli.dll" -advdataflow -L ovi_simprim -L ovi_unisim -L ovi_xilinxcorelib glbl testbench # ELBREAD: Elaboration process. # ELBREAD: Elaboration time 0.0 [s]. # asim: Stack memory: 32MB # asim: Retval memory: 32MB # KERNEL: Main thread initiated. # KERNEL: Kernel process initialization phase. # KERNEL: Time resolution set to 1ps. # ELAB2: Elaboration final pass... # KERNEL: PLI/VHPI kernel's engine initialization done. # PLI: Loading library 'C:\Program Files\Aldec\Active-HDL 7.3\bin/systf.dll' # PLI: Loading library 'C:\Program Files\Aldec\Active-HDL 7.3\BIN\swift.dll' # PLI: Loading library 'C:\Program Files\Aldec\Active-HDL 7.3\BIN\swift_lmtv.dll' # ELAB2: Create instances ... # ELAB2: Create instances complete. # ELAB2: Elaboration final pass complete - time: 0.1 [s]. # KERNEL: Kernel process initialization done. # Allocation: Simulator allocated 4394 kB (elbread=2054 elab2=1973 kernel=367 sdf=0) # : SWIFT: Beginning the session. # : Copyright (c) 1984-2008 Synopsys Inc. ALL RIGHTS RESERVED # : You can use the Browser tool to configure the SmartModel # : Library and access information about SmartModels: # : $LMC_HOME/bin/sl_browser # : # : SmartModel product documentation is available here: # : $LMC_HOME/doc/smartmodel/manuals/intro.pdf # : http://www.synopsys.com/products/lm/doc/smartmodel.html # : # : SWIFT: Session terminated. # PLI: SWIFT: Template TEMAC_SWIFT_lmtv not found in SmartModel Library!!!: $lm_model (0) # RUNTIME: RUNTIME_0068 $finish called. # KERNEL: Time: 0 ps, Iteration: 0, Instance: /testbench/dut/v5_emac_ll/v5_emac_block/v5_emac_wrapper/v5_emac/temac_swift_1/I1, Process: #INTERNAL#0_391. # KERNEL: ASDB file was created in location c:\temp\coregen\v5_emac_v1_3\simulation\temac\temac\src\wave.asdb # 11:47 PM, Monday, January 28, 2008 # Simulation has been initialized # Selected Top-Level: glbl testbenchArticle: 128505
On Jan 28, 2:52 pm, "chaitanyakurm...@gmail.com" <chaitanyakurm...@gmail.com> wrote: > i need the equivalent Xilinx FPGA for the following altera devices. > > - Altera Stratix II GX-60 > > - Altera Stratix II GX-90 > > in terms of the resources available in these devices (logic, block > ram, dcms, global clock etc) with those available in Xilinx FPGAs. > > thanks Hi, It is very difficult to get a full feature to feature compatible device in both families. Both companies have different kind of resources, for Xilinx has 18Kbits size block RAMs, whereas Altera has 512bits and 4k bits block RAMs. But the rough way to compare is to compare the LUTs, i.e. four input Logic elements. Both the vendors give their FPGA logic capability in terms of equivalent Logic Elements. GX-60 has about 60K LEs, so you could think of using Virtex5, LX50T, which would have about 50K LEs, Similarly for GX-90 (90K LEs) you can take a look at Virtex5 LX85T (~85K LEs) -- GoliArticle: 128506
>
> > -- glen
>
> I just found out that I need random number generator just for
> simulation. I do not need to synthesize it. Some feedback on this
> would be helpful. I am having a look at some of the links posted here.
>
> Thanks
The math_real package has a random number function in it, uniform. It
generates reals between 0 and 1. you can use this to easily generate
an integer, which can then be converted to anything.
I created this function specifically for testbenches:
--min and max can be swapped quite happily
procedure rand_int( variable seed1, seed2 : inout positive;
min, max : in integer;
result : out integer) is
variable rand : real;
begin
uniform(seed1, seed2, rand);
result := integer(real(min) + (rand * (real(max)-real(min)) ) );
end procedure;
Article: 128507
On Tue, 29 Jan 2008 02:23:35 -0800 (PST),
Tricky <Trickyhead@gmail.com> wrote:
>I created this function specifically for testbenches:
>
>--min and max can be swapped quite happily
>procedure rand_int( variable seed1, seed2 : inout positive;
> min, max : in integer;
> result : out integer) is
> variable rand : real;
>begin
> uniform(seed1, seed2, rand);
> result := integer(real(min) + (rand * (real(max)-real(min)) ) );
>end procedure;
Ahem... if you'd read my correction to my own post, you
might have spotted that this is in fact wrong...
Your function's probability of getting exactly "max"
or "min" is only half the probability of getting any
other values in the range. To see why, consider this:
max = 3, min = 0
So real(max) - real(min) = 3.0
and rand is in the range 0.0 ... 1.0 (not quite 1.0)
so rand*(real(max)-real(min)) is in range 0.0 ... 3.0
The conversion integer(some_real) rounds to the nearest whole
number, so...
0.0 .... 0.5 rounds to 0
0.5 .... 1.5 rounds to 1
1.5 .... 2.5 rounds to 2
2.5 .... 3.0 rounds to 3
Clearly the integers 0 and 3 have only a "width" of 0.5,
whereas all the other values have a "width" of 1.0 and
thus the edge values have only half the probability.
My solution yields a uniform integer distribution.
Note also that I used "floor()" from math_real to
be sure that there's no risk of getting (max+1).
Getting these probability distribution things just
right is often quite a bit of work. That's why I
and many others are unimpressed with the argument
that "VHDL random generation is just as good as
SystemVerilog's constraint solver because you can
write whatever you need in VHDL". The better
solution to this problem, surely, is...
rand int N;
constraint N_uniform { N inside {[min:max]}; }
or whatever is the right syntax in your chosen
testbench automation language. Traditional
procedural languages just don't cut it for
smart randomization.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 128508Guys, I saw this and thought of you... http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=1196&view=by_date_ascending&page=1 HTH., Syms.Article: 128509
BigJamesLau@gmail.com pisze:
> here is my codes. I want to verify the result and display at the end,
> however I got like "cdcd", what's wrong? thanks
>
>
> /*
> * "Hello World" example.
> *
> * This example prints 'Hello from Nios II' to the STDOUT stream. It
> runs on
> * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost'
> example
> * designs. It runs with or without the MicroC/OS-II RTOS and requires
> a STDOUT
> * device in your system's hardware.
> * The memory footprint of this hosted application is ~69 kbytes by
> default
> * using the standard reference design.
> *
> * For a reduced footprint version of this template, and an
> explanation of how
> * to reduce the memory footprint for a given application, see the
> * "small_hello_world" template.
> *
> */
>
> #include <stdio.h>
> #include <stdlib.h>
> #include <sys/alt_dma.h>
> #include "system.h"
>
> static volatile int rx_done = 0;
>
> /*
> * Callback function that obtains notification that the data has
> * been received.
> */
> static void done (void* handle, void* data)
> {
> rx_done++;
> }
>
> int main(int argc, char* argv[], char* envp[])
> {
> int rc;
> static char buff[256]="abcdefghijklmn\0";
> alt_dma_txchan txchan;
> alt_dma_rxchan rxchan;
>
> void* tx_data = (void*) buff; /* pointer to data to
> send */
> void* rx_buffer = (void*) 0x01000000; /* on_chip_memory addr*/
>
>
> /* Create the transmit channel */
> if ((txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL)
> {
> printf ("Failed to open transmit channel\n");
> exit (1);
> }
>
> /* Create the receive channel */
> if ((rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL)
> {
> printf ("Failed to open receive channel\n");
> exit (1);
> }
>
> /* Post the transmit request */
> if ((rc = alt_dma_txchan_send (txchan,tx_data,128,NULL,NULL)) < 0)
> {
> printf ("Failed to post transmit request, reason = %i\n", rc);
> exit (1);
> }
>
> /* Post the receive request */
> if ((rc = alt_dma_rxchan_prepare (rxchan,rx_buffer,128,done,NULL)) <
> 0)
> {
> printf ("Failed to post read request, reason = %i\n", rc);
> exit (1);
> }
>
> /* wait for transfer to complete */
> while (!rx_done);
> printf ("Transfer successful!\n");
> printf ("%s",(ONCHIP_MEMORY_0_BASE));
> return 0;
> }
What is set in system configuration ?
Adam
Article: 128510On Jan 29, 3:08 am, Goli <tog...@gmail.com> wrote: > On Jan 28, 2:52 pm, "chaitanyakurm...@gmail.com" > > <chaitanyakurm...@gmail.com> wrote: > > i need the equivalent Xilinx FPGA for the following altera devices. > > > - Altera Stratix II GX-60 > > > - Altera Stratix II GX-90 > > > in terms of the resources available in these devices (logic, block > > ram, dcms, global clock etc) with those available in Xilinx FPGAs. > > > thanks > > Hi, > > It is very difficult to get a full feature to feature compatible > device in both families. Both companies have different kind of > resources, for Xilinx has 18Kbits size block RAMs, whereas Altera has > 512bits and 4k bits block RAMs. > > But the rough way to compare is to compare the LUTs, i.e. four input > Logic elements. Both the vendors give their FPGA logic capability in > terms of equivalent Logic Elements. > > GX-60 has about 60K LEs, so you could think of using Virtex5, LX50T, > which would have about 50K LEs, > > Similarly for GX-90 (90K LEs) you can take a look at Virtex5 LX85T > (~85K LEs) > > -- > Goli But watch out for inflated "logic element" count in Xilinx where the actual number of LUTs is smaller. For V5, however you'll probably need to port your design to see how it fares because of the LUT6 vs LUT4 size factor. If you have a lot of paths with multiple levels of logic, the LUT6 can help with speed as well as logic element reduction.Article: 128511
On Jan 29, 6:51 am, "Symon" <symon_bre...@hotmail.com> wrote: > Guys, > I saw this and thought of you...http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=11... > HTH., Syms. There was another thread on this... http://forums.xilinx.com/xlnx/board/message?board.id=ISE&message.id=1034&query.id=19234#M1034Article: 128512
On Tue, 29 Jan 2008 11:51:45 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >Guys, >I saw this and thought of you... >http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=1196&view=by_date_ascending&page=1 >HTH., Syms. In your opinion, how are the Xilinx forums shaping up as a useful tool for exchanging information? - BrianArticle: 128513
"Gabor" <gabor@alacron.com> wrote in message news:4cdc9cd9-6b63-4288-bbe0-4999da9a6686@l1g2000hsa.googlegroups.com... > On Jan 29, 6:51 am, "Symon" <symon_bre...@hotmail.com> wrote: >> Guys, >> I saw this and thought of >> you...http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=11... >> HTH., Syms. > > There was another thread on this... > > http://forums.xilinx.com/xlnx/board/message?board.id=ISE&message.id=1034&query.id=19234#M1034 Looks like the latest AVG update fixes the problem.Article: 128514
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:s6fup350dvj91v096p3hrdtbj1qa2015ka@4ax.com... > On Tue, 29 Jan 2008 11:51:45 -0000, "Symon" <symon_brewer@hotmail.com> > wrote: > >>Guys, >>I saw this and thought of you... >>http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=1196&view=by_date_ascending&page=1 >>HTH., Syms. > > In your opinion, how are the Xilinx forums shaping up as a useful tool for > exchanging information? > > - Brian Hi Brian, No idea, I only went there because it was the solitary hit for 'Downloader.Swizzor xilinx'! Cheers, Syms.Article: 128515
Can anyone point me to a sight with HDLC schematic or drawings? ThanksArticle: 128516
Hi John, John McCaskill wrote: > On Jan 28, 5:52 pm, Michael Laajanen <michael_laaja...@yahoo.com> > wrote: >> Hi, >> >> >> >> talkb wrote: >>> "John McCaskill" <jhmccask...@gmail.com> wrote in message >>> news:aa864ccf-655f-445e-9a68-a25979acbdc2@v67g2000hse.googlegroups.com... <sniP> >> Xilinx works with VCS-MX also and probably all decent simulatorns on all >> platforms, we use it on AMDs running Solaris 10 where Xilinx is not >> supported, see below for supported simulators on Sparc Solaris 10! >> >> edaadm@brera $ compxlib -help sim >> Release 9.2.04i - COMPXLIB J.40 >> Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. >> >> -s <simulator> : Specify the name of the simulator for which the libraries >> are to be compiled. The valid simulator names are :- >> >> mti_se mti_pe vcs_mx vcs_mxi ncsim >> >> Also compiling is trivial in Verilog(just compile it), and in VHDL >> Xilinx has supplied a file named vhdl_analyze_order in the >> $XILINX/vhdl/src/XilinxCoreLib directory. >> >> /michael > > The OP asked what EDK supports, compxlib is part of ISE, not EDK. I > am currently using EDK/ISE 8.1 8.2 and 9.1, and I see that ISE does > support vcs, but EDK does not. I also use ModelSim but not Cadence. > Ops, my misstake! > When I say that EDK supports ModelSim and Cadence, I mean two things. > > 1. For those simulators the SimGen tool will generate setup scripts > for you from your EDK project that let you launch the simulator, > compile the project, setup the display windows, and run the > simulation. I think that this is a very nice feature, but if you > prefer another simulator, you can of course do this yourself. > > 2. Xilinx presumably does quality assurance testing against the > simulators that they say are supported, and will provide help if you > have problems. To me this is the critical point. > > At least for ModelSim, Xilinx is very specific about which versions > they support. In the case of EDK 8.2, they specify one specific > release of ModelSim as the only supported version. We have tried > running with other versions with mixed results. When we used the > supported version, our test benches passed and matched what we saw in > hardware. When we used other versions, some times we got the same > results, some times we did not. You are ofcourse right. My experience with simulator versions not working is often connected to improper code in the libraries which some tools ignores or interpret it as they like, just like syntheses tools for some vendors. I have run lint tools on many of these libraries and they are not that well written, my experience is that unless one "relaxes" the compiler it usually works. And when filed a bug, the respons can often be "not supported simulator/version) although the code is not correct, that pisses me off alot (: But then again, if you want a easy supported tool chain, the "builtin" is the way to go just like you say. regards MichaelArticle: 128517
"George" <romans5_8@earthlink.net> wrote in message news:13puheg9o1tgl0e@corp.supernews.com... > Can anyone point me to a sight with HDLC schematic or drawings? > Not sure about a schematics version but there is an HDL version on opencores: http://www.opencores.org/projects.cgi/web/hdlc/overview Hans www.ht-lab.com > ThanksArticle: 128518
You have to load only one PLI library when you start simulation. In your case you only need swift_lmtv.dll. The latter has internal reference to the either libswift.dll or lmtv.dll that you have built in Xilinx. Xilinx LMC_HOME variable has to point to the smartmodels installation directory (Xilinx\smartmodel\nt\installed_nt) for libswift/lmtv to be found. There is a nice tool to check dependencies inside your dll file. You can get it from www.dependencywalker.com. Check if you have any links broken in your swift_lmtv.dll.Article: 128519
On 28 Jan., 23:43, Kevin Neilson <kevin_neil...@removethiscomcast.net> wrote: > comp.arch.fpga wrote: > > Hi, > > > am a little confused as far as the capabilities of the DSP48 go. > > I would like to implement a 18x35 MACC in (hopefully) only two DSP48. > > The 18 bit coefficient is a 0.18 fixed point number. I.e. what I > > really want > > to implement is > > ((A18 x B36)>>17)+C48 > > > Apparently I overlooked that the DSP48 slice only allows for common C > > inputs > > which means that I can not split C appropriatly accross the two > > adders. > > > What am I missing? Do I really need to implement the adder in LUTs? > > > Kolja Sulimma > > Kolja, > You can easily make an 18x85 multiplier with two DSP48s (see fig 1-20 of > http://www.xilinx.com/bvdocs/userguides/ug073.pdf) but to do an > accumulation you will have to add a third DSP48, using it only as an > accumulator. (I wouldn't do this in fabric. See fig. 5-2 of the same > doc to see the concept used in a semiparallel FIR.) You could do it in > two DSP48s if you can spare a cycle, for example, when it's time to > clear the accumulator. This is done by doing separate > multiply-accumulates on the MSB and LSB DSP48s, and then at the end of > the accumulation period, on the spare cycle, summing the two together by > changing the opcode mux. > -Kevin Hi, thanks for that. It got crowded in the chip so I kept banging my head against the user guide schematics and came up with the following. To compute A18*B35 + C35 I chain two DSP48 to form a 18x35 multiplier. Then I set C48 <= C(29 downto 0) << 17; and use it as the Z input to the lower DSPs adder. The remaining 6 bits need to be added in fabric. With a simple retiming step I can even use the PREG of the upper DSP slice. I understand that there are not enough routing ressources to have to independant C inputs, but as AxB+C is a common function, maybe support for this could be added to the next generation of the DSP slice? All that is needed is an additional mux to split the C input between the two slices. (actually not even that, all is needed are seperate controls for parts of the existing muxes, so the critical path does not get slower.) Kolja SulimmaArticle: 128520
On 2007=B3=E212=BF=F913=C0=CF, =BF=C0=C0=FC12=BD=C346=BA=D0, "koce" <bojan_1= ...@yahoo.com> wrote: > Can U, please, send me a byteblasterII schematic file if U have it. > Thank U! > Bojan > > -- > Message posted usinghttp://www.talkaboutelectronicequipment.com/group/comp= .arch.fpga/ > More information athttp://www.talkaboutelectronicequipment.com/faq.html Hello You can get very low cost ByteBlaster II at http://fpgaguy.110mb.com It is only $36.95. You do not need to make byteblaster II. Save your time and money.Article: 128521
On Jan 28, 11:16 pm, "talkb" <no...@talkb.com> wrote: > "John McCaskill" <jhmccask...@gmail.com> wrote in message > > news:aa864ccf-655f-445e-9a68-a25979acbdc2@v67g2000hse.googlegroups.com... > > > You can use Smartmodels with ModelSim PE, you just need to get a > > license for it. Look in the license file on the computer that you used > > to see if it had a license. I use ModelSim PE with extra license for > > Smartmodels, mixed language support, and code coverage. Even with > > getting the extra licenses PE was much cheaper than SE. Most of the > > difference is because of using a dongle instead of a floating license. > > SE comes standard with a floating license. > > Ok, I double-checked our license-server's license.dat file. > The commented section indicated our company is licensed for "Modelsim-PE > Plus" > > As far as I can tell, the actual license-increments are just 2 items: > 1) msimpevlog (Verilog) > 2) msimpe (VHDL) > > Nothing else 'special' in the license-file. Perhaps Modelsim allows a > Verilog+VHDL combo license to subsitute for a Smartmodel license? As luck would have it I just got a call from someone at Mentor Graphics so I asked them about this. What they told me is that if you are using only Verilog in your design, you do not need the extra license for Smartmodels. If you are using any VHDL, you do need the license. When I asked why, they said that they would have to ask someone else and get back to me. Regards, John McCaskill www.FasterTechnology.comArticle: 128522
BigJamesLau@gmail.com wrote: > here is my codes. I want to verify the result and display at the end, > however I got like "cdcd", what's wrong? thanks You need to ensure that the memory involved in the transfer is not cached - you can simply set bit 31 of the address to bypass the NIOS cache. I use a macro thusly: #define UNCACHED(addr) ((1<<31)|(addr)) What's the width on your DMA register? Not 7 bits I hope! :O You also use 0x01000000 for the rx_buffer yet you're printing the contents of INCHIP_MEMORY_0_BASE, which IMHO is bad practise. Otherwise it looks OK to me... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 128523
comp.arch.fpga wrote: > On 28 Jan., 23:43, Kevin Neilson <kevin_neil...@removethiscomcast.net> > wrote: >> comp.arch.fpga wrote: >>> Hi, >>> am a little confused as far as the capabilities of the DSP48 go. >>> I would like to implement a 18x35 MACC in (hopefully) only two DSP48. >>> The 18 bit coefficient is a 0.18 fixed point number. I.e. what I >>> really want >>> to implement is >>> ((A18 x B36)>>17)+C48 >>> Apparently I overlooked that the DSP48 slice only allows for common C >>> inputs >>> which means that I can not split C appropriatly accross the two >>> adders. >>> What am I missing? Do I really need to implement the adder in LUTs? >>> Kolja Sulimma >> Kolja, >> You can easily make an 18x85 multiplier with two DSP48s (see fig 1-20 of >> http://www.xilinx.com/bvdocs/userguides/ug073.pdf) but to do an >> accumulation you will have to add a third DSP48, using it only as an >> accumulator. (I wouldn't do this in fabric. See fig. 5-2 of the same >> doc to see the concept used in a semiparallel FIR.) You could do it in >> two DSP48s if you can spare a cycle, for example, when it's time to >> clear the accumulator. This is done by doing separate >> multiply-accumulates on the MSB and LSB DSP48s, and then at the end of >> the accumulation period, on the spare cycle, summing the two together by >> changing the opcode mux. >> -Kevin > > Hi, thanks for that. > It got crowded in the chip so I kept banging my head against the user > guide schematics > and came up with the following. To compute A18*B35 + C35 I chain two > DSP48 to form > a 18x35 multiplier. Then I set > C48 <= C(29 downto 0) << 17; > and use it as the Z input to the lower DSPs adder. > The remaining 6 bits need to be added in fabric. With a simple > retiming step I can even use the > PREG of the upper DSP slice. > > I understand that there are not enough routing ressources to have to > independant C inputs, but as > AxB+C is a common function, maybe support for this could be added to > the next generation of the DSP slice? > All that is needed is an additional mux to split the C input between > the two slices. > (actually not even that, all is needed are seperate controls for parts > of the existing muxes, so the critical > path does not get slower.) > > Kolja Sulimma > Kolja, I'm not sure exactly what you are describing. You could take the 30 bits from the upper (msb) slice's P output and leftshift 17 bits and route them to the C input so they can be summed with AxB from the lower slice, but then you still can't accumulate. When you multiply, you have to use both the X and Y muxes for the multiplier's partial sums, so then you are left with the Z mux, which you can use to add in either C, PCIN, or P. So you can't multiply, accumulate, and add in a third thing at the same time. I'm not sure what you mean by your suggestion about the mux to split the C between the two slices. The C input already goes to both slices. (By the way, the DSP48E in the V5 has independent C inputs for each slice. And it does a 25x18 multiply.) -KevinArticle: 128524
Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.1.3. This current version is built against GTK 2.12.6 so you'll need to get the libs.tar.gz. The new GTK fixes a problem which happens with Vista. http://www.dspia.com/gtkwave.html
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