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Le Fri, 04 Jan 2008 11:51:56 +0100, Arlet Ottens a écrit: > Andreas Ehliar wrote: >> On 2008-01-03, Arlet Ottens <usenet+5@c-scape.nl> wrote: >>> Habib Bouaziz-Viallet wrote: >>>> always @(posedge clk) >>>> begin >>>> out<=out+1; >>>> if (reset==1) >>>> out[7:0] <= 0; >>>> else if(load==1) >>>> out[7:0] <= in[7:0]; >>>> end >>> You're doing two assignments to 'out' in the same clock cycle. >> >> Doing more than one assignment to a signal is allowed for >> synthesizable code, both in Verilog and VHDL. The last assignment >> in the process block takes precedence. (This assumes that >> all assignments are done in the same process, if not you >> will have a whole bunch of problems...) > > I didn't know that.. Thanks. > > I noticed it synthesized OK, but I assumed the behavior would be > unspecified. Hey what makes you think that the behaviour would be unspecified ? -- HBVArticle: 127626
On Jan 4, 1:42 am, Gabor <ga...@alacron.com> wrote: > On Jan 3, 10:28 am, "MJ Pearson" <mjp...@york.ac.uk> wrote: > > > > > Hello, > > > I've some issues hooking up some external components (camera link based > > cameras) to my XUPV2P board. I've built a PCB which connects the high > > speed expansion port of the XUPV2P to the outputs of the National Chip > > DS90CR288A. I've two cameras running simultaneously, so thats two chips on > > the PCB. > > > On the high speed expansion port of the XUPV2P there's a clock input, but > > because I've got two external clocks (one from each chip), I decided to > > attach them to the 'regular' FPGA pins. Sorry if this makes no sense! The > > other high speed expansion port connections are connected to the data > > signals, and data-valid signals from the chips. > > > I've created a peripheral which samples the camera data according to these > > clock signals, and then sampled again using the Bus2IP clock. I use a > > microblaze processor just to output various data. On the scope, my clock > > signals seem to have a period of 16ns, is this too fast for what I want to > > do? The voltage swing is about 600mV. My design doesn't seem to be working! > > Just wondered if anyone had any suggestions comments on how best to debug > > and proceed. > > I would first check that the clocks are being received properly by > the V2P. Add a T flip-flop on each input clock and drive it to an > I/O or LED that is easy to scope. Check that the frequency is > 1/2 of the input frequency and that you don't get runt pulses or > other undesired behavior. > > If your two input clocks are running O.K., but your data capture is > not consistent, it is possible to run standard (non-GCLK) inputs > to a DCM to adjust the clock phase. You might need to set an > environment variable to force ISE to do this depending on the version > of ISE you run. On my system I set: > XIL_MAP_ALLOW_ANY_DLL_INPUT = 1 > But that was for a very old version of Foundation, so you may not > need this. > > I'm not sure what you mean by sampling the camera data according > to these clock signals, and then sampled again using the Bus2IP > clock. I would think you need to use a FIFO to move from the > camera clocks to the Bus2IP clock. Camera Link places a LVAL > signal on each of the Channel-Links, so you can generate a > FIFO write signal for each link independently using its own > clock. > > Hope this helps, > Gabor Gabor, Which camera are you using ? What is the source of this 16ns clock period ? (Probably from a camera with pixel clock frequency of 60Mhz) If it is pixel clock from a camera and the voltage swing is about 600mV, then I am afraid that the fault lies in your custom PCB. Did you perform impedance matching for the tracks from high speed edge connector to DS90288 Chip ? Have you used appropriate termination resistance to differential lines ? What is the distance between the chip (DS90288) and edge connector ? What is the status of power save mode pin on DS90288 Chip ? In my experience, FVAL, LVAL and clock signals are extremely stable signals from the output of camera. And voltage swing of clock is very appropriate. Try using chipscope pro to observe input signals to FPGA and perhaps by exporting to data to a text file and using matlab try to display resulting image. Hope this helps. /MHArticle: 127627
Habib Bouaziz-Viallet wrote:
> Le Fri, 04 Jan 2008 11:51:56 +0100, Arlet Ottens a écrit:
>
>> Andreas Ehliar wrote:
>>> On 2008-01-03, Arlet Ottens <usenet+5@c-scape.nl> wrote:
>>>> Habib Bouaziz-Viallet wrote:
>>>>> always @(posedge clk)
>>>>> begin
>>>>> out<=out+1;
>>>>> if (reset==1)
>>>>> out[7:0] <= 0;
>>>>> else if(load==1)
>>>>> out[7:0] <= in[7:0];
>>>>> end
>>>> You're doing two assignments to 'out' in the same clock cycle.
>>> Doing more than one assignment to a signal is allowed for
>>> synthesizable code, both in Verilog and VHDL. The last assignment
>>> in the process block takes precedence. (This assumes that
>>> all assignments are done in the same process, if not you
>>> will have a whole bunch of problems...)
>> I didn't know that.. Thanks.
>>
>> I noticed it synthesized OK, but I assumed the behavior would be
>> unspecified.
>
> Hey what makes you think that the behaviour would be unspecified ?
That's just what I had assumed. It is actually specified to take the
last one, like Andreas said, so your original code works as intended.
Still, you may prefer to make the priority encoding explicit by putting
the "out <= out + 1" assignment in an "else" branch. That way, you won't
be tempted to write something like:
out <= out + 1;
if( condition )
out <= out + 1;
Article: 127628
>...in one of the connectors the wires were off by one. So only one
>line of my diff pair was actually connected...
Interestingly, it's possible to get this wrong even with the cable
wired correctly (and no tracking mistake at either end).
Recently, I saw a 20-way cable where each end had the same type of
connector and a multimeter confirmed this wiring:
A01---B20
A02---B19
A03---B18
:
:
:
A19---B02
A20---B01
My first thought was "this cable is symmetrical - it doesn't matter
which way round I connect it".
But it turned out that (for example):
the wiring from A08/A09 to B13/B12 is a twisted pair
the wiring from B08/B09 to A13/A12 is not
So, the cable was reversible mechanically and for DC, but not for AC.
One connector had a cryptic label which just read BOARD. Maybe the
designer should have used two different connectors (or arranged the
twisted pairs symmetrically). I hope he isn't designing cables for
use in aircraft.
Mike
Article: 127629
I havw writtent the following code. It compiles correctly. When i run
the simulation it just stops and points to this statement
variable result : unsigned(bw-1 downto 0);
The code and test bench are as below
-- VHDL library declarations
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- entity declaration
entity floor_top is
generic ( bwin : integer:= 6; bwout : integer := 3);
port(
x : IN unsigned(bwin-1 downto 0);
bw : IN integer;
y : OUT unsigned(bwout-1 downto 0)
);
END floor_top;
-- architecture declaration
architecture behavioral of floor_top is
-- function declaration
function floor( x: unsigned; bw: integer) return unsigned is
variable result : unsigned(bw-1 downto 0);
begin
result := resize(x,bw);
return result;
end floor;
begin
y <= floor(x,bw);
end behavioral;
test bench is as follows =>
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY util_tb IS
-- testbench entity is ALWAYS EMPTY
END util_tb;
ARCHITECTURE tb OF util_tb IS
-- local signal declaration
SIGNAL x : unsigned(5 downto 0) ;
SIGNAL bw : integer;
SIGNAL y : unsigned(2 DOWNTO 0);
-- component declaration
COMPONENT floor_top IS
generic ( bwin : integer:= 6; bwout : integer := 3);
port(
x : IN unsigned(bwin-1 downto 0);
bw : IN integer;
y : OUT unsigned(bwout-1 downto 0)
);
END COMPONENT;
BEGIN
UUT : floor_top
PORT MAP(
x => x,
bw => bw,
y => y
);
-- apply inputs to monitor outputs
x <= "101101" AFTER 0 ns,
"001001" AFTER 15 ns,
"111001" AFTER 25 ns;
bw <= 3 AFTER 0 ns;
END tb;
Article: 127630Nico Coesel <nico@puntnl.niks> wrote: > "Pat Magnits" <Pat@Magnits.com> wrote: > >Hi, > > > >Am far from being an expert in fpga usage and programming, I was wondering > >if there exists any ip cores out there that would allow the use of > >ethernet interfaces on recent FPGAs. For instance say that I have a > >rather important bandwidth (500Mb/s) and that I want to send that > >over the Gigabit interface of a Virtex 5 in UDP frames. Is there > >any blackbox concept IP Core that would allow me to do that without > >having to learn about UDP frame and TCP > >and the use of the Xilinx ethernet MAC usage etc etc ? > Sending UDP packets is rather straightforward. Look here: > http://www.fpga4fun.com/10BASE-T.html 10base-t and Gigabit ethernet have different implementation difficulty levels ;-) FPGA, uC-Core and Gigabit is being done. Look at the Leon or the USRP2/Gnuradio effort. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 127631
On Jan 4, 8:10=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > I havw writtent the following code. It compiles correctly. When i run > the simulation it just stops and points to this statement > variable result =A0 : =A0 unsigned(bw-1 downto 0); > > The code and test bench are as below > -- VHDL library declarations > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.all; > use ieee.numeric_std.all; > > -- entity declaration > entity floor_top is > generic ( bwin : integer:=3D 6; bwout : integer :=3D 3); > port( > =A0 =A0 =A0 =A0 x =A0 : =A0 IN unsigned(bwin-1 downto 0); > =A0 =A0 =A0 =A0 bw =A0: =A0 IN integer; > =A0 =A0 =A0 =A0 =A0 =A0 =A0y =A0 : =A0 OUT unsigned(bwout-1 downto 0) > =A0 =A0 ); > END floor_top; > > -- architecture declaration > architecture behavioral of floor_top is > > =A0 =A0-- function declaration > =A0 =A0function floor( x: unsigned; bw: integer) return unsigned is > =A0 =A0 =A0 variable result =A0 : =A0 unsigned(bw-1 downto 0); > =A0 =A0begin > =A0 =A0 =A0 result =A0 :=3D =A0 resize(x,bw); > =A0 =A0 =A0 return result; > =A0 =A0end floor; > > begin > > =A0 =A0 =A0 =A0y =A0 <=3D =A0 floor(x,bw); > > end behavioral; > > test bench is as follows =3D> > > LIBRARY IEEE; > USE IEEE.std_logic_1164.ALL; > use ieee.std_logic_unsigned.all; > use ieee.numeric_std.all; > > ENTITY util_tb IS > =A0 =A0 =A0 =A0-- testbench entity is ALWAYS EMPTY > END util_tb; > > ARCHITECTURE tb OF util_tb IS > > =A0 =A0-- local signal declaration > =A0 =A0SIGNAL x =A0 =A0: =A0 unsigned(5 downto 0) ; > =A0 =A0SIGNAL bw =A0 : =A0 integer; > =A0 =A0SIGNAL y =A0 =A0: =A0 unsigned(2 DOWNTO 0); > > =A0 =A0 -- component declaration > =A0 =A0COMPONENT floor_top IS > =A0 =A0generic ( bwin : integer:=3D 6; bwout : integer :=3D 3); > =A0 =A0port( > =A0 =A0 =A0 =A0 =A0 =A0x =A0 : =A0 IN unsigned(bwin-1 downto 0); > =A0 =A0 =A0 =A0 =A0 =A0bw =A0: =A0 IN integer; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 y =A0 : =A0 OUT unsigned(bwout-1 downto 0)= > =A0 =A0 =A0 =A0); > =A0 =A0END COMPONENT; > > =A0 BEGIN > =A0 =A0 =A0 =A0 UUT : floor_top > =A0 =A0 =A0 =A0 PORT MAP( > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0x =A0 =3D> =A0 x, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bw =A0=3D> =A0 bw, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0y =A0 =3D> =A0 y > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0); > > =A0 =A0 =A0 =A0 =A0 =A0 -- apply inputs to monitor outputs > =A0 =A0 =A0 =A0 =A0 =A0 x =A0 =A0<=3D =A0 "101101" AFTER 0 ns, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "001001" AFTER 15 ns, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "111001" AFTER 25 ns; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bw =A0 =A0<=3D =A0 3 AFTER 0 ns; > > END tb; The error i get is as follows # ** Fatal: (vsim-3965) Memory Allocation is too large. Please check your usage. # Time: 0 ns Iteration: 0 Process: /util_tb/uut/line__55 File: C:/ Modeltech_pe_edu_6.3c/examples/floor_top.vhd # Fatal error in Subprogram floor at C:/Modeltech_pe_edu_6.3c/examples/ floor_top.vhd line 47 line 47 in my code is variable result : unsigned(bw-1 downto 0);Article: 127632
On Fri, 4 Jan 2008 01:38:21 -0800 (PST), vasile <piclist9@gmail.com> wrote: >On Jan 1, 10:04 pm, "maxascent" <maxasc...@yahoo.co.uk> wrote: >> Hi >> >> I am designing an 8 layer board with a Virtex 4 device on it. I will have >> 2 solid ground planes and 2 split power planes. If I have a signal plane >> that is between a ground and power plane will it matter if I cross a split >> on the power plane with a signal track. I know that you should not cross a >> split it in a plane if you are referencing to that plane. But if I have a >> solid ground plane beneath the track will it use this plane as its >> reference rather than the power plane. > > Please enlight me: how do you know the trace you are discussing about >will have the "reference" plane either the ground plane or the ground >signal plane ? >The return path will be the smallest impedance path. Meaning it could >be a part from the ground plane and a part of your solid signal ground >plane. You haven't too many options in controlling precisely the >return path as long you have plenty of vias between those two ground >planes... > So you design the stack-up so that the signal plane is close to the ground plane, and at least twice as far from the split power plane. - BrianArticle: 127633
Hi, Can anyone tell me what this bit of code is doing ? -- declarations ------------------------------------------------------------------------------------------- signal phase : std_logic_vector(6 downto 0); type INTEGER_ARRAY is array ( natural range <> ) of integer; constant NUMERATOR : INTEGER_ARRAY(7 downto 0) := (7,30,7,7, 30, 30, 30,30); variable phase_next : std_logic_vector(6 downto 0); -------------------------------------------------------------------------------------------- -- **** problem code ********** phase_next := phase + NUMERATOR(conv_integer(std)); Obviously the conv_integer(std) part of the code is being used to access the array NUMERATOR but I don't understand exactly how since no number value is being specified to key into the array ie. what is the value of 'std' that is being converted to an integer by the function 'conv_integer' ? ThanksArticle: 127634
If I am looking for buying just the FPGA chip itself - not a development board - where could I buy this? What do commercial buyers do? Best Regards HansenArticle: 127635
On 03 Jan 2008 14:44:20 GMT, Habib Bouaziz-Viallet <habib@rigel.systems> wrote: >Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit: > >> Habib Bouaziz-Viallet wrote: >> >>> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >>> >>>> Habib Bouaziz-Viallet wrote: >>>>> Hi all ! >>>>> >>>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>>> >>>>> The "Translate" phase failed : >>>>> What's wrong with this ? > >The problem was that some files in ../bin/lin/ have not executing perms. i >made this : chmod +x winds* or something ... and it compiles fine now ! Glad you found the problem this time; but a pointer to finding problems in general may be useful... the "Translate" phase is basically the NGDbuild program, which writes a ".bld" report file. This ought to contain a messsage (in your case, such as "<something> was not found, or not executable : NGDbuild aborting".) pointing straight at the problem. Ditto failures at the "Map" phase; in the ".mrp" map report file, or at the "PAR" phase, in the ".par" report file. - BrianArticle: 127636
> bw <= 3 AFTER 0 ns; This is your problem. Assigning a value "AFTER 0 ns" in reality means it wont assign the value until the 2nd delta cycle, as it incurs a 1 delta cycle delay. this means "bw" is unassigned for the 1st delta cycle, and it will be trying to resize the unsigned x with INTEGER'LOW, which is something like -2.147Billion IE. its probably trying to make the unisgned variable "result" 2.147 billion bits wide. I doubt you have enough memory for that. to fix: either remove the "AFTER 0 ns" or give BW an initial value in the signal declarations ie: signal bw : integer := 3;Article: 127637
On Fri, 4 Jan 2008 05:10:39 -0800 (PST), FPGA <FPGA.unknown@gmail.com> wrote: >I havw writtent the following code. It compiles correctly. When i run >the simulation it just stops and points to this statement >variable result : unsigned(bw-1 downto 0); It would. >The code and test bench are as below >-- VHDL library declarations >library ieee; >use ieee.std_logic_1164.all; >use ieee.std_logic_unsigned.all; This is NOT a standard library. Don't use it. >use ieee.numeric_std.all; This is a standard library and works well. What you have done here is introduce two different incompatible definitions of "unsigned"... - BrianArticle: 127638
I fixed the problem which I had initially. I have a new one now :) ** Fatal: (vsim-3420) Array lengths do not match. Left is 3 (2 downto 0). Right is 0 (-1 downto 0 (null array)). # Time: 0 ns Iteration: 0 Process: /util_tb/uut/line__55 File: C:/ Modeltech_pe_edu_6.3c/examples/floor_top.vhd # Fatal error in Architecture behavioral at C:/Modeltech_pe_edu_6.3c/ examples/floor_top.vhd line 55 # line 55 is y <=3D floor(x,bw); Please help On Jan 4, 9:39=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Fri, 4 Jan 2008 05:10:39 -0800 (PST), FPGA <FPGA.unkn...@gmail.com> > wrote: > > >I havw writtent the following code. It compiles correctly. When i run > >the simulation it just stops and points to this statement > >variable result =A0 : =A0 unsigned(bw-1 downto 0); > > It would. > > >The code and test bench are as below > >-- VHDL library declarations > >library ieee; > >use ieee.std_logic_1164.all; > >use ieee.std_logic_unsigned.all; > > This is NOT a standard library. Don't use it.>use ieee.numeric_std.all; > > This is a standard library and works well. > > What you have done here is introduce two different incompatible > definitions of "unsigned"... > - BrianArticle: 127639
Hi all , I have been stumped by xilinx tools again ! I have just baught a Evaluation board , whos supporting software , base system etc where writen using EDK 8.1 using older IP cores. Now I am using EDK 9.2i and all the IP cores in the catalogue are new and not compatable with the microblaze version on the older base system that came with the eval board. Is there an easy way to reuse this older base system without rebuilding a new base system from scratch? I tried to preempt the problem by downloading the lates base system file from avnet , but this doesnt give an option for interfacing the Micron DDR SDRAM (MT46V16M16FG-75)! I am currently trying to use the XPS MPMC from the IP catalogue , which apparently support interfacing with the exact SDRAM , but when I configure it , it takes away all the IO lines for DDR! is it a tools bug or am I doing something wrong that causes this? has any one seen such things? Thanks RateArticle: 127640
>On Jan 4, 1:42 am, Gabor <ga...@alacron.com> wrote: >> On Jan 3, 10:28 am, "MJ Pearson" <mjp...@york.ac.uk> wrote: >> >> >> >> > Hello, >> >> > I've some issues hooking up some external components (camera link based >> > cameras) to my XUPV2P board. I've built a PCB which connects the high >> > speed expansion port of the XUPV2P to the outputs of the National Chip >> > DS90CR288A. I've two cameras running simultaneously, so thats two chips on >> > the PCB. >> >> > On the high speed expansion port of the XUPV2P there's a clock input, but >> > because I've got two external clocks (one from each chip), I decided to >> > attach them to the 'regular' FPGA pins. Sorry if this makes no sense! The >> > other high speed expansion port connections are connected to the data >> > signals, and data-valid signals from the chips. >> >> > I've created a peripheral which samples the camera data according to these >> > clock signals, and then sampled again using the Bus2IP clock. I use a >> > microblaze processor just to output various data. On the scope, my clock >> > signals seem to have a period of 16ns, is this too fast for what I want to >> > do? The voltage swing is about 600mV. My design doesn't seem to be working! >> > Just wondered if anyone had any suggestions comments on how best to debug >> > and proceed. >> >Gabor, >Which camera are you using ? >What is the source of this 16ns clock period ? (Probably from a camera >with pixel clock frequency of 60Mhz) > >If it is pixel clock from a camera and the voltage swing is about >600mV, then I am afraid that the fault lies in your custom PCB. > >Did you perform impedance matching for the tracks from high speed edge >connector to DS90288 Chip ? >Have you used appropriate termination resistance to differential >lines ? >What is the distance between the chip (DS90288) and edge connector ? >What is the status of power save mode pin on DS90288 Chip ? > >In my experience, FVAL, LVAL and clock signals are extremely stable >signals from the output of camera. And voltage swing of clock is very >appropriate. > >Try using chipscope pro to observe input signals to FPGA and perhaps >by exporting to data to a text file and using matlab try to display >resulting image. > >Hope this helps. > >/MH > > Hi, thanks for the replies, I thought my PCB might be the problem. I didn't perform any impedance matching or termination. I'm "tapping-off" the signals between the camera and framegrabber. So i have a straight through connection - camera to framegrabber and then "tap-off" the LVDS data-signals and clock and send these into the DS90CR288A. This way I can setup and control the camera using the camera software on PC, and just perform data processing on FPGA. I wasn't sure I needed to terminate the lines, as this would be performed further up the line - at the framegrabber end. The pixel clock from the camera should be 66MHz (I think), so thought I was on the right lines with a 16ns period. The chip however is the 85Mhz version. Is this a maximum? I'm not sure what the clock output of the chip should be - 85Mhz or 66MHz!? I can see data on the output of the chip, LVAL and DVAL signals are correct, not sure about the clock. As I say, the output voltage swing is about 600mV, and looks sinusoidal in shape on the scope - Sorry for the description! The distance between the chip and the connector is about 10mm. Do i need termination resistors across the differential lines in my case?Article: 127641
Hansen, They order from a distributor. Or, they go to the manufacturer's website, and order online through their "store" (which actually takes you to a distributor). AustinArticle: 127642
Rate, Yes, all the tools need to have the same release. Perhaps in the future we can create separate modules and have them be backward compatible, but for right now, the effort is better spent on having the entire release as bug free as possible, supporting all of the features. Typically in a commercial setting, the version of the software is "frozen" and placed under engineering change control at the start of a project. That way, there is no wasted time as the project moves forward, as all the tools are "approved" and verified. AustinArticle: 127643
On Jan 4, 3:18 pm, austin <aus...@xilinx.com> wrote: > Rate, > > Yes, all the tools need to have the same release. > > Perhaps in the future we can create separate modules and have them be > backward compatible, but for right now, the effort is better spent on > having the entire release as bug free as possible, supporting all of the > features. > > Typically in a commercial setting, the version of the software is > "frozen" and placed under engineering change control at the start of a > project. That way, there is no wasted time as the project moves > forward, as all the tools are "approved" and verified. > > Austin True , but in our case there is lagacy code import issues. The application should have backwards compatability. rateArticle: 127644
Rate, "should" would be nice, yes. No question there. But, we do state that we must have all elements of the software toolset at the same revision level (ISE rev must = EDK rev, etc.). Sorry, AustinArticle: 127645
I have 2 inputs x : unsigned bw : integer when x>bw I want to check if x(x'length downto bw) = "1111111......" How do i write this in VHDL since my length of x is unknown at this point. Normally if x was 4 bits, i would check if x(3) and x(2) and x(1) and x(0) = '1' ;Article: 127646
On Jan 4, 10:03 am, "MJ Pearson" <mjp...@york.ac.uk> wrote: > >On Jan 4, 1:42 am, Gabor <ga...@alacron.com> wrote: > >> On Jan 3, 10:28 am, "MJ Pearson" <mjp...@york.ac.uk> wrote: > > >> > Hello, > > >> > I've some issues hooking up some external components (camera link > based > >> > cameras) to my XUPV2P board. I've built a PCB which connects the > high > >> > speed expansion port of the XUPV2P to the outputs of the National > Chip > >> > DS90CR288A. I've two cameras running simultaneously, so thats two > chips on > >> > the PCB. > > >> > On the high speed expansion port of the XUPV2P there's a clock input, > but > >> > because I've got two external clocks (one from each chip), I decided > to > >> > attach them to the 'regular' FPGA pins. Sorry if this makes no sense! > The > >> > other high speed expansion port connections are connected to the > data > >> > signals, and data-valid signals from the chips. > > >> > I've created a peripheral which samples the camera data according to > these > >> > clock signals, and then sampled again using the Bus2IP clock. I use > a > >> > microblaze processor just to output various data. On the scope, my > clock > >> > signals seem to have a period of 16ns, is this too fast for what I > want to > >> > do? The voltage swing is about 600mV. My design doesn't seem to be > working! > >> > Just wondered if anyone had any suggestions comments on how best to > debug > >> > and proceed. > > >Gabor, > >Which camera are you using ? > >What is the source of this 16ns clock period ? (Probably from a camera > >with pixel clock frequency of 60Mhz) > > >If it is pixel clock from a camera and the voltage swing is about > >600mV, then I am afraid that the fault lies in your custom PCB. > > >Did you perform impedance matching for the tracks from high speed edge > >connector to DS90288 Chip ? > >Have you used appropriate termination resistance to differential > >lines ? > >What is the distance between the chip (DS90288) and edge connector ? > >What is the status of power save mode pin on DS90288 Chip ? > > >In my experience, FVAL, LVAL and clock signals are extremely stable > >signals from the output of camera. And voltage swing of clock is very > >appropriate. > > >Try using chipscope pro to observe input signals to FPGA and perhaps > >by exporting to data to a text file and using matlab try to display > >resulting image. > > >Hope this helps. > > >/MH > > Hi, thanks for the replies, > > I thought my PCB might be the problem. I didn't perform any impedance > matching or termination. I'm "tapping-off" the signals between the camera > and framegrabber. So i have a straight through connection - camera to > framegrabber and then "tap-off" the LVDS data-signals and clock and send > these into the DS90CR288A. This way I can setup and control the camera > using the camera software on PC, and just perform data processing on > FPGA. > Tapping into 7 * 66 MHz = 462 Mbps LVDS lines needs to be done carefully to avoid signal integrity problems at the receiver. However if your LVAL and DVAL signals look correct, you may have lucked out... > I wasn't sure I needed to terminate the lines, as this would be performed > further up the line - at the framegrabber end. The pixel clock from the > camera should be 66MHz (I think), so thought I was on the right lines with > a 16ns period. The chip however is the 85Mhz version. Is this a maximum? > I'm not sure what the clock output of the chip should be - 85Mhz or > 66MHz!? > Channel-Link receivers have a wide frequency range of about 20 MHz minimum to the specified maximum (66 or 85 MHz). 66 MHz should work fine. > I can see data on the output of the chip, LVAL and DVAL signals are > correct, not sure about the clock. As I say, the output voltage swing is > about 600mV, and looks sinusoidal in shape on the scope - Sorry for the > description! The distance between the chip and the connector is about > 10mm. Do i need termination resistors across the differential lines in my > case? You may be OK with the 10mm stubs. Definitely don't terminate them if there is already termination at the framegrabber. Also if you still get a proper picture at the framegrabber, you probably have reasonable signal integrity. With your scope it would be hard to look at this... I'm going to guess that the clock is correct, too, but that your scope is bandwidth limiting the signal to form the sine wave you see. What is the input bandwidth of your scope and probe? Did you try to implement a simple T flip-flop in the FPGA to see if the clock is getting into the chip OK? Regards, GaborArticle: 127647
On Jan 4, 10:12 am, austin <aus...@xilinx.com> wrote: > Hansen, > > They order from a distributor. > > Or, they go to the manufacturer's website, and order online through > their "store" (which actually takes you to a distributor). > > Austin Some more notes: Manufacturer websites often point you to a stocking distributor, which may not be a good option for price if you need to buy in quantity. Most FPGA vendors reward their franchised distributors for bringing in business by providing a price break when the distributor "registers" a new product. This is generally passed on to the registered customer and can be a significant price reduction from the published web pricing, even at the same distributor. If you are starting a new product and need to buy FPGA's in quantity, I would suggest talking to your preferred distributor. Don't just place web orders or you could miss out on a sizable price-break. Regards, GaborArticle: 127648
I want to write a function to 1) convert single precision 32 bit floating point number to integer and return integer 2) convert integer to single precision floating point number and return 32 bit floating point What are the parameters I should give to each functions and what logic do I use for both the functions. Do i need to write seperate function for signed and unsigned numbers? Your help would be appreciatedArticle: 127649
On 4 Jan, 17:08, FPGA <FPGA.unkn...@gmail.com> wrote: > I want to write a function to > 1) convert single precision 32 bit floating point number to integer > and return integer > 2) convert integer to single precision floating point number and > return 32 bit floating point > > What are the parameters I should give to each functions and what logic > do I use for both the functions. > > Do i need to write seperate function for signed and unsigned numbers? > > Your help would be appreciated Is this homework / an assignment?
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