Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
> I am presuming that you are referring to a Spartan 3E/3A/3AN/3D series > part. If not, then please let me know if it is a Xilinx part, and which one. > > First, LVDS is a standard, and does not have a specified Vcc. By that, > I mean the output voltages, and input ranges are all detailed in the > IEEE/ANSI standards, and the designer can choose how to power it. > > We chose (in the referenced parts above) to power it from 2.5V. If > instead, you power the bank from 3.3V, no harm is done, both the driver > and the receiver will function (operate), but the specifications of LVDS > (drive impedances, input termination impedances, p-p voltage swing, > common mode voltage) may not be within the LVDS standard's specifications. > > That said, if you characterize it over voltage, and temperature, and > feel you have sufficient margins, and accept responsibility for using it > this way, then, be our guest. Of course, if it doesn't meet one or more > of your requirements, don't expect Xilinx to do anything for you, as > your use is outside of the recommended data sheet parameters. It's for a Spartan-3E starter kit (thus XC3S500E-FG320-4C) which I want to use for driving a lvds receiver (like THC63LVDF84A found in tft modules). The problem is that the Hirose FX2 connector which have a jumper for 3.3V or 2.5V Vcco is expensive when you just want the connector. So I'm looking for using other available ports (J1, J2, J4). But they are likely 3.3V only. So my idea was that maybe at least for testing, 3.3V Vcco operation is tolerable for the lvds receiver specification. The only alternative seems to put a 5x RS422 400 Mbps transmitter chip on seperate prototype pcb.Article: 127251
Can someone please point to a site where we can get some good design examples for Sysgen (not the ones mentioned in the guide) ? Thanks in advance.Article: 127252
Michael Some useful bits and pieces that might help on our website http://www.enterpoint.co.uk/techitips/techitips.html. John Adair Enterpoint Ltd. - Home of Darnaw1. The low cost FPGA development board. On 15 Dec, 16:11, Michael <nleah...@gmail.com> wrote: > Hi there - I recently got a Digilent Spartan 3E Starter Board (http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&N...). > It's been a while since I played with an FPGA, so I was hoping to find > a really comprehensive guide that would walk me through everything, > from making a new project (using Xilinx's software, preferrably), to > writing a simple program (ie hello world, led blink, etc.), to putting > it on the Spartan 3E starter board. Does anybody know of such a guide? > I had expected one to be included with the board, but I can't seem to > find one. > > Thanks! > > -MichaelArticle: 127253
On 14 Dec, 14:40, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 13 Dec 2007 08:19:26 -0800 (PST), ratemonotonic > > <niladri1...@gmail.com> wrote: > >On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> > >wrote: > >> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic > > >> The synthesis output is valid - BUT - will not pass through the > >> implementation tools until you either: redesign to use fewer resources, > >> or: target a bigger FPGA. > >spartan 3 400 has 56Kbit distributed RAM is it possible that the > >synthesizer is using then as block RAMs as well? > > Not if your design specifically calls for BRAMS, so not likely. > In any case it would appear in the synth report and map.mrp > as "LUTs used as memory" or equivalent wording. > > I am confused by the separate synthesis reports yu posted for > modem_wrapper and local_bram ... are you synthesising the two > separately? If so, how are you combining them into one project? > > Is this built entirely under EDK or are you combining an EDK design with > an XST design? It is possible that something is going wrong with that > step; apparently leaving you with a working Microblaze so presumably no > modem... you have to get through this step to correctly fail, THEN worry > about economising memory. > > - Brian Thanks for all the useful messages , I have clarified the base system and connected all the External IOs in the UCF and the synthesis is failing. I will be designing SRAM and FLASH to the design for software and use the internal block rams for local memory , cache and Hardware usage. I am learning more an more about synthesis tools and I am starting to like this! Thanks NiladriArticle: 127254
In answer to all of you who asked about LVDS support on Drigmorn1 we believe 2 pairs of LVDS are very viable but as yet have not tested the feature. Some others may be possible but pin routing is not so good. John Adair Hone of Drigmorn1. The low cost starter FPGA development board.Article: 127255
On Sat, 15 Dec 2007 12:42:09 -0800 (PST), posedge52@yahoo.com wrote: >> I am presuming that you are referring to a Spartan 3E/3A/3AN/3D series >> part. If not, then please let me know if it is a Xilinx part, and which one. >> >> First, LVDS is a standard, and does not have a specified Vcc. By that, >> I mean the output voltages, and input ranges are all detailed in the >> IEEE/ANSI standards, and the designer can choose how to power it. >> >> We chose (in the referenced parts above) to power it from 2.5V. If >> instead, you power the bank from 3.3V, no harm is done, both the driver >> and the receiver will function (operate), but the specifications of LVDS >> (drive impedances, input termination impedances, p-p voltage swing, >> common mode voltage) may not be within the LVDS standard's specifications. >> >> That said, if you characterize it over voltage, and temperature, and >> feel you have sufficient margins, and accept responsibility for using it >> this way, then, be our guest. Of course, if it doesn't meet one or more >> of your requirements, don't expect Xilinx to do anything for you, as >> your use is outside of the recommended data sheet parameters. > >It's for a Spartan-3E starter kit (thus XC3S500E-FG320-4C) which I >want to use for driving a lvds receiver (like THC63LVDF84A found in >tft modules). >The problem is that the Hirose FX2 connector which have a jumper for >3.3V or 2.5V Vcco is expensive when you just want the connector. So >I'm looking for using other available ports (J1, J2, J4). But they are >likely 3.3V only. So my idea was that maybe at least for testing, 3.3V >Vcco operation is tolerable for the lvds receiver specification. >The only alternative seems to put a 5x RS422 400 Mbps transmitter chip >on seperate prototype pcb. We usually use 3.3 volts on Spartan3 lvds inputs and outputs, and it has always worked so far. External termination of inputs might be prudent, as someone has mentioned that the termination impedance might not be right at 3.3. JohnArticle: 127256
posedge52@yahoo.com wrote: > > It's for a Spartan-3E starter kit (thus XC3S500E-FG320-4C) which I > want to use for driving a lvds receiver (like THC63LVDF84A found in > tft modules). > The problem is that the Hirose FX2 connector which have a jumper for > 3.3V or 2.5V Vcco is expensive when you just want the connector. So > I'm looking for using other available ports (J1, J2, J4). But they are > likely 3.3V only. So my idea was that maybe at least for testing, 3.3V > Vcco operation is tolerable for the lvds receiver specification. > The only alternative seems to put a 5x RS422 400 Mbps transmitter chip > on seperate prototype pcb. Consider soldering directly to the pins on the expansion connector. The Hirose connector isn't that expensive (I believe they're available from both DigiKey and Mouser) but before I had them on hand, I wired an RJ45 connector straight to the pins on the board-side of the connector. The nice thing about differential signals is that they're pretty tolerant to this kind of manipulation. I would *seriously* consider avoiding the general purpose connections because they are *not* treated as differential signals on the board. Finding complementary pairs on those connectors might also be difficult. Keep in mind that the signals that go to the Hirose connector also go to the "no touch connector" pads where you could pick of some signals for soldering; there would be a stub if you don't do anything but you could always take an Xacto knife to the trace beyond that point. Go for the 2.5V! - John_HArticle: 127257
Digilent provides no sw or documentation & a pretty junky usb cable with their kit. You should've bought it from avnet or nuhorizon, same board, same price. They include a large amount of useful sw & tutorial. "Michael" <nleahcim@gmail.com> wrote in message news:59abbd2d-d9e7-4bf9-8bdf-aae821eb5eae@i12g2000prf.googlegroups.com... > Hi there - I recently got a Digilent Spartan 3E Starter Board (http:// > www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable). > It's been a while since I played with an FPGA, so I was hoping to find > a really comprehensive guide that would walk me through everything, > from making a new project (using Xilinx's software, preferrably), to > writing a simple program (ie hello world, led blink, etc.), to putting > it on the Spartan 3E starter board. Does anybody know of such a guide? > I had expected one to be included with the board, but I can't seem to > find one. > > Thanks! > > -MichaelArticle: 127258
Use National serdes to handle the serial stream. A lot cheaper than a v5. "cpope" <cepope@nc.rr.com> wrote in message news:4762b4a9$0$28815$4c368faf@roadrunner.com... > This is probably a long shot but I'm wondering if serial ATA can be run at > a > speed less than 1.5 Gbps? I have a V4 fpga but no MGTs so it would be nice > if I could make it work with regular chipsync resources which can only go > about 800 mbps. > > Thanks, > Clark > >Article: 127259
Nationaereader wrote: > Use National serdes to handle the serial stream. A lot cheaper than a v5. > > "cpope" <cepope@nc.rr.com> wrote in message > news:4762b4a9$0$28815$4c368faf@roadrunner.com... >> This is probably a long shot but I'm wondering if serial ATA can be run at >> a >> speed less than 1.5 Gbps? I have a V4 fpga but no MGTs so it would be nice >> if I could make it work with regular chipsync resources which can only go >> about 800 mbps. >> >> Thanks, >> Clark >> >> > > The National SERDES does out of band signaling? Handles spread spectrum? You're talking about a SATA PHY? What's the part number? Or were you thinking "serdes" generically?Article: 127260
This may sound like a stupid question to you. But I really don't understand how come the core dynamic power is still quite large when toggle rate is. In my understanding, there is no signal change when toggle rate is 0 and thus no discharge and charge will happen except the clock net. So when the toggle rate is 0, the clock power should be the only power consumption of the dynamic power. But it doesn't look like that when I analysis the power consumption using Xpower? Thank you very much for your reply, RebeccaArticle: 127261
Hi guys, finally Mico32 linux kernel source tree is available as a git repos. Anyone interested in joining the journey could get it from: git clone git://sopc.et.ntust.edu.tw/git/linux-2.6.git test-lm32 cd test-lm32 git checkout -b test-lm32 origin/test-lm32 mkdir ../lm32-build make O=../lm32-build ARCH=lm32 CROSS_COMPILE=lm32-elf- defconfig make O=../lm32-build ARCH=lm32 CROSS_COMPILE=lm32-elf- vmlinux Some info about how to obtain the cross-compiler directly from Lattice: http://www.latticesemi.com/forums/forum/messageview.cfm?catid=523&threadid=3942&enterthread=y or, if you prefer, I've written down an article about it (in Italian) at: http://www.porcacchia.com/index.php?option=com_content&task=view&id=61&Itemid=48 Despite being at very early stage, you can to debug and help in developing using the simulator provided by Lattice in the GCC suite. Dig for mico32 in the 'Documentation/mico32' folder of your newly git kernel directory, I will add more info on this topic soon, since it has some command-line parameters that are strictly necessary in order to have a working timer and uart. Regards, AndreaArticle: 127262
Hi, There are several modules in a design, which will be assigned to several member in the group. If the system clock is 100MHz, what timing constraint value should be for each input Pad-to-Setup and Clock-to-Out paths? If clock rate is 200MHz or 300MHz, what about the constraints? I doubt it should be proportional to the clock rates. Thanks a lot.Article: 127263
On Dec 15, 2:10 pm, John_H <newsgr...@johnhandwork.com> wrote: > posedg...@yahoo.com wrote: > > What's the 6-pin connection "J8" on the lower-left of the Xilinx/ > > Digilent "Spartan-3E starter kit" (rev D) wired too ..?, can't find it > > in the schematics.. > > > Google search doesn't turn up anything useful either. > > J8 appears to be labeled on the board as "CPLD JTAG." I don't have my > revD board here at home but I looked through the user guide and found > figure 2-3, page 16, had a good closeup of that corner of the board > > http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf > > I don't believe this is the "J28" mentioned for an alternate JTAG in the > user guide but, instead, part of the super-secret embedded USB JTAG > programmer. If you download the schematics separately > > http://www.xilinx.com/support/documentation/boards_and_kits/S3E_Start... > > you'll find page 3 is intentionally left blank. It's here that the USB > chip and supporting circuitry would be found. If you find an > undocumented CPLD next to the Cypress chip, you'll probably find its > JTAG pins connected to J8. > > Have fun with your board! > > - John_H Does anybody know why this page is mysteriously and 'intentionally' left blank? John.Article: 127264
On Dec 15, 8:19 pm, "ereader" <r...@myhouse.com> wrote: > Digilent provides no sw or documentation & a pretty junky usb cable with > their kit. > You should've bought it from avnet or nuhorizon, same board, same price. > They include a large amount of useful sw & tutorial. > To be honest - I don't know where the board came from. I am the second owner. How do you tell where it came from? -MichaelArticle: 127265
Hi,all.I am doing a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software designer and never do IC design before ,so this project is very difficult for me.Who could help me and give me some guidances or some datum and paper about how to implement SAS with FPGAs.I will be very grateful.Thanks very much.Article: 127266
Rebecca, Dynamic power is the power consumed when all clocks are toggling. When all clocks are at 0 hertz (not running), the power that is still there, is known as the static power. In any design, with all data forced to 0's, and all flip flops with their clock enables disabled, but with the clock running, there will be dynamic power consumed from the clock tree toggling, and all of the logic in each flip flop that is still toggled by the clock, even without the flip flops changing state (a clock enable does not eliminate dynamic power). Toggle rate is how often the data is changing. For example, 50% toggle rate means the data changes on every other clock. So, the amount of logic and flip flops connected to a clock, the rate at which the nodes change state, and the frequency are all elements of the dynamic power. The static power is from the leakage of the devices, and any constant current bias sources required for operation. A toggle rate of 0%, is not a very interesting case (clocks are running, but nothing happens). AustinArticle: 127267
On 16 Dez., 16:11, westsp...@gmail.com wrote: > Hi,all.I am doing a project which will implement SAS with FPGAs on > Xilinx Virtex 4 ML405 board. But before I am a software designer and > never do IC design before ,so this project is very difficult for > me.Who could help me and give me some guidances or some datum and > paper about how to implement SAS with FPGAs.I will be very > grateful.Thanks very much. You are not talking about the airline, are you? If not, lease check all that apply: You want ot build an: a) Safety and Automation System b) Synthetic Aperture Sonar c) beam forming circuitry for Small-Angle Scattering d) Slot Accounting System a) will be easist, c) requires a lot of additional hardware not found on an ML405, a) should not be build by a novice. b) probably is the best match for an ML405. Kolja SulimmaArticle: 127268
comp.arch.fpga wrote: > On 16 Dez., 16:11, westsp...@gmail.com wrote: >> Hi,all.I am doing a project which will implement SAS with FPGAs on >> Xilinx Virtex 4 ML405 board. But before I am a software designer and >> never do IC design before ,so this project is very difficult for >> me.Who could help me and give me some guidances or some datum and >> paper about how to implement SAS with FPGAs.I will be very >> grateful.Thanks very much. > > You are not talking about the airline, are you? > > If not, lease check all that apply: > You want ot build an: > a) Safety and Automation System > b) Synthetic Aperture Sonar > c) beam forming circuitry for Small-Angle Scattering > d) Slot Accounting System > > a) will be easist, c) requires a lot of additional hardware not found > on an ML405, a) should not be build by a novice. b) probably is the > best match for an ML405. > > > Kolja Sulimma I think the OP probably means Serial Attached SCSI, which is very close to SATA. Depending on the speeds involved, 1.5G or 3G, this may not be an appropriate first project. RBArticle: 127269
jcr_alr@xplornet.com wrote: > > Does anybody know why this page is mysteriously and 'intentionally' > left blank? > > John. "It's here that the USB chip and supporting circuitry would be found." The Xilinx Platform USB cable and associated embedded version is proprietary design information. I imagine Xilinx doesn't want to add the need to support people trying to build their own or complaining when their self-cloned hardware stops working when firmware is updated. While I would like to see this information made public - with a good way in and out of the development boards through USB for the user - I can understand the headaches that would accompany making this material public. Not everyone understands what "no support provided" means for people who choose to modify or copy the functionality, so it's perhaps best left behind the curtain. - John_HArticle: 127270
Michael wrote: > On Dec 15, 8:19 pm, "ereader" <r...@myhouse.com> wrote: >> Digilent provides no sw or documentation & a pretty junky usb cable with >> their kit. >> You should've bought it from avnet or nuhorizon, same board, same price. >> They include a large amount of useful sw & tutorial. >> > To be honest - I don't know where the board came from. I am the second > owner. How do you tell where it came from? > > -Michael You don't. Digilent manufactures the board for their online store, for Avnet, for NuHorizons, and for Xilinx when they choose to sell direct. In my opinion, the online information at xilinx.com is typically sufficient to work with the Xilinx/Digilent starter kits. As for "junky USB cable" - a USB cable is a USB cable, isn't it? It's not like the typical engineer wants "Monster Cables" to provide their USB connectivity. With the exception of the EDK starter kit, I don't think there's software involved with any of the starter kits. Webpack is online. The user guide is online. I'm happy with the boards I've purchased. - John_HArticle: 127271
westspeed@gmail.com wrote: > Hi,all.I am doing a project which will implement SAS with FPGAs on > Xilinx Virtex 4 ML405 board. But before I am a software designer and > never do IC design before ,so this project is very difficult for > me.Who could help me and give me some guidances or some datum and > paper about how to implement SAS with FPGAs.I will be very > grateful.Thanks very much. Serial Attached SCSI is NOT a task for someone to design from the ground up unless they are *very* seasoned hardware engineers, in my opinion, and have time to "waste" at that. If you purchase an SAS core from a 3rd party vendor, integrating this core to a usable system would be a challenge for someone unfamiliar with hardware design, though doable. Starting from nothing, this would have to be at least a man year worth of work to get to where the drives are starting to talk for someone who isn't already confident with FPGAs. If you have the SAS cores, you may be able to get integration help from the people who developed the cores. At least the learning curve at that point would be much simpler for the uninitiated since wiring up cores to a top level design is easier than developing the core, but it's still not something I'd expect a non-hardware person to be responsible for. It's a little like asking me - expert in hardware, knowledge about software with the ability to read through most and write some C - to develop a database system for those SAS drives. Uhhh.... - John_HArticle: 127272
fl wrote:
> Hi,
> There are several modules in a design, which will be assigned to
> several member in the group. If the system clock is 100MHz, what
> timing constraint value should be for each input Pad-to-Setup and
> Clock-to-Out paths? If clock rate is 200MHz or 300MHz, what about the
> constraints? I doubt it should be proportional to the clock rates.
> Thanks a lot.
Knowing nothing else,
I would set reg to reg Fmax to the system clock frequency
and the pin Tsu and Th to half the system clock period.
-- Mike Treseler
Article: 127273Rebecca wrote: > This may sound like a stupid question to you. But I really don't > understand how come the core dynamic power is still quite large when > toggle rate is. In my understanding, there is no signal change when > toggle rate is 0 and thus no discharge and charge will happen except > the clock net. > So when the toggle rate is 0, the clock power should be the only power > consumption of the dynamic power. But it doesn't look like that when > I analysis the power consumption using Xpower? > > Thank you very much for your reply, > Rebecca This may be a terminology issue. Is there a separate listing for Static Power ? All devices have a power-drain of the form Icc[Vcc.Temp.Max] = Icc.Static + Icc.Dynamic[Nodes.MHz] Icc[Vcc.Temp.Typ] = Icc.Static + Icc.Dynamic[Nodes.MHz] With this, if Mhz is zero, only the Icc.Static component should be included, and in modern FPGA that certainly IS 'still quite large'. Even smaller CPLD devices that claim to be 'Zero power', really only get that Static.Icc somewhere under 100uA. -jgArticle: 127274
Hi,
I have some trouble when I try to generate a RPM using the
floorplanner tool in Xilinx.
I'm trying to make a RPM from a quite large design but cannot get it
to work.
Now I'm trying with a simplified sub-module of my design (see below).
The merge_test entity is a simple demux with 3 select signals for each
data signal.
When I synthesize and implement in Xilinx ISE I use the standard
settings except
that I unchecks the insertion of I/O buffers and trimming of
unconnected signals.
After PAR I load the design into floorplanner and selects floorplan-
>replace all with placement.
I get the first problem after executing "replace all with placement".
Two gates in the Design Hierarchy
window is still unplaced! I have to place them manually to get them
included in the RPM.
Next issue:
When I count the number of LUTs showing up in floorplanner I only get
18 LUTs including the two
unplaced gates. Two LUTs are missing! So I loads the design into FPGA
Editor and I'm able to locate all 20 LUTs. The four problematic LUTs
are the 4 3-input OR-gates for or-ing the select signals together.
The four problematic are all marked as "Route Through"s in FPGA
Editor.
What are a route through?
How do I get all LUTs to show up and get placed in floorplanner so I'm
able to generate an RPM of the design?
The target is a Xilinx Virtex-5 FPGA.
Any help is appreciated.
Kind Regards
Jon Neerup Lassen
------ BEGIN VHDL -------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity merge_test is
port(
a0,a1,a2 : in std_logic;
b0,b1,b2 : in std_logic;
c0,c1,c2 : in std_logic;
d0,d1,d2 : in std_logic;
a_data : in std_logic_vector(7 downto 0);
b_data : in std_logic_vector(7 downto 0);
c_data : in std_logic_vector(7 downto 0);
d_data : in std_logic_vector(7 downto 0);
z_data : out std_logic_vector(7 downto 0)
);
end merge_test;
architecture arch of merge_test is
signal a,b,c,d : std_logic;
begin
data_demux :
process(a0,a1,a2,b0,b1,b2,c0,c1,c2,d0,d1,d2,a_data,b_data,c_data,d_data)
begin
if (a0 or a1 or a2) = '1' then
z_data <= a_data;
elsif (b0 or b1 or b2) = '1' then
z_data <= b_data;
elsif (c0 or c1 or c2) = '1' then
z_data <= c_data;
elsif (d0 or d1 or d2) = '1' then
z_data <= d_data;
else
z_data <= (others => '0');
end if;
end process;
end arch;
----- END VHDL -----
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z