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I'm a beginner with FPGA and I want to dive into the digital video filtering, analysis and display. I can clearly imagine that it is a big performance for a beginner and I wonder to start in the better way. What is the easier way to start? Xilinx or ALtera? What guides? CheersArticle: 125451
Hello, All, T the clocks power results given by the XPower are always 0 when I tested my designs. But there must be some clock power consumption. If an EDK generated project which contains a MicroBlaze is analyzed, the clocks power is about 80mw. I think I must omit something here. It seems like the synthesis doesn't know that my input clk is a clock signal. Where should I give the information and how? Thank you very much, RebeccaArticle: 125452
tagough@gmail.com wrote: > Hello all > > Does anyone have a Signetics data sheet / data book with this part? > > Thank you Did you mean the 82S101 ? Google has more luck with that more correct part number :) -jgArticle: 125453
Surely you would be the kind of person to jump to conclusion? I have used Quartus II from before version 6 and I have never had a crash (unlike with ISE). TommyArticle: 125454
techG wrote: > HI, I'm new in FPGA, I have to build a SPI interface (in VHDL) to let > an fpga read and write a flash memory. > The fpga is a Xilinx Spartan3E, while the memory is an ST M25P16 > (serial I/O). > Do you know if is there any built vhdl core to start with? > > Thanks in advance > Giulio > An SPI interface is really pretty easy to implement. The major difficulty is reading through the device data sheet to make sure you get all the details correct. There are a large number of different flavors of SPI, so an interface developed for one application is probably not going to be a perfect fit for another. It is a good beginner's project.Article: 125455
> > Since the OP seems to have disappeared to wherever OPs go, I > suspect we will never find out. > I didn't disappear, I posted a reply but for some reason it didn't show up... I didn't want to accidentally spam the newsgroups by reposting and figured I'd wait to make sure it wasn't just my newsreader or ISP causing the problem. Anyway, I guess I'll answer the reason why I want to do this in the same post. I'm trying to characterize a DRAM device in certain environmental (radiation) conditions and see how that effects the retention characteristics. I'm not sure if there tests the industry uses to do this, but I needed to evaluate it realtime. I'm using the core Altera provided but all the code is there (except for the NIOS II cpu). So I have direct access to the SDRAM controller.Article: 125456
> Assuming he has a good reason to change it, > the safest thing to do would be to call a > routine in flash to change it.- Hide quoted text - > Thanks for giving me the benefit of the doubt. I put this in another reply, but the reason I want to change it is to characterize the DRAM to get it's retention characteristics in a radiation environment. So I want to know how long the DRAM keeps it's charge given a specific and controlled environment. Interfacing, programming, and DRAM definitely aren't my areas of study (materials is). This is for a small but time consuming part of my thesis project. Thanks, ericArticle: 125457
> Probably so, but it isn't at all obvious how to answer. The DRAM > doesn't care as long as every row is refreshed within the specified > amount of time. Some refresh all rows in a big burst, others one > at a time uniformly over the interval. You can refresh faster than > the specified rate, but there is no system independent way to > describe how to do that. For systems with a variable speed > clock (such as power saving modes) one does have to design > the refresh system appropriately. I know the mode register is initialized at the beginning with the refresh rate (and some other information). Is it possible to reload the mode register and will this do anything to the stored data (such as letting all the caps discharge)? Is this even possible? I do appreciate everyone's replies and I certainly didn't mean to ignore your answers and questions that were trying to help me. Paul mentioned in his reply that it makes sense to do it in different temperatures. This really is similar to what I am trying to do. I'm trying to figure out (partly) if the refresh rate will help with the radiation tolerance of the device (i.e. speeding it up).Article: 125458
Gabor wrote: (snip) > He's probably sorry about the flame war he unintentionally created > but thinks it would have been nice if one of the 25 replies answered > his original question... Probably so, but it isn't at all obvious how to answer. The DRAM doesn't care as long as every row is refreshed within the specified amount of time. Some refresh all rows in a big burst, others one at a time uniformly over the interval. You can refresh faster than the specified rate, but there is no system independent way to describe how to do that. For systems with a variable speed clock (such as power saving modes) one does have to design the refresh system appropriately. -- glenArticle: 125459
Andy wrote: (snip) > The TRS-80 Color Computer (Moto 6809 based) refreshed during the > vertical retrace. But there was a bit in the system controller that > could be set to turn it and video access off, while doubling the > processor clock. I thought it was the display memory access that did the refresh. I probably still have the service manual around somewhere. > As long as your Basic code was running, and not > waiting on a keyboard input or other event, the ROM interpreter's RAM > accesses managed to keep the RAM (at least the part of it being used) > refreshed. But if/when the code hit an error (and thus waited for user > response) you could watch the screen go from random pixels to all > white. Once the coding errors were eliminated, it was a reliable way > to double the processing speed when you did not need video. If I remember, there were three modes. Normal mode, one that doubled the clock speed some of the time, and one that doubled it all the time. I never tried turning the display off, though. -- glenArticle: 125460
lyfieryflame@gmail.com wrote: > The EDIF file generated by DK4 is working fine with Xillinx ISE. Is > there any special requirement for compiling EDIF using QuartusII? An EDIF file is a device netlist. There should be two of them if you want to try both X and A. -- Mike TreselerArticle: 125461
I'm woefully undereducated to be doing this, but I figure the best way to learn is by doing, so I need a little help with my current project. I'm designing a lighting dimmer around the Altera Cyclone EP1C6 in the 240 pin package. I will be using the chip to turn on and off up to 128 optoisolators at a frequency of 120Hz. (The optos will feed the gate pins of TRIACs which will turn Christmas lights on and off. By turning the optos on in the middle of an AC half-cycle I plan on getting dimming in addition to on/off.) Each opto will draw a maximum of 7mA. The FPGA will be sinking the current from the opto, not sourcing current. Absolute worst case would be all 128 channels switching simultaneously, although I doubt that would happen very frequently. (For one, I don't have enough circuits to drive 128 strings of Christmas lights without tripping a breaker at the house.) I have no clue how to determine what size capacitors to put between the VCCIO pins and GND. If anyone could give some guidance, I'd appreciate it. (If you happened to use my particular implementation as an example, I'd appreciate it that much more!) Thanks, all! -MattArticle: 125462
Unless the netlist is incorrect i.e. there is truly a net missing a source, it is possible that the strings used to identify VCC and GND signals have not been specified. To specify the VCC and GND signals that is used in the EDIF file do the following: 1. Go to Assignments->EDA Tool Settings->Design Entry/Synthesis 2. Set Tool name to Custom 3. Make Sure Tool is EDIF 4. Set the VCC and GND values as you see them in the EDIF file being used. Hope this helps, Subroto Datta Altera Corp. <lyfieryflame@gmail.com> wrote in message news:1193323633.246260.157870@z9g2000hsf.googlegroups.com... > Hi all, > > I got an error when I compile the EDIF file generated by Celoxica DK4. > The code is written in Handel-C. I add the EDIF file and the TCL file > generated by DK4 to the project, the error is following: > Error: Node "B57_testforQuartusII_hcc_8_DTYPE0IR" is missing source > > the TCL file is following: > > ############################################################################## > # > # Assignment and Constraints Quartus TCL script for design N:\myhome > \my stuff\handel-c\test\testforQuartusII\EDIF\testforQuartusII.edf > # > # Generated by Celoxica Hardware Compiler (Version 3.5.3555.63181) > # Timestamp 2007 4 17 15 54 52 > # > ############################################################################## > > > # Set family and part > set_global_assignment -name FAMILY "STRATIX II" > set_global_assignment -name DEVICE "ep2s15f484c5" > > # Set compilation options > set_global_assignment -name ALLOW_POWER_UP_DONT_CARE Off > set_global_assignment -name AUTO_PACKED_REGISTERS Normal > > > ############################### IO assignments > ############################### > > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADIN_testforQuartusII_hcc_ClockInPin > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADIN_testforQuartusII_hcc_Read_read_4 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADIN_testforQuartusII_hcc_Read_read_3 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADIN_testforQuartusII_hcc_Read_read_2 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADIN_testforQuartusII_hcc_Read_read_1 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADIN_testforQuartusII_hcc_Read_read_0 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADOUT_testforQuartusII_hcc_Write_write_4 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADOUT_testforQuartusII_hcc_Write_write_3 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADOUT_testforQuartusII_hcc_Write_write_2 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADOUT_testforQuartusII_hcc_Write_write_1 > set_instance_assignment -name IO_STANDARD "LVTTL" -to > PADOUT_testforQuartusII_hcc_Write_write_0 > > > ############################# Timing requirements > ############################ > > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B48_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B49_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B50_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B51_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B52_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B53_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B54_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B55_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B56_testforQuartusII_hcc_8_DTYPE0IR > set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to > B57_testforQuartusII_hcc_8_DTYPE0IR > > > The EDIF file generated by DK4 is working fine with Xillinx ISE. Is > there any special requirement for compiling EDIF using QuartusII? > > Many Thanks, > Ying >Article: 125463
Tommy Thorn wrote: > Surely you would be the kind of person to jump to conclusion? I have > used Quartus II from before version 6 and I have never had a crash > (unlike with ISE). You mustn't use it very much then! I'm not saying it's flakey, it _is_ pretty stable, but I certainly couldn't say it _never_ crashes. Antti, I have it on good authority that Quartus v7.1 is not to be touched with a 10-ft clown pole, but v7.2 fixes a lot of the problems with it. I'm still using v7.0 myself (for this reason), so all this is just hear-say. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 125464
tirsys wrote: > What is the easier way to start? Xilinx or ALtera? Try one of the alt.religion newsgroups for these types of questions... ;) Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 125465
Not really answering your question, but... Sink or source, 128 x 7mA is a lot, your FPGA may not be able to handle it. You probably need something a bit more efficient or maybe an extra level of transistors to give current gain.Article: 125466
On Oct 26, 5:49 am, Mark McDougall <ma...@vl.com.au> wrote: > tirsys wrote: > > What is the easier way to start? Xilinx or ALtera? > > Try one of the alt.religion newsgroups for these types of questions... ;) > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 If you go for Xilinx you can read my FPGA for beginner's blog: http://www.fpgafromscratch.com SvenArticle: 125467
On Oct 25, 4:20 pm, sendt...@gmail.com wrote: > > Since the OP seems to have disappeared to wherever OPs go, I > > suspect we will never find out. > > I didn't disappear, I posted a reply but for some reason it didn't > show up... I didn't want to accidentally spam the newsgroups by > reposting and figured I'd wait to make sure it wasn't just my Here is a free suggestion (the price is right): I would write a specific word-pattern with an even mix of 1 and 0 into every location in the whole DRAM. Then read back sequentially at a slow pace through all addresses, always checking the readback. Sooner or later, you will pick up an error, becaue you exceeded the refresh delay. You may want to repeat this with different starting addresses and with different word patterns. My opinion: SEU errors have little to do with refresh delay, since an ion can tip over even a fully charged bit. But that seems to be what you want to find out... Peter Alfke > newsreader or ISP causing the problem. > > Anyway, I guess I'll answer the reason why I want to do this in the > same post. > > I'm trying to characterize a DRAM device in certain environmental > (radiation) conditions and see how that effects the retention > characteristics. I'm not sure if there tests the industry uses to do > this, but I needed to evaluate it realtime. > > I'm using the core Altera provided but all the code is there (except > for the NIOS II cpu). So I have direct access to the SDRAM > controller.Article: 125468
Hi Mikhail. Alright.. There seems to be new model Using the Timer-Based Simplex Mode in the version of Aurora 2.8 core. This contains the little tricks to set initialization settings using a timer. Will check that option out as well. Thanks, Best Regards shakith On Oct 25, 10:29 pm, "MM" <mb...@yahoo.com> wrote: > A small addition: > > The TX_BONDED-RX_BONDED connection is only required when channel bonding is > used. > > /MikhailArticle: 125469
On 25 Okt., 23:21, Tommy Thorn <tommy.th...@gmail.com> wrote: > Surely you would be the kind of person to jump to conclusion? I have > used Quartus II from before version 6 and I have never had a crash > (unlike with ISE). > > Tommy eh, yes, I have really occasionally touched quartus. to my memory it did never have problems. so that made me really wonder that 7.1 self-terminates about once per hour. expect that self-termiation it works rather fine, and yes its better to live with occasioal self-closure then real bugs with tools like some other vendor tools AnttiArticle: 125470
On Oct 26, 5:58 am, svenand <sven...@comhem.se> wrote: > > If you go for Xilinx you can read my FPGA for beginner's blog:http://www.fpgafromscratch.com > > Sven It's nice blog. I just wonder how much of the material in this blog is applicable for Spartan3E-1600E Microblaze Development Kit which I've got?Article: 125471
On 26 Okt., 07:00, Peter Alfke <al...@sbcglobal.net> wrote: > On Oct 25, 4:20 pm, sendt...@gmail.com wrote:> > Since the OP seems to have disappeared to wherever OPs go, I > > > suspect we will never find out. > > > I didn't disappear, I posted a reply but for some reason it didn't > > show up... I didn't want to accidentally spam the newsgroups by > > reposting and figured I'd wait to make sure it wasn't just my > > Here is a free suggestion (the price is right): > I would write a specific word-pattern with an even mix of 1 and 0 into > every location in the whole DRAM. > Then read back sequentially at a slow pace through all addresses, > always checking the readback. > Sooner or later, you will pick up an error, becaue you exceeded the > refresh delay. > You may want to repeat this with different starting addresses and with > different word patterns. > > My opinion: > SEU errors have little to do with refresh delay, since an ion can tip > over even a fully charged bit. But that seems to be what you want to > find out... > Peter Alfke > > > > > newsreader or ISP causing the problem. > > > Anyway, I guess I'll answer the reason why I want to do this in the > > same post. > > > I'm trying to characterize a DRAM device in certain environmental > > (radiation) conditions and see how that effects the retention > > characteristics. I'm not sure if there tests the industry uses to do > > this, but I needed to evaluate it realtime. > > > I'm using the core Altera provided but all the code is there (except > > for the NIOS II cpu). So I have direct access to the SDRAM > > controller.- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - eh, there used to be a special software that allows a DRAM to work as black white camera it was using 64K x 1 military DRAMs, with REMOVED top lid, directly connected to PC LPT port. the software measured the refresh of each cell, what is proportional to the light the author of that software had some "photos" taken with DRAM online too. and eh it wasnt me. but one of my first self-made homecomputers used the same military gold-ceramic packaged DRAMs AnttiArticle: 125472
Antti wrote: <snip> > > eh, there used to be a special software that allows a DRAM to work as > black white camera > > it was using 64K x 1 military DRAMs, with REMOVED top lid, > directly connected to PC LPT port. > > the software measured the refresh of each cell, what is proportional > to the light > the author of that software had some "photos" taken with DRAM online > too. > and eh it wasnt me. but one of my first self-made homecomputers used > the same military gold-ceramic packaged DRAMs Please see the thread entitled: "Poor Man's image sensor; Was: Re: Simple Still Camera components?" from June of this year (in comp.arch.embedded). If anyone wants it and cannot find it, I have the archive of this project's code and documentation (in German, filename: kuckuck.zip). Regards, MichaelArticle: 125473
> Here is a free suggestion (the price is right): > I would write a specific word-pattern with an even mix of 1 and 0 into > every location in the whole DRAM. > Then read back sequentially at a slow pace through all addresses, > always checking the readback. > Sooner or later, you will pick up an error, becaue you exceeded the > refresh delay. > You may want to repeat this with different starting addresses and with > different word patterns. The problem is during the read (I'm assuming you mean by disabling the refresh altogether and relying solely on the refresh after read) is that it takes several seconds to read from the DRAM. This will always exceed the refresh time right? From the start_address to end_address it takes quite a while for a 64Mbit DRAM. The spec calls for a 64ms refresh.Article: 125474
On Oct 26, 12:01 am, Ray Andraka <r...@andraka.com> wrote: > techG wrote: > > HI, I'm new in FPGA, I have to build a SPI interface (in VHDL) to let > > an fpga read and write a flash memory. > > The fpga is a Xilinx Spartan3E, while the memory is an ST M25P16 > > (serial I/O). > > Do you know if is there any built vhdl core to start with? > > > Thanks in advance > > Giulio > > An SPI interface is really pretty easy to implement. The major > difficulty is reading through the device data sheet to make sure you get > all the details correct. There are a large number of different flavors > of SPI, so an interface developed for one application is probably not > going to be a perfect fit for another. It is a good beginner's project. I agree both of you: this is a very good project for a beginner. Once you master the shift register the other things become a piece of cake. Try to use simulator (Modelsim XE) for code simulation and Chipscope for HW debug. These two tools will eventually save you a lot of time. Guru
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