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posedge52@yahoo.com wrote: > On 31 Jan, 00:01, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> > wrote: > >>posedg...@yahoo.com wrote: >> >> >>>It's not problem to run ISE with linux-api module (linux.ko) under FreeBSD btw. >> >>If you run on anything non-Redhat/Windows, be prepared to get the answer >>"Not a supported platform" all the time :-( Sounds like a default response. So far I haven't had any ISE issues that I can't fix by creating a new project and putting the original source. As to my verilog and design that's my own fault. I am definitely still learning. Thanks AndyArticle: 128576
On Jan 31, 4:08 am, Nick <tk...@cuhk.edu.hk> wrote: > Hi all, > > I am sorry if this problem has been answered but I cannot find much help > from the archive. > > I am using a Spartan3 starter board to interface with a Micron CMOS > Image sensor (MT9T001), and is confused with the output data from the > sensor. > > It outputs 10-bit pixel datum in each pixel clock, but I am wondering > what is the use of the last 2 bits? > > From my understanding, each pixel datum is of 0~255 value (2-to-power-8). > > Thanks! > > Nick Hi, with 10 bits pixel you have more accuracy for each pixel. If you need only 8 bit for each pixel, just ignore the 2 LSBs. MatteoArticle: 128577
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:fnqvks$2gi$1@lnx107.hrz.tu-darmstadt.de... > posedge52@yahoo.com wrote: > ... >> It's not problem to run ISE with linux-api module (linux.ko) under >> FreeBSD btw. > > If you run on anything non-Redhat/Windows, be prepared to get the answer > "Not a supported platform" all the time :-( Unfortunately that seem to apply to most EDA tools. I would recommend to use one of the Redhat clones like CentOS/WhiteBox/StarCom assuming of course you can't afford to buy a Redhat EL license. Hans www.ht-lab.com > for every problem you report/webcase you open, as unrelated to any > distribution the problem can be. It takes persistance to get Xilinx > first level support to realize the problem... > > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 128578
Hi everybody! I did a controller to SRAM, so, I need controller a SDRAM, like it=B4s more difficult, (refresh). I=B4m looking for som code free in vhdl. I have seen one code with double port of xilinx but I have got actel. a big ansker: do you recomend a core about this?, I have a friend that he have bought a core (edif) and he can=B4t enter more things in the FPGA, becouse de edif are in the top, and he can=B4t touch the core. I know that it=B4s sounds bad, but I prefer have the source in vhdl to can modify. anybody know o have done a similar controller? thanksArticle: 128579
"Chris Maryan" <kmaryan@gmail.com> wrote in message news:a8fe60c6-d737-4e13-aa5c-74294c4e4593@j20g2000hsi.googlegroups.com... > I'm trying to understand the intricacies of implementing a ROM in an > FPGA. I've searched around and come up with some useful tidbits, but I > was hoping someone here could clear up a few issues with doing it > "right" for those looking to learn. I would greatly appreciate any > comments on the "correctness" of the following (using VHDL): > > - There seem to be two common ways to do the implementation: one is to > create an array and essentially index into it using a mux, the other > seems to involve generating RAM with predefined values and then > defining it as read-only. There are other coding styles to create a ROM, see the (oldish) paper below although I would stick to whatever is recommended by your synthesis tool. http://www.klabs.org/richcontent/Papers/Mapld99/D2_Kleyner_P.pdf Hans www.ht-lab.com The latter seems to be preferred for large > LUTs (why?). > -- On that note, is there a preferred template for doing the latter? I > know what a RAM template looks like, how does one go about forcing it > to predefined values and setting it to read only? (or is it just a > matter of directing the RAM input/enable ports nowhere) > -- Also, I notice Altera has a ROM megafunction, am I restricted (at > least in terms of ease of creation) to the altera megafunction or is > it relatively easy to roll my own RAM based ROM? > > - Are there any particular considerations if I am looking for a dual > ported ROM? (except for the fact that the megafunction doesn't seem to > support dual ports) > - What about initialization? Right now I have a Matlab file that spits > out text that is formatted such that I can cut and paste. Is there an > easier way with the VHDL file read functions, that still remains > synthesizable? Any considerations in this regard for RAM based versus > mux based? > > For the curious, I'm trying my hand at direct digital synthesis: this > is a 1/2 wave LUT (the other half is just the negative of the first, > done on the fly, I haven't tried to reduce this to 1/4 yet). The dual > ports stem from the need to access the sine and cos portion (phase and > phase-(1/4 wave length) index). > > I realize this topic roughly comes up in one form or another every now > and then, but I am trying to put the knowledge in one place and figure > out how to do it "right" for the sake of learning. > > Thanks, > > ChrisArticle: 128580
On Jan 31, 1:43 pm, merche <dora...@gmail.com> wrote: > Hi everybody! > > I did a controller to SRAM, so, I need controller a SDRAM, like it=B4s > more difficult, (refresh). I=B4m looking for som code free in vhdl. I > have seen one code with double port of xilinx but I have got actel. > > a big ansker: do you recomend a core about this?, I have a friend that > he have bought a core (edif) and he can=B4t enter more things in the > FPGA, becouse de edif are in the top, and he can=B4t touch the core. I > know that it=B4s sounds bad, but I prefer have the source in vhdl to can > modify. > > anybody know o have done a similar controller? > > thanks Hi, Check out the http://www.opencores.org web site and search for sdram_ctrl Rajkumar...Article: 128581
Chris Maryan <kmaryan@gmail.com> writes: > I'm trying to understand the intricacies of implementing a ROM in an > FPGA. I've searched around and come up with some useful tidbits, but I > was hoping someone here could clear up a few issues with doing it > "right" for those looking to learn. I would greatly appreciate any > comments on the "correctness" of the following (using VHDL): > > - There seem to be two common ways to do the implementation: one is to > create an array and essentially index into it using a mux, the other > seems to involve generating RAM with predefined values and then > defining it as read-only. The latter seems to be preferred for large > LUTs (why?). I've always coded the former, and ended up (post-synthesis) with the latter :-) For very small ROMs, the synth tool might not produce a RAM block, unless you provide it with some guidance through attributes or similar. Writing a constant array and then indexing into it is a trivial bit of code, it states clearly to the reader what you want to do and you can leave the "how" bit to the synth tool. <snip> > - What about initialization? Right now I have a Matlab file that spits > out text that is formatted such that I can cut and paste. Is there an > easier way with the VHDL file read functions, that still remains > synthesizable? Any considerations in this regard for RAM based versus > mux based? Write your matlab so that it spits out a file which is valid VHDL, just a package body and the constant you need. Put the package with a deferred constant in a separate file. Then you need only compile your matlab generated file when it changes and rerun your simulation very quickly. I've never had much joy with using external files for initialising values, they work fine for simualation, but synth tools don't support file reading functions, even for init yet... > > For the curious, I'm trying my hand at direct digital synthesis: this > is a 1/2 wave LUT (the other half is just the negative of the first, > done on the fly, I haven't tried to reduce this to 1/4 yet). The dual > ports stem from the need to access the sine and cos portion (phase and > phase-(1/4 wave length) index). > One thing to be aware of if this goes into any kind of system that needs to be robust: You can end up with a corrupted ROM if your clock goes awry: http://groups.google.co.uk/group/comp.arch.fpga/browse_thread/thread/03131539d6475600/4fb4b87a564be8c1#4fb4b87a564be8c1 Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 128582
Nick <tklau@cuhk.edu.hk> writes: > Hi all, > > I am sorry if this problem has been answered but I cannot find much > help from the archive. > > I am using a Spartan3 starter board to interface with a Micron CMOS > Image sensor (MT9T001), and is confused with the output data from the > sensor. > > It outputs 10-bit pixel datum in each pixel clock, but I am wondering > what is the use of the last 2 bits? > > From my understanding, each pixel datum is of 0~255 value (2-to-power-8). > Nope - each pixel is of value 0-1023. It makes it difficult to display what the FPGA can process - there are details that it will pick up that you can't see on the screen (I'd be surprised if your monitor truely has 256 levels of gray you can distinguish anyway :-) It makes data storage a bit more hassle as well, not many formats support 10 bit data and even fewer packages import it. imageMagick is one that can AFAIK, and PGM files can hold 10 bit data. We've seen the benefits of using the bits that are there though! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 128583
On Jan 31, 10:24 am, Rajkumar <shubamshre...@gmail.com> wrote: > On Jan 31, 1:43 pm, merche <dora...@gmail.com> wrote: > > > Hi everybody! > > > I did a controller to SRAM, so, I need controller a SDRAM, like it=B4s > > more difficult, (refresh). I=B4m looking for som code free in vhdl. I > > have seen one code with double port of xilinx but I have got actel. > > > a big ansker: do you recomend a core about this?, I have a friend that > > he have bought a core (edif) and he can=B4t enter more things in the > > FPGA, becouse de edif are in the top, and he can=B4t touch the core. I > > know that it=B4s sounds bad, but I prefer have the source in vhdl to can= > > modify. > > > anybody know o have done a similar controller? > > > thanks > > Hi, > Check out thehttp://www.opencores.orgweb site and search for > sdram_ctrl > > Rajkumar... thanks a lot, i=B4m look the controller that these page. Other thing, why for a dual port to SDRAM? i suppose it=B4s faster.Article: 128584
thanks a lot, i=B4m looking the controller on these page and it=B4s seem easy to understand. Other thing, why for a dual port to SDRAM controller? i suppose it=B4s faster.Article: 128585
thanks a lot, i=B4m looking the controller on these page and it seems use an Altera_mf Library, so i don=B4t know what to do for Actel. Other thing, why for a dual port to SDRAM controller? i suppose it=B4s faster.Article: 128586
Hello, I am working on Actel Fusion FPGA. I am having problems with the ADC in my design. Can someone please help me with this? Thanks alot! Cheers!Article: 128587
Hello All, I am curious what are main applications of FPGA in Telecommunications? It's well known (well, at least for some smart chaps :) ) that DSPs (Digital Signal Processing Systems) can be implemented on FPGAs, but what about their use in Telecommunications? What are main directions, nowdays, for applications of FPGAs in telecommunications?Article: 128588
On 31 Jan, 09:41, "HT-Lab" <han...@ht-lab.com> wrote: > "Uwe Bonnes" <b...@hertz.ikp.physik.tu-darmstadt.de> wrote in message > news:fnqvks$2gi$1@lnx107.hrz.tu-darmstadt.de... > > posedg...@yahoo.com wrote: > > ... > >> It's not problem to run ISE with linux-api module (linux.ko) under > >> FreeBSD btw. > > > If you run on anything non-Redhat/Windows, be prepared to get the answer > > "Not a supported platform" all the time :-( > > Unfortunately that seem to apply to most EDA tools. I would recommend to use > one of the Redhat clones like CentOS/WhiteBox/StarCom assuming of course you > can't afford to buy a Redhat EL license. Maybe the term 'ISE' was a bit misleading. The whole toolchain is possible to run under FreeBSD with linux.ko. Third party download tools eliminates the while USB-oh-so-secret-protocol-mess. Besides I have an idea for jtag download tool which will likely be more smooth in handling. And I rather put my money on that than a neverending circus of driver mess. A tip is to run ISE with Xnest as the display, which seem to eliminate some crashes related with X11 refresh. I would not likely select RedHat anyway disregarding any monetary issues by the following reasons: * Network services enabled by default opens up for all kinds of security issues. * Library incompabilities causes moment 22. * Inmature code inclusion. * inconsistent filesystem layout. * Commercial tie-in, the setup is leaned towards that you must be dependent on RH. (Many other distributions don't have these issues)Article: 128589
Has anyone managed to get the xilinx BSCAN primitives (for interfacing with the USERx jtag registers/comands) working robustly? I've found a depressing lack of information as to what the actual pins do -- aside from a (now unavailable?) techXclusive article, "Reconfiguring Block RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't find much more info. What's the best way to interface with this part? In particular, how do you deal with the obvious synchronization/metastability issues when crossing clock domains, esp. if you're hoping for a device that's still small (i.e. no hardware async fifos or anything). Thanks for any advice you can provide, ...EricArticle: 128590
Hello all, i have a design finished a few month ago, that is working fine on a xc2s200-pq208, but when i port it to a xc3s400-tq144, it ain't work most of the time (depends on the synthesis process) even with lowest frequencies for a single clock and a given period constraint. Now, i wonder, if this is due to wrong regulators. Are there any other good guys here, using those? (If yes, please, tell me Package and Size of Fpga too. :-) much thanks in advance waltherArticle: 128591
On Jan 31, 5:01 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > Nick <tk...@cuhk.edu.hk> writes: > > Hi all, > > > I am sorry if this problem has been answered but I cannot find much > > help from the archive. > > > I am using a Spartan3 starter board to interface with a Micron CMOS > > Image sensor (MT9T001), and is confused with the output data from the > > sensor. > > > It outputs 10-bit pixel datum in each pixel clock, but I am wondering > > what is the use of the last 2 bits? > > > From my understanding, each pixel datum is of 0~255 value (2-to-power-8). > > Nope - each pixel is of value 0-1023. It makes it difficult to > display what the FPGA can process - there are details that it will > pick up that you can't see on the screen (I'd be surprised if your > monitor truely has 256 levels of gray you can distinguish anyway :-) > > It makes data storage a bit more hassle as well, not many formats > support 10 bit data and even fewer packages import it. imageMagick is > one that can AFAIK, and PGM files can hold 10 bit data. > > We've seen the benefits of using the bits that are there though! > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html You can also use the 10 bits to get a little more dynamic range from the camera even if you only display with 8-bit resolution. I have used two approaches to this. One is to set the "digital gain" parameter to 1, 2, or 4. This "gain" selects whether you see the upper 8 bits, the middle 8 bits, or the lower 8 bits respectively. Usually when selecting gain 2 or 4, the FPGA would saturate the pixels where the unused upper bits are not zero. Another approach is a quasi-logarithmic function that translates 10 bits to 8 bits. This is useful for visual images that don't require linearity. It allows you to see some contrast in otherwise dark regions of an image. Regards, GaborArticle: 128592
On Jan 30, 7:06 pm, Falk Brunner <Falk.Brun...@gmx.de> wrote: > sam catalpatechnology com schrieb: > > > Does anyone have a suggestion as to what is broke? Thanks. > > If not a software bug ist looks like a partially broken PROM. > > Regards > Falk The only obvious problem is if you don't select "erase before programming". However this "PROM" is really a flash device and is likely to have a bad block.Article: 128593
"Vagant" <vladimir.v.korostelev@rambler.ru> wrote in message news:48b66280-8f2d-4fa2-877d-ac28b1ca0de8@i7g2000prf.googlegroups.com... > Hello All, > > I am curious what are main applications of FPGA in > Telecommunications? > > It's well known (well, at least for some smart chaps :) ) that DSPs > (Digital Signal Processing Systems) can be implemented on FPGAs, but > what about their use in Telecommunications? > > What are main directions, nowdays, for applications of FPGAs in > telecommunications? > Essay for your tutor is it?Article: 128594
On Jan 31, 5:18=A0pm, "David Spencer" <davidmspen...@verizon.net> wrote: > "Vagant" <vladimir.v.koroste...@rambler.ru> wrote in message > > news:48b66280-8f2d-4fa2-877d-ac28b1ca0de8@i7g2000prf.googlegroups.com... > > > Hello All, > > > I am curious what are main applications of FPGA in > > Telecommunications? > > > It's well known (well, at least for some smart chaps :) ) that DSPs > > (Digital Signal Processing Systems) can be implemented on FPGAs, but > > what about their use in Telecommunications? > > > What are main directions, nowdays, for applications of FPGAs in > > telecommunications? > > Essay for your tutor is it? (How dare you?!...lol) No! I am really curious.Article: 128595
> I am working on Actel Fusion FPGA. > I am having problems with the ADC in my design. > > Can someone please help me with this? More details please :) (I'm not overly-familiar with the ADC, but if you provide a few more details, either I or someone else may be able to help.) K.Article: 128596
Hi all, Has anyone ever tried to improve the security for the old Xilinx FPGA devices, which doesn't have the 3-DES encryption? If so what's the feasible approach ? So far I have no clue TIA,Article: 128597
On Jan 31, 6:24 am, jo...@mit.edu wrote:
> Has anyone managed to get the xilinx BSCAN primitives (for interfacing
> with the USERx jtag registers/comands) working robustly? I've found a
> depressing lack of information as to what the actual pins do -- aside
> from a (now unavailable?) techXclusive article, "Reconfiguring Block
> RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't
> find much more info.
>
> What's the best way to interface with this part? In particular, how do
> you deal with the obvious synchronization/metastability issues when
> crossing clock domains, esp. if you're hoping for a device that's
> still small (i.e. no hardware async fifos or anything).
>
> Thanks for any advice you can provide,
> ...Eric
I used it recently for the 1st time to check out a JTAG interface
block I
was developing. Here's the very simple code I used:
//
----------------------------------------------------------------------
// Xilinx BSCAN
// This is temporary code that allows us to test out JTAG master block
by
// using the Xilinx JTAG block
reg [31:0] bscan_data;
BSCAN_SPARTAN3 u_bscan (
.CAPTURE (BSCAN_CAPTURE),
.DRCK1 (BSCAN_DRCK1),
.DRCK2 (),
.RESET (BSCAN_RESET),
.SEL1 (BSCAN_SEL1),
.SEL2 (),
.SHIFT (BSCAN_SHIFT),
.TDI (BSCAN_TDI),
.UPDATE (BSCAN_UPDATE),
.TDO1 (bscan_data[0]),
.TDO2 (1'b0)
);
always @(posedge BSCAN_DRCK1 or posedge BSCAN_RESET)
if (BSCAN_RESET)
bscan_data <= 32'h87654321;
else if (BSCAN_SHIFT)
bscan_data <= {BSCAN_TDI, bscan_data[31:1]};
The code provides access to a simple shift register. This would be
simple
to extend to a much more functional block, but as you point out,
you'll
need to take care of clock domain crossing, etc.
John Providenza
Article: 128598posedge52@yahoo.com wrote: > On 31 Jan, 00:01, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> > wrote: > > If you run on anything non-Redhat/Windows, be prepared to get the answer > > "Not a supported platform" all the time :-( > > for every problem you report/webcase you open, as unrelated to any > > distribution the problem can be. It takes persistance to get Xilinx > > first level support to realize the problem... > So far I have solved problems without help from Xilinx. And should it > be needed one can always employ helpdesk engineering :) Beside the silly use of WinDriver, I also have no real problems when running on Linux/Suse. And with Micheals work http://www.rmdir.de/~michael/xilinx there is no more need for WinDriver to run Impact. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 128599
On Jan 31, 4:24=A0am, Rajkumar <shubamshre...@gmail.com> wrote: > On Jan 31, 1:43 pm, merche <dora...@gmail.com> wrote: > > anybody know o have done a similar controller? > > > thanks > > Hi, > Check out thehttp://www.opencores.orgweb site and search for > sdram_ctrl > I thought there was an SDRAM controller on opencores as well, but if there is I don't see it. Searching for 'sdram_ctrl' as you suggested comes up empty. 'Memory Controller IP core' seems to be that and more. According to the blurb, it supports SDRAM, SSRAM, FLASH, ROM and many other devices...but I'm guessing that it supports those at the cost of logic resources unless there is a way to parameterize it for the devices that you actually want so you don't end up with SSRAM, FLASH and ROM controllers if you don't happen to need them. There are DDR SDRAM controller out there but those aren't the same thing. I guess if one wants a simple SDRAM controller, one will have to continue the search someplace else. Kevin Jennings
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