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"austin" <austin@xilinx.com> wrote in message news:fhn7u2$1bd1@cnn.xilinx.com... > Luc, > > Contact your disti or FAE. > > Austin Hello Austin (& all) It's this kind of approach that made me drop X and start using Lattice. I find that the Lattice approach is much more upfront - its all on the web and the distribution is used for box shifting (which is about all they are capable of (on a good day)). My heart sinks when a semi company says 'contact the disti of FAE' - in the case of small users like me and the big distributors like X and A use it means 'prepare to plumb new depths of ignorance and/or bad service' For a while X had only one distributor in the UK and that was truly awful. There are 2 now but my limited contact with the new one has not been strong on surpise and delight. Michael KellettArticle: 126251
MyHDL looks really nice!
Is it possible to have in a FSM one procedure-or-function for each
state? It should make the program code easy to read. It will be also
better to have an array of functions and call them according FSM state
number. Do you have any idea how to implement this in MyHDL?
Here is a vivid wishful pseudo-Python example of what I mean:
def read(args):
do smth.
def write(args):
do smth.
...
function = [1:read, 2:write, 3:sleep, 4:wake]
next_state = [1:3, 2:3, 3:3, 4:1]
def FSM_states_switch:
state = next_state[state]
def FSM_output_function:
function[state](args)
Article: 126252Hello, because download was not possible I checked after some tries (as always hecticness) the links - the links are not valid! Webinstall: http://direct.xilinx.com/support/download/http://download.xilinx.com/direct/webpack/92/WebPACK_92i_WebInstall.zip Single File Download: http://direct.xilinx.com/support/download/http://download.xilinx.com/direct/webpack/92/WebPACK_SFD_92i.zip Of course you must first log-in. Then use these links: Webinstall: http://download.xilinx.com/direct/webpack/92/WebPACK_92i_WebInstall.zip Single File Download: http://download.xilinx.com/direct/webpack/92/WebPACK_SFD_92i.zip Greetings UdoArticle: 126253
On Sat, 17 Nov 2007 20:52:59 +0100, Jan Decaluwe wrote:
> The synthesizable RTL subset is what it is. Conceptually, there's little
> to be gained from using MyHDL or whatever instead of VHDL for this.
I think that there is something to be gained from using 'whatever', but it
depends - if you are full-time vhdler working on small or large FPGA
designs then fine; if you are an electronics engineer who on a reasonably
regular basis has an FPGA that needs to be designed/verified then vhdl is
(IMO of course) too complex, and, for test benches in particular, too
cumbersome.
Here is an example of my solution:
# @title Dual UART Tx FPGA
# @description FPGA design with two UART tranamitters that
# continuously transmit data taken from one-hot counters
# @port clk 10MHz clock
# @port nARst Active low reset
# @port txA UART transmit channel A
# @port txB UART transmit channel B
# @marked nARst Use aRst
use berry.if.serial.*;
use berry.util.*;
module DualUartTx() {
inport clk, marked nARst;
outport txA, txB;
reg stateMachine[] = {
async 0 when aRst;
: uartA.wr = 1; uartB.wr = 1; next;
: 0 when uartA.ready & uartB.ready;
}
UartTransmitter uartA(), uartB();
connect uartA aRst, baudClk(clk115.out), data(cntA), tx(txA);
connect uartB aRst, baudClk(clk96.out), data(cntB), tx(txB);
PulseGen clk115(DIV = 10e6 / 115200), clk96(DIV = 10e6 / 9600);
onehot reg cntA[%8] = {async 0 when aRst; next when uartA.wr;}
onehot reg cntB[%8] = {async 7 when aRst; prev when uartB.wr;}
connect SyncARst() in(! marked nARst), out(node aRst);
DualUartTxConstraints();
}
and here is another example:
# @title Stopwatch
# @description A stopwatch with tenths, seconds, and tens of seconds.
# @port tenths Tenths of seconds, inverted one-hot encoded
# @port ones Seconds encoded to drive a seven segment display
# @port tens Tens of seconds encoded to drive a seven segment display
module StopWatch() {
inport clk, aRst, clk100ms; startStop;
outport tens[%7], ones[%7], tenths[%10];
reg stateMachine[] = {
async 0 when aRst;
: next when startStop;
: tenthsCnt.inc = 1 when clk100ms; next when !startStop;
: tenthsCnt.inc = 1 when clk100ms; next when startStop;
: 0 when !startStop;
}
onesCnt.inc = tenthsCnt.rollover = 1 when tenthsCnt.inc & tenthsCnt == 9;
tensCnt.inc = onesCnt.rollover = 1 when onesCnt.inc & onesCnt == 9;
tensCnt.rollover = 1 when tensCnt.inc & onesCnt == 5;
reg tenthsCnt[%4], onesCnt[%4], tensCnt[%3] = {
node rollover, inc; async 0 when aRst; 0 when rollover; next when inc;
}
const SEVEN_SEG_DECODE[10] = { 0x79, 0x24, 0x30, 0x19, 0x12, 0x02, 0x78,
0x00, 0x10, 0x08 };
tens = SEVEN_SEG_DECODE[0 .. 5] when tenthsCnt == 0 .. 5; ones =
SEVEN_SEG_DECODE[0 .. 9] when onesCnt == 0 .. 9;
node tenthsDec[%10] = 1 << 0 .. 9 when tenthsCnt == 0 .. 9;
tenths = !tenthsDec;
}
> If you like dynamic languages (not everybody does), you'll enjoy
> using MyHDL/python especially during verification. There you can
> use the full power of python, which is in my opinion invariably
> useful. Combined with a unit test framework such as py.test,
> verification almost becomes fun :-)
I would agree with that idea - unit testing + general purpose scripting
language as a basis for verification. I would also like a nice editor
with auto compile (as in eclipse), oh, and with auto-completion too :-)
Regards,
Paul.
Article: 126254
In article <A35%i.17632$pr6.16558@newsfe06.phx>,
Colin Hankins <Colin.Hankins@touit.com> wrote:
>My particular interest developed in the
>Lattice ECP2M because I need a FPGA/SERDES combo and the price for the ECP2M
>seems unbelievable compared to their competitor's equivalent FPGAs.
How about Altera's Aria GX? The 60K LE device is $262.50 from Arrow, about
the same as the 70K device from Lattice. The SERDES in the Lattice device
looks better (and there are more of them), but Altera's synthesis tools are
better. The free web edition software supports this device.
I know they support x4 PCIe, if that's why you need the SERDES.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 126255MK, Sorry to hear you feel this way. I would hope that contacting your Xilinx distributor would result in useful and helpful information. If not, we would certainly like to know. "Being small" has many disadvantages, but I have to say that many FPGA sockets are created by 'small' businesses. To that end I would hope that our distributors are doing the job we expect them to do by providing you with the services you require. Sounds like that did not happen. Perhaps this is something we should be aware of? As always, Peter an I stand ready to listen (and act). AustinArticle: 126256
I think there's often a problem of poor communication. Here are some examples from my own experience (working alone, not as part of a large company): ----------------------------------------- Altera: I'm involved in developing with this vendor's products (mainly because I came across Altera first), so I have most experience with them. I can find all the information I need and the basic documentation is very good. The dev kits are excellent, but the accompanying example code makes you wonder if they know what they're doing. I've found the field engineers to be very helpful, but...I feel repelled from this vendor because of the hassle in installing tools (registering against a fixed MAC address and so on) and, if I want to register on their site, I must promise to keep Altera informed of my career moves for ever and ever (which I refuse to do). This has pushed me to look at other suppliers. ----------------------------------------- Lattice: Despite the abysmal experience of a visit by the UK/Ireland Sales manager, I was still keen to learn of competing products, so I attended a seminar arranged by a distributor. This was excellent, so I made enquiries about buying a development kit. It seemed that the XP10 demo board would be best and the distributor was offering this at the "special" price of $555. Just to make sure I knew what I was getting (since there were two dev boards with the XP10), I enquired to confirm that this was the "LatticeXP Advanced Evaluation Board". The answer came back "The special offer relates to the "Standard" XP board". In other words, the distributor wanted to charge $555 (their "special" price") for the board which Lattice advertised on their web site for $229. Bye-bye, Lattice. A narrow escape there, but at least we didn't waste $555 on a dev kit which is (as I understand it), an oscillator, an FPGA and a few LEDs. ----------------------------------------- Xilinx: Another excellent seminar organised by a distributor and a great dev board advertised there for an great price ($199). So I enquired at the seminar... I was referred to someone else who was there and given that person's business card. The seminar was nearly done and he was busy, so I decided to e-mail him when I got home. He telephoned and asked me to contact their sales office. Nothing like giving the customer a chance to get away, eh? So, I e-mailed the sales office the same day (4th June), quoting the exact product reference. They replied by sending me a quotation which estimated delivery on 4th August and telling us not to pay but to apply for a credit account, giving our company registration number, VAT registration number, postal code, telephone number, fax number, trading names, a trade referee (with telephone number and fax number), a second trade referee (with telephone number and fax number) - all this to buy a development kit for about $199. Am I in a parallel universe? I reach into my pocket for $199. I don't waste my time making credit account applications. The same product was available in stock at Digi-Key for a few dollars more, so we ordered it and it came the same week (from a different continent). Which would you choose? Digi-key (21st century) or the distributor (19th century)? On 17th July, the distributor e-mailed us (as an attendee at the seminar) to ask if we wanted to buy any of the Xilinx development kits. I think you can guess our reply. So, maybe the kit is good (I haven't yet had time to do more than check that it seems to work), but I feel that we don't have a distributor of any serious value to us, so would it actually be much use switching it on? ----------------------------------------- As ever, the chief problem with all the vendors is that, if you want to know about prices, the response is typically the robotic, unblinking face, saying "We can talk about prices...tell us about your application...". >MK, > >Sorry to hear you feel this way. > >I would hope that contacting your Xilinx distributor would result in >useful and helpful information. > >If not, we would certainly like to know. > >"Being small" has many disadvantages, but I have to say that many FPGA >sockets are created by 'small' businesses. To that end I would hope >that our distributors are doing the job we expect them to do by >providing you with the services you require. > >Sounds like that did not happen. Perhaps this is something we should be >aware of? > >As always, Peter an I stand ready to listen (and act). > >AustinArticle: 126257
On Nov 17, 11:58 pm, radarman <jsham...@gmail.com> wrote: > I noticed that the Xilinx webpack version of ISE now runs in Linux. I > seem to recall in the past that the webpack was a Windows only tool, > so this seems like a signficant shift. > > Does anyone know if Altera has any plans to release a Quartus webpack > for Linux? I still prefer Altera devices for my hobby work even though > my current employer is 100% Xilinx. However, I'm looking down the > barrel of Vista on my next system, and while I would prefer to migrate > to Linux, I can't justify buying a license for Quartus to play at > home. > > I suppose the other alternative is to bite the bullet, put my Altera > dev boards away, and migrate to Xilinx dev boards. Just curious, why do you prefer Altera devices for hobby work? -Dave PollumArticle: 126258
On 17 Nov., 23:27, John Retta <jre...@rtc-inc.com> wrote:
> [1] As others suggest, make sure that all
> inputs are known ... not X. X in results in
> X out.
>
> [2] The test bench should initialize memory
> first, then read data, OR use the initialization
> attributes of the BLKRAM to initialize values.
> I would try the latter first, since if you are
> relatively new to simulation, you can get the
> READ working before the WRITE.
>
> Take a look at your install directory
> /xilinx/doc/usenglish/books/docs/lib.pdf
> the section on RAMB for the syntax of initializing
> the device contents in your respective language
> (Verilog or VHDL).
>
> [3] You may have to add delays to your nets for
> some of your incoming signals relative to your
> clk. The unisim models perform timing checks, and
> if you violate setup and hold (as you do for RTL
> sims ... who cares ... we the sim model does),
> the model outputs X.
>
> [4] The suggestion to use inference of memories
> is a good one. For many years I instantiated
> BLKRAMs .... my rationale was I synthesized exactly
> what I wanted ... this was based on earlier
> experience of fighting tools to synthesize a
> certain configuration of memory. Anyway,
> a friend let me know this was terribly inefficient
> from a simulation point of view ... and I
> disagreed. So I coded up a testbench for
> bench marking purposes of instantiated blkram
> vs inferred memory, and the instantiated
> blkram ran 5x slower.
>
> Now if you were to pay your tool vendor for
> a simulator with 5x performance improvement,
> you might go bankrupt.
>
> --
>
> Regards,
> John Retta
> Owner and Designer
> Retta Technical Consulting Inc.
>
> Colorado Based Xilinx Consultant
>
> phone : 303.926.0068
> email : jre...@rtc-inc.com
> web : www.rtc-inc.com
thanks for all the replies.
well of course i checked my input signals and i applie values to them.
the rd and wr signals are good aswell as the clk and
the address signal (good meaning that they have a defined level
(either '0' of '1' applied to them)).
a strange thing is that the data_in signal has all 'U' althoug i apply
for example all '0' to it.
this is probably the reason that when i write to the memory and then
read from the same address i get all 'U' in my data_out.
any idea whats wrong here?
entity spi_memory is
PORT ( CLK : in STD_LOGIC;
Data_in : inout STD_LOGIC_VECTOR (31 downto 0);
Data_out : inout STD_LOGIC_VECTOR (31 downto 0);
Address : in STD_LOGIC_VECTOR (9 downto 0);
WR : in STD_LOGIC;
RD : in STD_LOGIC);
end spi_memory;
architecture Behavioral of spi_memory is
signal s_write_strobe : std_logic;
type mem_array is array(0 to 1023) of std_logic_vector(31 downto 0);
signal ram : mem_array;
signal rd_addr_ram : std_logic_VECTOR(9 downto 0);
begin
wr_p: process(CLK, Data_in)
begin
if rising_edge(CLK) then
if s_write_Strobe = '1' then
ram(to_integer( unsigned ( Address ))) <= Data_in;
end if;
end if;
end process wr_p;
rd_p: process(CLK, Address)
begin
if rising_edge(CLK) then
rd_addr_ram <= Address;
end if;
end process rd_p;
Data_Out <= ram(to_integer( unsigned( rd_addr_ram )));
GENERATE_WRITE_STROBE: process(WR, RD, Address)
begin
s_write_strobe <= '0';
if RD = '0' and WR = '1' and Address >= "0000001010" then
s_write_strobe <= '1';
end if;
end process GENERATE_WRITE_STROBE;
end Behavioral;
i drive the data_in signal from the outside testbench..
thanks urban
Article: 126259<hershkoy@gmail.com> wrote in message news:785b48e0-35da-47fa-b4b8-54e4e31ea9ae@c30g2000hsa.googlegroups.com... > Hi, > > I have a verilog module in my project, which is instantiated in the > design 3 times, each time with different parameters. I generated 3 > different vqm files outside the Quartus project (with Synplify), one > for each instantiation. How can I tell Quartus which vqm file should > be linked to its appropriate block? > By writing the code that instantiates the blocks KJArticle: 126260
"rickman" <gnuarm@gmail.com> wrote in message news:b79b7e6e-7cc1-4501-9a8e-92e7f6b84f6a@l1g2000hsa.googlegroups.com... > On Nov 17, 9:12 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: >> "Hal Murray" <hal-use...@ip-64-139-1-69.sjc.megapath.net> wrote in >> message >> >> news:i7adnXA_7OEPGKLanZ2dnUVZ_ujinZ2d@megapath.net... >> > > But aren't you making an assumption that "the design functions as you > want"? The OP may not have complained that it did not simulate > correctly or that it did not meet performance. However, he is clearly > concerned that it is not implementing as he requires. > The OP said nothing about the function being incorrect, since he is designing it he is responsible for job #1 which is getting the function correct. To quote from the OP, the concern is... "Warning: Inferred RAM node "ram~0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." The addition of pass-through logic being added to match behaviour is a 'good' thing. What is the alternative? Not adding the logic and creating something that functions differently? KJArticle: 126261
"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message news:LL6dne-J2bj1T6LanZ2dnUVZ_trinZ2d@megapath.net... > > > I want warnings when I might be doing something wrong or even slightly > fishy. > So do I, but one must deal with overly chatterly tools at times. > Leaving them alone is not a sensible approach if there are more than a > few. > The clutter gets in the way of finding important warnings. > The original post's complaint is.... "Warning: Inferred RAM node "ram~0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." Post your sensible approach that does not change the function. KJArticle: 126262
Didi wrote: >> So ask Xilinx for the info, explain you are manufacturing device >>programmers. >> >> If they prove too hard to work with, you could try Atmel etc >>They have appx equivalent devices to the smaller XPLA3 > > > Well thanks, Jim, sounds encouraging. Have not wasted any time talking > programming data to their support for years, time to try again may be. > I strongly suspect I know what the result will be, though. > > >> It means that progamming documents must exist, and be sent to the >>programmer manufacturers. > > > Are you saying you can program a Coolrunner using a non-Xilinx > programmer and a _JEDEC_ file? Without the programmer using > (or asking you to use) some paid Xilinx software to do some > fuse address mapping? > Generally this is the question Xilinx' documents do not > answer (and seem to deliberately obscure). Yes. On my EE Tools ChipMAx and TopMAX, I can load a std JED file (which typically does need Xilinx/Vendor tools to generate :) and then I can Pgm Xc2C XCR, XCS Coolrunner devices ( as well as CPLD from Altera, Atmel, Lattice, etc,so they have the Programming specs from all those suppliers ) The fuse address mapping, is included in the Programming Document, so the Device programmer handles that (and does the reverse process, when it reads the CPLD and saves to a JED file) It will also vector test, which just needs a simple pin-mapping. On the documents I've seen, it aligns reasonably well with the JED - often they vary Pgm block sizes, and round to boundaries, and security can differ. > >> A working device programmer is also not a bad way to reality-check your >>work. >> eg You can pgm a part, and then confirm you can read it in your system, >>and then pgm in your system, and read/save the result, to analyse if >>some bits are in the wrong place. > > > Oh I do not need that, last time I did it for the original Coolrunner > it took me weeks rather than months to do the whole thing having > just the data and a few chips. It totally took me about 3 months > to write a suitable logic compiler (similar - not directly > compatible - to PHDL, but more flexible/powerful, with all the DPS > scripting. macros etc.) and some reverse engineering I had to do > because I did not have all the data (Philips were easier to deal > with than Xilinx - I guess everyone is that - but sent me only > _most_ of the data, omitted a significant part of them...). > Programming a device via JTAG is a lot easier than they make > it sound (and cash in for), one just needs the device documentation. I didn't think you _needed_ it, just that it can be useful to save time... :) -jgArticle: 126263
psihodelia@googlemail.com wrote:
> MyHDL looks really nice!
> Is it possible to have in a FSM one procedure-or-function for each
> state? It should make the program code easy to read. It will be also
> better to have an array of functions and call them according FSM state
> number. Do you have any idea how to implement this in MyHDL?
Depends on what "implement" means.
For pure modelling with MyHDL, you can use python's full power.
For code intended for conversion to Verilog/VHDL, there are very
severe restrictions, similar to those for synthesizable RTL code.
(Conversion support is intended to provide a path to hardware
implementation.) Such code will look similar to RTL code in other
languages.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 126264On Sun, 18 Nov 2007 14:03:09 -0500, "KJ" <kkjennings@sbcglobal.net> wrote: > >"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message >news:LL6dne-J2bj1T6LanZ2dnUVZ_trinZ2d@megapath.net... >> >> >> I want warnings when I might be doing something wrong or even slightly >> fishy. >> >So do I, but one must deal with overly chatterly tools at times. > >> Leaving them alone is not a sensible approach if there are more than a >> few. >> The clutter gets in the way of finding important warnings. >> > >The original post's complaint is.... > >"Warning: Inferred RAM node "ram~0" from synchronous design logic. >Pass-through logic has been added to match the read-during-write >behavior of the original design." > >Post your sensible approach that does not change the function. Not that I'm advocating it but in this specific case the solution might be to modify the design so that it doesn't do "read-during-write" which the underlying memory doesn't support. RDW probably isn't needed, most probably it makes the resulting design larger and slower because of the added logic. Unless it is absolutely needed for lower latency it can be removed by changing the design.Article: 126265
> For pure modelling with MyHDL, you can use python's full power. > > For code intended for conversion to Verilog/VHDL, there are very > severe restrictions, similar to those for synthesizable RTL code. > (Conversion support is intended to provide a path to hardware > implementation.) Such code will look similar to RTL code in other > languages. > > Jan > Hmm... It is very serious restriction. I did imagine MyHDL to be more powerful. MyHDL is just a wrapper?Article: 126266
Mike, I will look into this experience of the demo board. In general, the field is asked to find out what the customer needs (it helps us design better products), so it is unlikely that the field will stop asking for information. If sales or marketing asks me to design in a new feature, they have to have conducted a study to convince us that it is worth the millions of dollars it takes to do anything nowadays. However, I agree, that if all you want to do is buy something already researched, identified, etc. life is often not easy anymore (from tennis shoes to FPGAs). Thanks for taking the time to let us know how all of the FPGA vendors fare through their distributors. We don't often get that sort of feedback. AustinArticle: 126267
On Sun, 18 Nov 2007 11:54:41 -0800 (PST), "psihodelia@googlemail.com" <psihodelia@googlemail.com> wrote: >> For pure modelling with MyHDL, you can use python's full power. >> >> For code intended for conversion to Verilog/VHDL, there are very >> severe restrictions, similar to those for synthesizable RTL code. >> (Conversion support is intended to provide a path to hardware >> implementation.) Such code will look similar to RTL code in other >> languages. >> >> Jan >> > >I did imagine MyHDL to be more powerful. That's exactly the problem. The difficulty is with converting those powerful semantics to RTL which is called behavioral synthesis which is still an open research topic in most instances. Some top eda companies have tried and failed in the past and now C synthesis is being tried again with limited success. You can't expect myhdl to include a top notch behavioral synthesis feature; yet hopefully.Article: 126268
Jim, > The fuse address mapping, is included in the Programming Document, > so the Device programmer handles that > (and does the reverse process, when it reads the CPLD and saves to a JED > file) > It will also vector test, which just needs a simple pin-mapping. > > On the documents I've seen, it aligns reasonably well with > the JED - often they vary Pgm block sizes, and round to boundaries, > and security can differ. they are cheating somehow. Their document on Coolrunner-II programming states: "The Excel fuse map file indicates the bit position of each bit of fuse data in the ISC Register. Each column in the fuse map represents a device address. Each row represents a bit in the ISC Register. The leftmost column is ordinal address 0. The uppermost row is ISC Register data bit location 0. " This is pretty much what I have on the original coolruner, the .xls file which allowed me to do jedec file -> jtag stream. Not available anywhere from xilinx - I looked pretty hard. So either the programmer manufacturers have been "party members" and have been given these data or there is some other cheating going on. Can you please verify that you can program a jedec file to a coolrunner on a PC which does not have the Xilinx software on it? While being disconected from the net, that is... If it works, I may apply for party membership at 52 for the first time, who knows.... :-). Thanks a lot, Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ On Nov 18, 9:03 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Didi wrote: > >> So ask Xilinx for the info, explain you are manufacturing device > >>programmers. > > >> If they prove too hard to work with, you could try Atmel etc > >>They have appx equivalent devices to the smaller XPLA3 > > > Well thanks, Jim, sounds encouraging. Have not wasted any time talking > > programming data to their support for years, time to try again may be. > > I strongly suspect I know what the result will be, though. > > >> It means that progamming documents must exist, and be sent to the > >>programmer manufacturers. > > > Are you saying you can program a Coolrunner using a non-Xilinx > > programmer and a _JEDEC_ file? Without the programmer using > > (or asking you to use) some paid Xilinx software to do some > > fuse address mapping? > > Generally this is the question Xilinx' documents do not > > answer (and seem to deliberately obscure). > > Yes. On my EE Tools ChipMAx and TopMAX, I can load a std JED file > (which typically does need Xilinx/Vendor tools to generate :) > and then I can Pgm Xc2C XCR, XCS Coolrunner devices > ( as well as CPLD from Altera, Atmel, Lattice, etc,so they have the > Programming specs from all those suppliers ) > > The fuse address mapping, is included in the Programming Document, > so the Device programmer handles that > (and does the reverse process, when it reads the CPLD and saves to a JED > file) > It will also vector test, which just needs a simple pin-mapping. > > On the documents I've seen, it aligns reasonably well with > the JED - often they vary Pgm block sizes, and round to boundaries, > and security can differ. > > > > > > >> A working device programmer is also not a bad way to reality-check your > >>work. > >> eg You can pgm a part, and then confirm you can read it in your system, > >>and then pgm in your system, and read/save the result, to analyse if > >>some bits are in the wrong place. > > > Oh I do not need that, last time I did it for the original Coolrunner > > it took me weeks rather than months to do the whole thing having > > just the data and a few chips. It totally took me about 3 months > > to write a suitable logic compiler (similar - not directly > > compatible - to PHDL, but more flexible/powerful, with all the DPS > > scripting. macros etc.) and some reverse engineering I had to do > > because I did not have all the data (Philips were easier to deal > > with than Xilinx - I guess everyone is that - but sent me only > > _most_ of the data, omitted a significant part of them...). > > Programming a device via JTAG is a lot easier than they make > > it sound (and cash in for), one just needs the device documentation. > > I didn't think you _needed_ it, just that it can be useful to save > time... :) > > -jgArticle: 126269
Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.1.1 which supports reload now. http://www.dspia.com/gtkwave.htmlArticle: 126270
Didi wrote: > Jim, > > >>The fuse address mapping, is included in the Programming Document, >>so the Device programmer handles that >>(and does the reverse process, when it reads the CPLD and saves to a JED >>file) >>It will also vector test, which just needs a simple pin-mapping. >> >>On the documents I've seen, it aligns reasonably well with >>the JED - often they vary Pgm block sizes, and round to boundaries, >>and security can differ. > > > they are cheating somehow. > Their document on Coolrunner-II programming states: > > "The Excel fuse map file indicates the bit position of each bit > of fuse data in the ISC Register. Each column in the fuse map > represents a device address. Each row represents a bit in the > ISC Register. The leftmost column is ordinal address 0. The > uppermost row is ISC Register data bit location 0. " > > This is pretty much what I have on the original coolruner, the > .xls file which allowed me to do jedec file -> jtag stream. > Not available anywhere from xilinx - I looked pretty hard. > > So either the programmer manufacturers have been "party members" > and have been given these data Yes. They don't have the time, or inclination, to reverse engineer ! If Xilinx wants device programmer support, they must provide the info. (as do all the chip vendors) > or there is some other cheating going on. > Can you please verify that you can program a jedec file to > a coolrunner on a PC which does not have the Xilinx software > on it? While being disconected from the net, that is... > If it works, I may apply for party membership at 52 for > the first time, who knows.... :-). > > Thanks a lot, I'm not sure what you are expecting, the flow IS pretty simple : [I suspect you are being too paranoid :) ? ] eg : I trawl my PC for a Xilinx JED file, and find this D:\Xilinx\DesignPaths\Design.JED: Programmer Jedec Bit Map Date Extracted: Wed Apr 30 21:16:51 2007 QF25808* QP56* QV0* F0* X0* J0 0* N DEVICE XC2C64-4-CP56* Note Block 0 * Note Block 0 ZIA * L000000 1110110011111111* L000016 1110101011111111* <snip> Note Block 3 I/O Macrocell Configuration 27 bits * N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu* L025360 000001111001111100010000001* L025387 000001111001111100010000001* L025414 000001111001111100010000001* L025441 000001111001111110011111100* L025468 000001111001111101110000001* L025495 000001111001111110011111100* L025522 000001111000011100011111100* L025549 000001111001111110011111100* L025576 000001111001111110011111100* L025603 000001111000011100011111100* L025630 000001111001111110011111100* L025657 000001111001111110011111100* L025684 000001111001111110011111100* L025711 000001111001111110011111100* L025738 000001111001111110011111100* L025765 000001111001111110011111100* Note Globals * Note Global Clock Mux * L025792 100* Note Global Set/Reset Mux * L025795 00* Note Global OE Mux * L025797 11111111* Note Global Termination * L025805 0* Note Input Voltage Standard for IOB * L025806 1* Note Output Voltage Standard for IOB * L025807 1* Then, on ChipMAX I just Select XC2C64A & File-Open gives this : -XILINX XC2C64A selected. -File loading... -File load success. -Buffer checksum : 9832h -File checksum : 9832h -Blow Count : 24180 and I can see and edit the fuses, by JED number. So, it is a simple Load process, and no, there is no translation process needed. The Programming data used by the Pgmr Vendor, handles all that (and also the converse on read-save-to-JED, as I mentioned ) What I cannot do with Xilinx tools (that I can with Atmel) is Vector Test the programmed device, but that's a side issue. -jgArticle: 126271
radarman <jshamlet@gmail.com> wrote: > I noticed that the Xilinx webpack version of ISE now runs in Linux. I > seem to recall in the past that the webpack was a Windows only tool, > so this seems like a signficant shift. > Does anyone know if Altera has any plans to release a Quartus webpack > for Linux? I still prefer Altera devices for my hobby work even though > my current employer is 100% Xilinx. However, I'm looking down the > barrel of Vista on my next system, and while I would prefer to migrate > to Linux, I can't justify buying a license for Quartus to play at > home. > I suppose the other alternative is to bite the bullet, put my Altera > dev boards away, and migrate to Xilinx dev boards. Xilinx own all parts of the software the constitute ISE. They can distribute without additional costs. Other vendors need external programms, where the external vendor probably charges real money for the Linux version. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 126272
> I'm not sure what you are expecting, the flow IS pretty simple : > [I suspect you are being too paranoid :) ? ] Of course I am paranoid - and I do not think I can be nearly enough that when it comes to xilinx programming data... > > eg : I trawl my PC for a Xilinx JED file, > and find this > > D:\Xilinx\DesignPaths\Design.JED: > ... Are you sure you don't have the xilinx paid software installed somewhere on that PC? If this is the case we cannot tell whether there is no fuse address mapping going on behind the scenes (transparent at user level). They would be less likely to do that over the net as this would be way easier to catch, but it would take an unplugged RJ-45 to make sure :-). Please keep the issue in background and keep me posted if you stumble across some related news (I seldomly read com.arch.fpga but a do read pretty often comp.arch.embedded). I would have tried to talk to some other vendor if anyone else had a coolrunner-like part (practically 0 static power), sadly xilinx bought the philips line only to shut it down - and now I cannot do what I could do while there were Philips devices. I'll try to ask xilinx support for the .xls document which translates jedec address <-> jtag_stream_bit_offset; I wonder how many millions/quarter revenue they'll ask me to make for them this time before they consider my chance of getting the data (last time I asked it was $20M/quarter). Thanks again, Dimiter P.S. I keep on wondering how come CPLD/FPGA manufacturers can get away with selling non-documented devices, if a CPU vendor would try to sell a processor and supply only a C compiler for it and no instruction set he would stand no chance (at least in todays world, not so sure about tomorrows...) ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ On Nov 19, 12:24 am, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Didi wrote: > > Jim, > > >>The fuse address mapping, is included in the Programming Document, > >>so the Device programmer handles that > >>(and does the reverse process, when it reads the CPLD and saves to a JED > >>file) > >>It will also vector test, which just needs a simple pin-mapping. > > >>On the documents I've seen, it aligns reasonably well with > >>the JED - often they vary Pgm block sizes, and round to boundaries, > >>and security can differ. > > > they are cheating somehow. > > Their document on Coolrunner-II programming states: > > > "The Excel fuse map file indicates the bit position of each bit > > of fuse data in the ISC Register. Each column in the fuse map > > represents a device address. Each row represents a bit in the > > ISC Register. The leftmost column is ordinal address 0. The > > uppermost row is ISC Register data bit location 0. " > > > This is pretty much what I have on the original coolruner, the > > .xls file which allowed me to do jedec file -> jtag stream. > > Not available anywhere from xilinx - I looked pretty hard. > > > So either the programmer manufacturers have been "party members" > > and have been given these data > > Yes. They don't have the time, or inclination, to reverse engineer ! > > If Xilinx wants device programmer support, they must provide the info. > (as do all the chip vendors) > > > or there is some other cheating going on. > > Can you please verify that you can program a jedec file to > > a coolrunner on a PC which does not have the Xilinx software > > on it? While being disconected from the net, that is... > > If it works, I may apply for party membership at 52 for > > the first time, who knows.... :-). > > > Thanks a lot, > > I'm not sure what you are expecting, the flow IS pretty simple : > [I suspect you are being too paranoid :) ? ] > > eg : I trawl my PC for a Xilinx JED file, > and find this > > D:\Xilinx\DesignPaths\Design.JED: > > Programmer Jedec Bit Map > Date Extracted: Wed Apr 30 21:16:51 2007 > QF25808* > QP56* > QV0* > F0* > X0* > J0 0* > N DEVICE XC2C64-4-CP56* > > Note Block 0 * > Note Block 0 ZIA * > L000000 1110110011111111* > L000016 1110101011111111* > <snip> > Note Block 3 I/O Macrocell Configuration 27 bits * > N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 > RegCom Oe:4 Tm Slw Pu* > L025360 000001111001111100010000001* > L025387 000001111001111100010000001* > L025414 000001111001111100010000001* > L025441 000001111001111110011111100* > L025468 000001111001111101110000001* > L025495 000001111001111110011111100* > L025522 000001111000011100011111100* > L025549 000001111001111110011111100* > L025576 000001111001111110011111100* > L025603 000001111000011100011111100* > L025630 000001111001111110011111100* > L025657 000001111001111110011111100* > L025684 000001111001111110011111100* > L025711 000001111001111110011111100* > L025738 000001111001111110011111100* > L025765 000001111001111110011111100* > > Note Globals * > Note Global Clock Mux * > L025792 100* > > Note Global Set/Reset Mux * > L025795 00* > > Note Global OE Mux * > L025797 11111111* > > Note Global Termination * > L025805 0* > > Note Input Voltage Standard for IOB * > L025806 1* > > Note Output Voltage Standard for IOB * > L025807 1* > > Then, on ChipMAX I just Select XC2C64A & File-Open gives this : > > -XILINX XC2C64A selected. > -File loading... > -File load success. > -Buffer checksum : 9832h > -File checksum : 9832h > -Blow Count : 24180 > > and I can see and edit the fuses, by JED number. > > So, it is a simple Load process, and no, there is no translation > process needed. The Programming data used by the Pgmr Vendor, handles > all that (and also the converse on read-save-to-JED, as I mentioned ) > > What I cannot do with Xilinx tools (that I can with Atmel) > is Vector Test the programmed device, but that's a side issue. > > -jgArticle: 126273
Specification EDK version:8.2i FPGA Board: Virtex II Pro I've tried generating a linker script to map the input object files (.text, .rodata, .sdata2, .data , .sdata, .sbss, .bss ) on to RAM (DDR_256MB_32MX64) and used the linker symbol _TEXT_START_ADDR to modify the starting address of my program. However, these instructions are when using mb-gcc compiler. A very simple program has been written to display a simple output using xil_printf() which works on the default memory settings but not when the linker script is used to map object files to RAM. Are there any suggestions on to how this can be done? PriyanthaArticle: 126274
On Nov 18, 5:36 pm, Bathala <priyanth...@gmail.com> wrote: > I've tried generating a linker script to map the input object files > (.text, .rodata, .sdata2, .data , .sdata, .sbss, .bss ) on to RAM > (DDR_256MB_32MX64) and used the linker symbol _TEXT_START_ADDR to > modify the starting address of my program. However, these instructions > are when using mb-gcc compiler. If you just want to run from RAM and aren't trying to do anything weird (like put text in ROM, some data in fast RAM and other data in slow RAM on alternate Tuesdays), just use the default linker script and set the Program Start Address, Stack and Heap size. This puts text followed by data followed by stack followed by heap in one big block starting from the given start address. These options are set with right click on Applications tab/Project, then select Set Compiler Options... Uncheck Use Custom Linker Script. Remember, you can't load external RAM from an fpga boot prom. You must load it with XMD or your own loader. If you are doing something weird, someone else is going to have to help you. Alan Nishioka
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