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fbv999@gmail.com writes: > I can hardly beleive, that when a single FPGA may cost up to 2000$, You apparently haven't looked at the low-quantity pricing of the very large FPGAs. It would be really nice if they could be purchased for only $2000. > there is no space for a few hundred kilo- maybe megabytes of > information in an age, when a terabyte costs around a few 100$s. Or > does it generate such a big traffic, without return o investment? > Someone tell me please the mail address of the marketing and financial > freaks at Xilinx! I would like to donate them my PC and a portion of > my 512kpbs bandwith for the purpuse... What are you blathering on about?Article: 128851
Antti <Antti.Lukats@googlemail.com> wrote: >On 7 Feb., 18:37, Sky46...@trline5.org wrote: >> Which I/O mode like LVDS_25 etc.. is suitable to interface USB on a Spartan-3 >> FPGA ..? (I know the single ended signaling within USB). >> >> The idea being to eliminate any external usb transceiver. >bad idea >it is possible and has been done, but its not recommended >and should not be attempted for any commercial product. What are the catches, and which speeds are at least possible ..? I'm considering this mainly for prototyping. I noticed no differential modes for 3.3V are available directly. So either one have to (ab)use two LVCMOS33/LVTTL or run Vcco=3.3V in conjuction with a differential mode. How does a mode like LVDS_25 behave with Vcco=3.3V btw?Article: 128852
USB2 chip is now down to less than $1. Why would you choose to suffer? AustinArticle: 128853
This datasheet is only available under NDA with NVidia. Xilinx cannot make this datasheet available and you will have to contact NVidia to get access to it. - Peter GaLaKtIkUs(tm) wrote: > Hi everybody > I had the intention to buy an ML410 board but the local Xilinx > reseller told me that there is a problem concerning the ALi M1535D+ - > there is no documentation given with the board. But in the > documentation (ug085.pdf - ML410 Embedded Development Platform User > Guide (v1.7) September 28, 2007) is stated that the datasheet is > located on the documentation CDROM accompanying the board. > Unfortunately this datasheet is not published on the internet (ie. > under NDA). > > My questiion is: does this problem really exist or the resseller is > wrong? if the problem exists is it possible to contact ALi (nowadays > NVidia I think) to get the datasheet? > > Thanks in advance for answer > MehdiArticle: 128854
On Jan 27, 11:51 pm, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > I took a quick look at your webpage [1] and have a few questions: > > Do you have a C-compiler for your processor? (You only say that it is > programmable in a high-level language on your webpage.) No, it's not C ... > Do you know if commercial compilers for Z80 and 8051 will produce better > results than sdcc? I don't have access to comercial compilers for Z80/8051. > I also note that the 8051 results were done with 6 clocks per machine > cycle. AFAIK there are much faster 8051 cores available. Yes, I know. The 8051 simulator I've used ( 8051sim) computes the cycles based on the original timing. I saw 2X cores which are just twice faster. The one called "single cycle" do not execute all the instruction in a single cycle (i.e. timing is dependent on the instruction, I think I saw 1-4) so you really need a core simulator. -- mmihaiArticle: 128855
On Feb 7, 10:06 pm, Peter Ryser <peter.ry...@xilinx.com> wrote: > This datasheet is only available under NDA with NVidia. Xilinx cannot > make this datasheet available and you will have to contact NVidia to get > access to it. > > - Peter > > GaLaKtIkUs(tm) wrote: > > Hi everybody > > I had the intention to buy an ML410 board but the local Xilinx > > reseller told me that there is a problem concerning the ALi M1535D+ - > > there is no documentation given with the board. But in the > > documentation (ug085.pdf - ML410 Embedded Development Platform User > > Guide (v1.7) September 28, 2007) is stated that the datasheet is > > located on the documentation CDROM accompanying the board. > > Unfortunately this datasheet is not published on the internet (ie. > > under NDA). > > > My questiion is: does this problem really exist or the resseller is > > wrong? if the problem exists is it possible to contact ALi (nowadays > > NVidia I think) to get the datasheet? > > > Thanks in advance for answer > > Mehdi Thank you for information. If you have an idea about how to contact them please write me by mail. Thanks in advance! MehdiArticle: 128856
austin <austin@xilinx.com> wrote: >USB2 chip is now down to less than $1. >Why would you choose to suffer? Less chips, less soldering, less waiting for yet another manufacturer. At least USB-1.5Mbps and USB-12Mbps should be doable.Article: 128857
Eric Smith wrote: > fbv999@gmail.com writes: > >>I can hardly beleive, that when a single FPGA may cost up to 2000$, > > > You apparently haven't looked at the low-quantity pricing of the very > large FPGAs. It would be really nice if they could be purchased for > only $2000. > > Well, you can if you don't mind getting it already installed on an eval board and bundled with tools...plus a premium for the extras.Article: 128858
Hi As mentioned in an earlier post, I need an asynchonous instead of a synchronous data memory. The design was working with the BRAM, but the data was delayed by one cycle. So one would expect when adding a synchronous memory with the right timing behaviour to get the design fully working. So I used the core generator 7.1 and generated a distributed RAM with 1536 words a 32 bits. I used then a .coe file to initialise the content of the distributed RAM cells. I used a black box to map the signals. During translation the RAM is integrated but then when I use Chipscope something strange happens. I have 8 load data from memory instructions, 7 of those transfer the right value but always the third memory access reads a 00000000 into the register. Although cleary I have a value specified in my .ceo... TO be honest I have no clue how to tackle this problem. So I am hoping that maybe someone made the same experience and could tell me a solution for this? many thanksArticle: 128859
Hi Kyprianos, Have you tried 9.1SP2 with EAPR? Don't use the 8.2i archive, simply go to: http://www.xilinx.com/support/prealounge/protected/index.htm As the website says: "These software tools only support the Virtex-5, Virtex(tm)-4, Virtex-II and Virtex-II Pro architectures.", so I believe 9.1SP2 will work with the Virtex-5. In any case, give it a go. Shannon On Feb 8, 1:48 am, kyprianos <kpapa...@mhl.tuc.gr> wrote: > On Feb 7, 2:39 am, shac...@gmail.com wrote: > > > > > > > Hi Kyprianos, > > > Your best bet will be to go for EAPR with ISE 9.1i SP2. I do research > > in partial reconfiguration and when I was at a Xilinx Partial > > Reconfiguration workshop in TU Delft in the Netherlands last year, the > > Xilinx presenter alluded to the fact that Virtex-5 FPGAs are being > > supported in 9.1i. > > > PlanAhead is the front-end to EAPR and ISE, so all it really does it > > give you a graphical, user-friendly interface, generate the > > constraints files and execute the tools for you rather than using your > > own scripts. > > > Austin, thanks for your reply and I believe Kyprianos did ask if which > > versions of the ISE and EAPR tools support Virtex-5. Apart from that, > > I do believe that the old Virtex (first generation) family does have > > some problems regarding glitchless reconfiguration? It would be great > > to talk to you to obtain more definitive answers from Xilinx! Were you > > at TU Delft (FPL2007) last August? > > > Cheers, > > Shannon > > > On Feb 7, 4:25 am, austin <aus...@xilinx.com> wrote: > > > > Kyprianos, > > > > Have you read: > > > >http://www.xilinx.com/products/design_tools/logic_design/advanced/par... > > > > ? > > > > All Virtex parts (original through V5) "support" partial reconfiguration > > > (able to load new partial bitstreams while continuing to run) in > > > hardware. Is your question more one of what tools and what is the > > > recommended flow? > > > > Austin > > Hi all, > > Austin and Shannon thank you for the reply. It is clear that Virtex-5 > architecture does support partial reconfiguration. My question was > more about the tools. Which versions of the ISE and EAPR - as well as > of EDK for self-reconfiguration with a uP - are needed to partially > reconfigure a Virtex-5? I understand that partial reconfiguration > becomes less painfull with the use of PlanAhead. Although someone can > proceed without it. > > In the Xilinx's website, Section "Partial Reconfiguration Early Access > software tools for ISE 8.2i SP1" (http://www.xilinx.com/support/ > prealounge/protected/archive_82.htm), it is mentioned that "These > software tools only support the Virtex(tm)-4, Virtex-II and Virtex-II Pro > architectures. They must be installed on top of the ISE(tm) 8.2i sp1 > release.". There is nothing reported regarding Virtex-5 and recent > versions of ISE, e.g. can 9.1.2i EDK + 9.1i ISE w/ SP3 + EAPR be used > to apply self-PR on the Virtex-5? Is there any reference design that I > can get? > > Kyprianos- Hide quoted text - > > - Show quoted text -Article: 128860
Gerry wrote:
> As mentioned in an earlier post, I need an asynchronous instead of a
> synchronous data memory. The design was working with the BRAM, but
> the data was delayed by one cycle.
I don't see why this is a problem.
An asynch ram has an output delay also.
Maybe you need a faster clock.
A bird in the hand is worth two in the bush.
> So I am hoping that maybe someone made the same
> experience and could tell me a solution for this?
Solutions are found by debugging.
The standard practice is simulation.
-- Mike Treseler
Article: 128861Your LUT-RAM-based very big RAM may have long routing delays. If you believe in trying things out (instead of simulation), then reduce the clock rate, and see whether that helps. In your place, I would still try to rearrange the logic, so as to live with synchronous BlockRAMs. Peter Alfke, Xilinx Gerry wrote: > Hi > > As mentioned in an earlier post, I need an asynchonous instead of a > synchronous data memory. The design was working with the BRAM, but > the data was delayed by one cycle. So one would expect when adding > a synchronous memory with the right timing behaviour to get the > design fully working. So I used the core generator 7.1 and generated a > distributed RAM with 1536 words a 32 bits. I used then a .coe file to > initialise the content of the distributed RAM cells. I used a black box > to map the signals. During translation the RAM is integrated but then > when I use Chipscope something strange happens. I have 8 load data from > memory instructions, 7 of those transfer the right value but always the > third memory access reads a 00000000 into the register. Although cleary > I have a value specified in my .ceo... TO be honest I have no clue how > to tackle this problem. So I am hoping that maybe someone made the same > experience and could tell me a solution for this? > > many thanksArticle: 128862
Hi, While debugging my xsvf parser for ft2232 jtag programmers I experience some really odd behavior; if I swapped my buffer and then send (essentially) 'junk' to my device it would actually boot, but, without any sensible configuration and it would keep GHIGH asserted. It didn't detect a CRC error however and completed the rest of the bootcycle, which was really odd. So I dug a little further and found this; The data in the .rbt, since it's rbt we have to read from left to right in bits; 00000000 00000000 01011111 01010111 00110000 00000000 10000000 00000001 The associated .bit, should be interpreted as MSB first; 00 00 5F 57 30 00 80 01 gives 00000000 00000000 01011111 01010111 00110000 00000000 10000000 00000001 which is a perfect match with the rbt, thus so far so good. Now, 1.xsvf is generated using iMPACT with just the fpga in the chain, no other devices. Program with .bit while exporting to xsvf; 80 01 00 0C EA FA 00 00 read as LSB first (because it's xsvf) gives 00000001 10000000 00000000 00110000 01010111 01011111 00000000 00000000 which is indeed a flipped buffer (as it should be with xsvf) and matches the .bit. Then, 2.xsvf, LSB first, flipped buffer with more devices in the chain (FPGA = 2nd out of 3, so shift 1 bit right) 40 00 80 06 75 7D 00 00 gives 00000010 00000000 00000001 01100000 10101110 10111110 00000000 00000000 Compensate 1 bit x0000001 00000000 00000000 10110000 01010111 01011111 00000000 00000000 What the @#$? We've got some bits going all over the place. The only explanation I can think of it this; Take the MSB first .bit; 00 00 5F 57 30 00 80 01 00000000 00000000 01011111 01010111 00110000 00000000 10000000 00000001 Compensate -1 bit 00000000 00000000 10111110 10101110 01100000 00000001 00000000 0000001x Which then reads, LSB first; 40 00 80 06 75 7D 00 00 Familiar, no? If we take more devices (say, FPGA being 3th out of 4) gives in the xsvf; 20 00 40 03 3A BE 80 00 which means the .bit has been compensated -2 before being byte swapped. So really what iMPACT does is take the bit file, shift it, and _then_ byte swaps, while it should byte swap first and only after that shift the data to compensate for the other devices in the chain. Am I a crackpot or is this a bug? Cheers, Mike http://projectvga.orgArticle: 128863
On Feb 5, 5:04 pm, FPGA <FPGA.unkn...@gmail.com> wrote: > On Feb 5, 4:52 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > > > > > FPGA wrote: > > > I just found out that the packages in ieee_proposed that I added in > > > the work dir are huge and thats what is causing the problem. > > > Glad you figured it out. > > > > Please > > > suggest on how to add this library and also if I would still get the > > > same problems with the size even after adding the packages into a > > > library > > > It won't matter where the library is. > > You are over the limit of the student license, > > once you compile it into any library. > > Pick a simpler project or call Mentor. > > > -- Mike Treseler > > Which tol do you suggest I use. I work on VHDL and Verilog. I need > something very basic. Some companies, for example Xilinx, have full-featured products (i.e. high-demo boards) at very low prices. Perhaps Mentor or some other simulator company would be able to help you. HTH -Dave PollumArticle: 128864
On Feb 7, 5:22 pm, austin <aus...@xilinx.com> wrote: > Shannon, > > My email is good (aus...@xilinx.com). > > As for 'old' Virtex (220nm), I seem to recall something, but that is > ancient history now. If anyone is using Virtex for their research, they > should contact the XUP and get some new parts! > > Austin Shannon and Austin, I will go through the new archive. Thank you both! Greetings, KyprianosArticle: 128865
On Feb 7, 3:19 pm, Michael Meeuwisse <mickeymeeuw@g_something> wrote: > While debugging my xsvf parser for ft2232 jtag programmers I experience > some really odd behavior; if I swapped my buffer and then send Did you try xc3sprog? I think it is working with ft2232 (I haven't tried it myself). It reads the bitstream and I've used it with parallel port w/o problems with XC3S50, XC3S200, XC3S400 and XC3S500E. Another path could be xil_up, I think it supports ft2232 too. If you try a software known to be working you'll be able to find out if it's the hardware or the software. [Again, I haven't used any of the above ft2232, I have a proto board but I didn't have time to solder the wires ... :-(] Hope this helps. -- mmihaiArticle: 128866
Sky465nm@trline5.org wrote: > Less chips, less soldering, less waiting for yet another manufacturer. > At least USB-1.5Mbps and USB-12Mbps should be doable. OTOH, more wondering (and wasted time) if the reason your prototype isn't working is because you're not driving the bus correctly... -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 128867
Mark McDougall <markm@vl.com.au> wrote: >Sky465nm@trline5.org wrote: >> Less chips, less soldering, less waiting for yet another manufacturer. >> At least USB-1.5Mbps and USB-12Mbps should be doable. >OTOH, more wondering (and wasted time) if the reason your prototype isn't >working is because you're not driving the bus correctly... In that case I would just buy a chip+pcb to handle it. But it would really handy to be able to hookup usb devices without external circuitry. Except for some passives.Article: 128868
On 8 Feb., 03:34, Sky46...@trline5.org wrote: > Mark McDougall <ma...@vl.com.au> wrote: > >Sky46...@trline5.org wrote: > >> Less chips, less soldering, less waiting for yet another manufacturer. > >> At least USB-1.5Mbps and USB-12Mbps should be doable. > >OTOH, more wondering (and wasted time) if the reason your prototype isn't > >working is because you're not driving the bus correctly... > > In that case I would just buy a chip+pcb to handle it. But it would really > handy to be able to hookup usb devices without external circuitry. Except for > some passives. it IS doable and has been done. But for PRODUCTION you should use real tranceiver IC. thats it. If you want to hobby prototype, it is ok to connectect directly too AnttiArticle: 128869
On Feb 4, 8:11 pm, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > Same here.. It is working fine for me too. You might want to remove the > instalation and re-install the software.*CRINGE* > > "Arlet Ottens" <usene...@c-scape.nl> wrote in message > > news:47a5a30e$0$85789$e4fe514c@news.xs4all.nl... > > > pallavi wrote: > >> Hello, > >> I want to set up design environment for my new Spartan-3E FPGA starter > >> kit. > >> I have downloaded ISE WebPack 9.2 and the service pack 9.2i SP4. > >> To my dismay, when I want to point to my target device at the start or > >> later(Set Properties for project), the Family drop-down, doesnot show > >> of all the things, Spartan-3E. > > > I don't know what's wrong with your setup, but I'm using ISE WebPack > > 9.2.04i, and it shows the Spartan-3E devices. Yes, i had to remove and reinstall and it worked. It was probably the sleepy web install overnight, at the first instance.Article: 128870
Gabor wrote: > > 1) Don't know how much this helps, but if you're using the > 3S500E and don't fill the part up too much, your bitstream > can fit into a 2 Mbit prom if you compress it. Banking on > that however can lead to problems if your design expands and > the compressed bitstream grows over the 2 Mbit boundary. I don't know yet if it fits in a 2 MBit prom because it depends on some cores not yet written. what do you mean with 'compress'? There is no processor available for some kind of uncompressing it during power up, the fpga should just 'boot' from the prom. > > 2) Do you have some other storage available that could be > shared to with the bitstream data? A microcontroller > with attached flash? A 120 Gbyte hard drive attached > via the host system interface? Or does your FPGA need to > come up running without any support from software? no not really a 120 GB drive available. The whole system should be fitted on a few cm.flexprint, the microcontroller/RAM etc. is part of the FPGA. > > 3) Any chance of using a Lattice XP2 in the 132-ball csBGA > instead (no external prom required)? Mm, good tip. I'll investigate that line. thanks. TacoArticle: 128871
> Using the math_real library can do for now. I have had a look at the > sin and cos functions there. I am also aware on how to conver the real > format to the format I want. I intend to generate a wave. sin and cos > in math_real would just generate a value for a particular input. How > can i generate a sine or cos waveform. I wish to make this function > parametrized as follows (not sure if this should go into a function or > process) > Are you sure you want to go down this path? If you eventually need it synthesizable, you will have to throw away ALL of the work you have done with the math_real package, unless you're using it as a model of the final block. The easiest way to implement sin and cosine in and FPGA is using a look up table (normally a ROM), with the address formed from the angle coefficient.Article: 128872
Hi all, I have done some resource estimation while doing my design on System generator 9.1. But it beats me where to get the map report after I have done post map estimation. I will appreciate some insight into that. Thank you. Regards, BryanArticle: 128873
On Feb 7, 7:30 am, fbv...@gmail.com wrote: > I can hardly beleive, that when a single FPGA may cost up to 2000$, > there is no space for a few hundred kilo- maybe megabytes of > information in an age, when a terabyte costs around a few 100$s. Or > does it generate such a big traffic, without return o investment? > Someone tell me please the mail address of the marketing and financial > freaks at Xilinx! I would like to donate them my PC and a portion of > my 512kpbs bandwith for the purpuse... marketing.freaks@xilinx.comArticle: 128874
Hi everybody , I am looking for a development board. My intention is to devolp a DSP application so ideally should contain : -xc3s500e-pq208 -ADC <80Msps <10bit -DAC same specifications. -The PROM and JTAG interface is not an issue . I have a JTAG programmer for PROMS. I would reaaly appreciate your help. Alfredo Taddei
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