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> In this case the reset port can be omitted, I wanna sythesis this as a > BRAM on a Xilinx FPGA. Hope that works! Well .. unfortuatnely XST tells me that the RAM will be implemented with LUTS and that I have to describe it in a way that BRAM can be instatiated, so that initial values can be stored in it... Anyone who can help me out in this matter?Article: 128776
"Gerry" <Gerry@hotmail.com> wrote in message news:focaks$3r3$2@aioe.org... > > > In this case the reset port can be omitted, I wanna sythesis this as a > > BRAM on a Xilinx FPGA. Hope that works! > > Well .. unfortuatnely XST tells me that the RAM will be implemented with > LUTS and that I have to describe it in a way that BRAM can be instatiated, > so that initial values can be stored in it... > > Anyone who can help me out in this matter? Xilinx has templates for how to write code that will infer memory that can be implemented in ram blocks. Check the documentation. I'm guessing that the problem area might have to do with your reset section. Try taking out the entire 'if (rst = '0')....end if;' section of code and see if it infers the memory correctly. Kevin JenningsArticle: 128777
Hi all, I thought I would share this report that I just wrote called "Single Top FPGA Tips". http://www.burched.com/BurchED_Single_Top_Tips.pdf It's a bit different to your normal "Top Ten Tips" or "Favourite Recipes" because I tried to write a single tip for each level of FPGA designer, right through from "not yet started" to "experienced". I hope you enjoy it! Kind regards, Anthony BurchArticle: 128778
Hello all, I am trying to configure the ADC for voltage monitoring part. I have to use only three channels, So I am using AV0, AV1 and AV2. I am using Flash running at 8MHz to initialize and 40MHz is the fast clock after initialization which I am using as analog system clock. In SMARTGEN in the analog system builder I am selecting "ADC Sample and Sequence Control only". And I am only outputting ADC Results from the analog system. In the post layout simulation, I see that Flash initialization is done and I see ADC results as well as the three ADC Channels I am configuring in my design. So post Layout simulation gives me perfect result but the design does not give any result on DC Result in reality. In my design, I have used a Dual Port RAM as well that comprises 128 addresses of 16 bit wide data. I am reading out the ADC Results on to the RAM memory but I see in POST LAYOUT Simulation perfect results but do not see anything when I download the design on the board. The design meets maximum delay timing requirements as well in the timing analyzer. Please help me if someone has suggestions. On Jan 31, 11:11 pm, Rehman <iamreh...@gmail.com> wrote: > On Jan 31, 4:46 pm, Kris Vorwerk <kris.vorw...@gmail.com> wrote: > > > > I am working on Actel Fusion FPGA. > > > I am having problems with the ADC in my design. > > > > Can someone please help me with this? > > > More details please :) > > > (I'm not overly-familiar with the ADC, but if you provide a few more > > details, either I or someone else may be able to help.) > > > K. > > Hey, > I am trying to configure the ADC for voltage monitoring part. > I have to use only three channels, So I am using AV0, AV1 and AV2. > I am using Flash running at 8MHz to initialize and 40MHz is the fast > clock after initialization which I am using as analog system clock. > In SMARTGEN in the analog system builder I am selecting "ADC Sample > and Sequence Control only". > And I am only outputting ADC Results from the analog system. > > Te problem is that nothing comes out on the ADC Result. > In the post layout simulation, I see that Flash initialization is > done, but the ADC Channel and ADC Result is always zero along with > ASSC_Done, ASSC_Wait, ChLAT, ChSAT signals. > > Out from the Analog system Block here is the code I use to read out > the ADC Results. > > library ieee; > > library fusion; > > use IEEE.std_logic_1164.all; > > use IEEE.std_logic_signed.all; > > entity strm_ebs is > > port ( > ebs_right,ebs_up,ebs_left,ebs_down : out std_logic; > rssi0,rssi1,rssi2,rssi3,rssi4,rfa0,rfa1,rfa2,rfa3,rfa4, > rfb0,rfb1,rfb2,rfb3,rfb4 : out std_logic_vector (11 downto > 0); > adc_result : in std_logic_vector (11 downto 0); > adc_ch : in std_logic_vector (4 downto 0); --adc channel > adc_data_valid,clk_5k,reset : in std_logic > ); > > end strm_ebs; > > architecture arch_strm_ebs of strm_ebs is > > begin > > ---------Generating ebs signals ------------------- > > Process (clk_5k,reset) > variable ebs_sig : std_logic_vector (3 downto 0) := "0000"; > begin > > if reset='0' then > ebs_sig := (others => '0'); > ebs_right <= '0'; > ebs_up <= '0'; > ebs_left <= '0'; > ebs_down <= '0'; > rssi0 <= (others => '0'); > rssi1 <= (others => '0'); > rssi2 <= (others => '0'); > rssi3 <= (others => '0'); > rssi4 <= (others => '0'); > rfa0 <= (others => '0'); > rfa1 <= (others => '0'); > rfa2 <= (others => '0'); > rfa3 <= (others => '0'); > rfa4 <= (others => '0'); > rfb0 <= (others => '0'); > rfb1 <= (others => '0'); > rfb2 <= (others => '0'); > rfb3 <= (others => '0'); > rfb4 <= (others => '0'); > elsif (clk_5k'event and clk_5k='1') then > > case ebs_sig is > when "0000" => > ebs_sig := "0001"; > when "0001" => > ebs_sig := "0010"; > when "0010" => > ebs_sig := "0100"; > when "0100" => > ebs_sig := "1000"; > when "1000" => > ebs_sig := "0000"; > when others => > null; > end case; > ebs_right <= ebs_sig(3); > ebs_up <= ebs_sig(2); > ebs_left <= ebs_sig(1); > ebs_down <= ebs_sig(0); > > if (adc_data_valid ='1') then > > case ebs_sig is > when "0000" => > case adc_ch is > when "00001" => > rfa0 <= adc_result; > when "00100" => > rfb0 <= adc_result; > when "00111" => > rssi0 <= adc_result; > when others => > null; > end case; > when "0001" => > case adc_ch is > when "00001" => > rfa4 <= adc_result; > when "00100" => > rfb4 <= adc_result; > when "00111" => > rssi4 <= adc_result; > when others => > end case; > > when "0010" => > case adc_ch is > when "00001" => > rfa3 <= adc_result; > when "00100" => > rfb3 <= adc_result; > when "00111" => > rssi3 <= adc_result; > when others => > end case; > > when "0100" => > case adc_ch is > when "00001" => > rfa2 <= adc_result; > when "00100" => > rfb2 <= adc_result; > when "00111" => > rssi2 <= adc_result; > when others => > end case; > > when "1000" => > case adc_ch is > when "00001" => > rfa1 <= adc_result; > when "00100" => > rfb1 <= adc_result; > when "00111" => > rssi1 <= adc_result; > when others => > end case; > > when others => > null; > > end case; --end ebs signal cases > end if; --if (adc_data_valid) > end if; --if (reset) > > end process; > > ---------------------------------------------------- > > ---------------------------------------------------- > > end arch_strm_ebs; > > Thanks, > Cheers!Article: 128779
KJ wrote: > "Gerry" <Gerry@hotmail.com> wrote in message news:focaks$3r3$2@aioe.org... >>> In this case the reset port can be omitted, I wanna sythesis this as a >>> BRAM on a Xilinx FPGA. Hope that works! >> Well .. unfortuatnely XST tells me that the RAM will be implemented with >> LUTS and that I have to describe it in a way that BRAM can be instatiated, >> so that initial values can be stored in it... >> >> Anyone who can help me out in this matter? > > Xilinx has templates for how to write code that will infer memory that can > be implemented in ram blocks. Check the documentation. > > I'm guessing that the problem area might have to do with your reset section. > Try taking out the entire 'if (rst = '0')....end if;' section of code and > see if it infers the memory correctly. Thanks Kevin, but the problem remains... Without the reset, the tool still tells me that when i have an asynchronous read and so BRAM cant be used... I am using XST 7.3. Anyone a workaround for this problem? Would be very much appreciatedArticle: 128780
On Feb 6, 1:26 am, xenix <last...@gmail.com> wrote: > Hello all. below is a part of my code for an OPB timer attached to a > Microblaze with no inerrupts. the timer counts correct but when > reaches the value 0xFFFFFFFF ( end point) should roll over and start > again counting but this doesn't happend. what might be wrong here? perhaps you need to set XTC_CSR_AUTO_RELOAD_MASK. alan nishioka alan@nishioka.comArticle: 128781
OK, you want a sine at 500 Hz. Suppose your class-D power amp has the following characteristics : - Tswitch : switching time - Fswitch : maximum switching frequency - Dmin, Dmax : minimum and maximum duty cycle at the output Let's suppose : Fswitch =3D 500 kHz Tswitch =3D 20 ns Dmin =3D 2% Dmax =3D 98% This means the PWM will have a frequency of Fs =3D 250 kHz which is a = period Ts =3D 4 us. On each PWM period, the output will be high for a certain time T, and l= ow = for the rest of the period, or Ts-T. So, first, you need a digital sinewave, that is a sequence of digital = samples, with a sampling frequency Fs. Then, for each digital sample, you set the output PWM signal to 1 for a= = time proportional to the sample value, and then to 0 for the rest of the= = period. You could implement it with a DDS (to generate the sine samples) which = = outputs a sample every Ts. Every time a sample is produced, - the PWM output is set to 1. - and a counter is set to the value of the sample. Then using a main clock, of frequency Fc, you decrement this counter. = When it reaches 0, you set the PWM output to 0. This will give you your PWM signal. Now, which frequency to use for the main clock Fc ? This depends on the= = precision you need. With a faster clock, you will be able to cut the Ts = = period into smaller slices and your samples can have more bits. Let's suppose you use Fc =3D 50 MHz which should be perfect for a Spart= an-3. In this case every sample Ts (4 us) contains 200 cycles of your main = clock. Therefore, your sine samples should be between 0 and 200 (integer). You= = can use a 8 bit counter. Now using the minimum and maximum duty cycle specs of your class-D amp,= = you can determine that your sine samples should be between 2% and 98% of= = 200, this means 4 and 196. You need to set those parameters in your DDS.= = I think you were confused because there are several clocks here : - the main clock which drives the counter which sets the duty cycle of = = the PWM (in this case 50 MHz) - the sample clock (in this case 250 kHz) - the output PWM signal frequency (in this case 250 kHz too) > Hallo to everyone, > I should develop a system which outputs a pwm signal into a filter to > obtain a sine at 500 Hz which will command a class D amplifier. > > I was considering to use dds compiler to generate digital sine, then > putting the output in a pwm generator, like the one seen in fpga4fun > website. > > If I can't use a high frequency oscillator for fpga, because of the > limit of class D amplifier, may I use an oscillator of 500kHz about? > > There are some troubles, in example with DCM? > > Many Thanks, > Marco >Article: 128782
"Gerry" <Gerry@hotmail.com> wrote in message news:focf2m$ij4$1@aioe.org... > KJ wrote: <snip> > Thanks Kevin, but the problem remains... Without the reset, the tool still > tells me that when i have an asynchronous read and so BRAM cant be > used... Seems pretty clear to me...use a synchronous read > I am using XST 7.3. Anyone a workaround for this problem? > > Would be very much appreciated Once again, we call on that Spanish hero Manual Per Xilinx's website Templates for inferring registers, flip-flops, or memory can be found in Chapter 2 of the XST User Guide at: http://www.xilinx.com/support/software_manuals.htm Although a more useful link is http://toolbox.xilinx.com/docsan/xilinx8/books/docs/xst/xst.pdf Page 174... Kevin JenningsArticle: 128783
Michael Meeuwisse wrote: > > I keep on arguing that it shouldn't matter, but to be absolutely on the > safe side I'll make it possible tomorrow to set M2 and M0 to 2.5V. I > really hope I'm wrong and changing this makes the problems go away. > There have been a number of issues over the years with JTAG configuration and mode select lines in various PROM/FPGA families; common symptoms are failed JTAG configuration, failed FPGA startup, failed DCM startup, etc. Sometimes these have been patched in Impact, sometimes with a die revision of the PROM or FPGA. For Spartan-3, try these: AR #22255 - Spartan-3 Configuration - JTAG configuration completes successfully, but the device is not fully operational or a verify fails AR #9013 - Spartan-3/-E/-A - JTAG configuration might fail when the PROM is loaded with data different from the bit file Other possibly useful things : AR #20047 - Spartan-3/-3E/-3A Configuration - The DONE pin goes High,but the device does not start up (I/Os are inactive/3-stated) AR #11778 - Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures correctly after PROG is pulsed, but DLL/DCM/DCI does not function correctly when reconfigured AR #24862 - PROM-XCF00P - When playing an SVF file to the XCF00P device, pulsing PROG after file completion does not cause a configuration AR #16829 - Virtex and Spartan FPGAs - How does the JTAG JPROGRAM instruction work? AR #14444 - XC18V00/XC1700/XCFxx - PROM frozen after the power cycling test; configuration fails after power-on reset/initial power up. What are the requirements for power cycling XC1700/XC18V00/XCFxx PROM? AR #4219 - 9.1i BitGen - Why does Virtex not pass data to DOUT? What is the purpose of the "-g DebugBitstream" option? How does a "debug bitstream" differ from a normal bitstream? have fun, BrianArticle: 128784
Tony Burch schrieb: > http://www.burched.com/BurchED_Single_Top_Tips.pdf Nice. But what about nr. six? A can't agree. AFAIK the ASIC guys do a Post Place & Route Simulation to check for possible errors of the compiler (wrong logic optimization, maybe wrong automatich pipeline modification etc.) But for a FPGA . . . In many cases, a real time test is much faster and more valueable for verification (including stress tests). Regards FalkArticle: 128785
Hi all, Does anyone know whether Virtex-5 devices are supported by the Partial Reconfiguration design flow. I understand that PlanAhead supports it but which versions of the ISE and the EAPR support partial reconfiguration for Virtex-5? Thanx kyprianosArticle: 128786
On 30 Jan., 07:24, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > On 28 Jan., 21:34, Ben Jackson <b...@ben.com> wrote: > > > >http://www.truedream.org/smile/MyFirstFlashFpgaCert.pdf > > > ...you got FIRED for missing 3 days of work due to a mixup in vacation > > scheduling? Wow. > > I wonder, too. Must have a strange boss. I thought you were still > working in Germany (where it is not easy to get that fast out of the > job). > > Antti: some :) :) :) for you and your book. > > bye Thomas Hi Thomas, the F=FChrers (gesch=E4ftsf=FChrer =3D=3D managing director) are good in ger= many at fast firing and I know from other people that both christmas-firing and vaccation- firing are popular. I wasnt going to comment this thread, but right now I noticed that they also have not transferred the last paycheck either! That is I received the official paper about my january salary from the bookkeeping, but the money has not arrived. based on that I have re-allocated the donations I have received for the e-book for food for my older son who lives separatly (I just transferred my paypal rest account to him - about 30eur). Antti and thanks all for the smilies!Article: 128787
I have posted here many times, and it is clearly descibed in the user guide: BlockRAM read is always a synchronous operation. There is no asynchronous read in BlockRAM, no matter how hard you try, and how much you desire it. It's inherent in the hardware design, no if, no but. LUT-RAM read is inherently asynchronous, but you can add a flip=3Dflop tp make it synchronous. Peter Alfke, Xilinx On Feb 6, 6:09=A0am, Gerry <Ge...@hotmail.com> wrote: > KJ wrote: > > "Gerry" <Ge...@hotmail.com> wrote in messagenews:focaks$3r3$2@aioe.org..= . > >>> In this case the reset port can be omitted, I wanna sythesis this as a= > >>> BRAM on a Xilinx FPGA. Hope that works! > >> Well .. unfortuatnely XST tells me that the RAM will be implemented wit= h > >> LUTS and that I have to describe it in a way that BRAM can be instatiat= ed, > >> so that initial values can be stored in it... > > >> Anyone who can help me out in this matter? > > > Xilinx has templates for how to write code that will infer memory that c= an > > be implemented in ram blocks. =A0Check the documentation. > > > I'm guessing that the problem area might have to do with your reset sect= ion. > > Try taking out the entire 'if (rst =3D '0')....end if;' section of code = and > > see if it infers the memory correctly. > > Thanks Kevin, but the problem remains... Without the reset, the tool > still tells me that when i have an asynchronous read and so BRAM cant be > used... I am using XST 7.3. Anyone a workaround for this problem? > > Would be very much appreciatedArticle: 128788
Hey guys, Be careful when using Virtex5 for SONET. The RocketIO tile only has 1 PLL used for transmit and receive on both bidirectional ports. This PLL is normally sync'd to the local reference so the transmit data is on the local clock rather than the network clock (recovered clock). This architecture leads to all sorts of problems. Xilinx is recommending that a crystal controlled VCO oscillator be used for the local reference per XAPP649 (old Virtex2 app note) but this entails designing a phase comparator and analog filter. Even if you do this, your stuck with the second transmitter sync'd to the recovered clock of the first port. In our application we would like to use the second port for Ethernet in a POS application (can't be done). In order to make this work, the application software has to keep track of where the recovered clock is coming from and the clocks from several ports need to be muxed to select which recovered clock is used for the VCO reference. See what I mean?Article: 128789
Kyprianos, Have you read: http://www.xilinx.com/products/design_tools/logic_design/advanced/partial_reconf_faq.htm ? All Virtex parts (original through V5) "support" partial reconfiguration (able to load new partial bitstreams while continuing to run) in hardware. Is your question more one of what tools and what is the recommended flow? AustinArticle: 128790
Peter Alfke wrote: > I have posted here many times, and it is clearly descibed in the user > guide: > BlockRAM read is always a synchronous operation. There is no > asynchronous read in BlockRAM, no matter how hard you try, and how > much you desire it. It's inherent in the hardware design, no if, no > but. > LUT-RAM read is inherently asynchronous, but you can add a flip=flop > tp make it synchronous. > Peter Alfke, Xilinx Alright, thanks for the feedback peter. The problem is, that I need an asynchronous read for the module I am using. So the problem is, that I cant initialise the values in the RAM as in the BRAM. Is there any other way to get initial values into the asynchronous RAM? Does an upgrade to a newer version of XST help or am I doomed? Thanks GArticle: 128791
Lars wrote: > Anyone with experience of the DS1WM, any pit-falls that you know of > that I might have fallen into? Serching this group for DS1WM does not > return any hits, and 1-Wire is almost as meager... I have implemented a 1-wire interface, with checksum test for the unique id chip of the Spartan 3E starter kit: http://www.frank-buss.de/vhdl/spartan3e.html Works nice all the time, on Cyclone, too :-) -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 128792
Take a look at /Xilinx/doc/usenglish/docs/lib/lib.pdf. Look up component RAM_16x1D. There are examples on setting the initial values of RAM. More importantly, be familiar with the various documents under the /docs/ subtree. The developers reference and constraint guide are equally invaluable. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado Based Xilinx Consultant phone : 303.926.0068 email : jretta@rtc-inc.com web : www.rtc-inc.comArticle: 128793
John Retta wrote: > Take a look at /Xilinx/doc/usenglish/docs/lib/lib.pdf. > Look up component RAM_16x1D. There are examples on > setting the initial values of RAM. > > More importantly, be familiar with the various > documents under the /docs/ subtree. The developers > reference and constraint guide are equally invaluable. THanks John, will have then a look at it. Just hope that it also works with my old XST 7.1...Article: 128794
I think your advice is basically sound, but... I would extend it to say that ANY SONET/SDH application requires a LOT OF WORK. Virtex 5 has a characterization report for OC-48, but it covers only the basic electrical and performance requirements: there is a lot more to SONET/SDH than just the transmit jitter, and the receive jitter tolerance (although, these are two very important specifications). Clocking (or in SONET/SDH language - "synchronization and timing") is a huge issue, that requires careful design and architecture analysis to be able to meet the requirements of the end application. All the clocking modes, stratum levels, etc. go far beyond the basic MGT in a device. We have an applications note on this subject, too: http://www.xilinx.com/publications/prod_mktg/NetworkTiming_ssht.pdf So, yes, the use of one PLL for both transmit and receive in order to save power in the MGT causes additional complexity for some, but overall, the power savings is well appreciated and becoming more important to telecom every day. So, again, YES. Read the data sheets. Read the characterization reports. Talk to your Xilinx or disti FAE. Find all reference designs. Then, go to work and see how to (or if you can) use Virtex 5 to solve your problem. AustinArticle: 128795
Replying to myself here for the moment. Michael Meeuwisse wrote: > This is where it gets annoying, I don't have anything to check out > the waveform with. I'll have to drag everything to uni tomorrow if I > want to see what's happening on such lines which is a much bigger > effort than just taking the PCI card - I'll do it anyway, but still. > It would be easier if I was able to program the fpga so I could fling > a little counter-thing on it outputting it to the led. > The only scope available was a 20MHz one (the clock should be running at 50) which didn't help. I'm seeing a DC voltage ~1.10V and AC voltage of ~2.3V on my (rather embarrassingly cheap) multimeter which makes me believe there's a clock running on that pin. >> The JTAG *interface* is available at all times. But the FPGA will only be >> configured by JTAG if the mode pins are M[2:0] = 101. >> (An exception might by with JSTART instruction, but I'm not sure). >> > > I keep on arguing that it shouldn't matter, but to be absolutely on the > safe side I'll make it possible tomorrow to set M2 and M0 to 2.5V. I > really hope I'm wrong and changing this makes the problems go away. > Well I'll be damned. It scared the hell out of me to unsolder a few of the fpga pins but I can now select between mode 101 (JTAG) and 000 (Master Serial) with a simple pin header. This results in a status register (before programming) of 0x30B00000 and 0x31B00000 or in other words; 0011 0001 1011 - no CRC error, DCM locks, DCI Matches, GHIGH_B deasserted, Mode 101 JTAG, INIT pin high. I especially like the last one, if I measure it on the print it is indeed still high after programming - afaik this means that the chip is programmed correctly without any CRC errors. The values of the configuration pins are; INIT_B: 3.3V (high) PROG_B: 2.5V (high) DONE: 0V (low) So why isn't it starting up after that? I've tried doing a runtest (go to RTI state, output a 1000 clockticks) directly after programming and the startup clock is set to JTAG in ISE. Didn't seem to help, so suggestions are once again welcome. Cheers, Mike http://projectvga.orgArticle: 128796
>The only scope available was a 20MHz one (the clock should be running at >50) which didn't help. I'm seeing a DC voltage ~1.10V and AC voltage of >~2.3V on my (rather embarrassingly cheap) multimeter which makes me >believe there's a clock running on that pin. I think DC voltage is the right one considering it's pulsed signal and that the frequency is way above what the multimeter can detect. Btw, Average of LVTTL threesholds 0.8 and 2.0 is 1.4V :) 20 MHz scope might be doable. Select the fastest timebase and enable 10x timebase. Adjust for higher intensity. And you should see a *tiny* weak signal. Probes matter too ofcourse ;) If you don't have money/equipment then you got to use your mind+time instead ;) >Well I'll be damned. It scared the hell out of me to unsolder a few of >the fpga pins but I can now select between mode 101 (JTAG) and 000 >(Master Serial) with a simple pin header. This results in a status >register (before programming) of 0x30B00000 and 0x31B00000 or in other >words; >0011 0001 1011 - no CRC error, DCM locks, DCI Matches, GHIGH_B >deasserted, Mode 101 JTAG, INIT pin high. >I especially like the last one, if I measure it on the print it is >indeed still high after programming - afaik this means that the chip is >programmed correctly without any CRC errors. The values of the >configuration pins are; >INIT_B: 3.3V (high) Shouldn't INIT_B be pull-up to 2.5V ? (R22 68R) Though the XCF04S eeprom might have another opinion on this :) >PROG_B: 2.5V (high) >DONE: 0V (low) >So why isn't it starting up after that? I've tried doing a runtest (go >to RTI state, output a 1000 clockticks) directly after programming and >the startup clock is set to JTAG in ISE. Didn't seem to help, so >suggestions are once again welcome. My suggestion is program that blinks a led (P77,P78) with help of the 50 MHz oscillator (P76). According to your schematic: http://wacco.mveas.com/img/schema1d.png You haven't wired anything to the 'DONE' pin (P103). In ds099.pdf p103: "A Low-to-High output transition on this bidirectional pin signals the end of the configuration process. The FPGA produces a Low-to-High transition on this pin to indicate that the configuration process is complete. The DriveDone bitstream generation option defines whether this pin functions as a totem-pole output that actively drives High or as an open-drain output. An open-drain output requires a pull-up resistor to produce a High logic level." So IF you have defined DONE as TOTEM-pole, you must NOT attach a PULL-up. If you have defined DONE as OPEN-drain, you must attach a PULL-up to 2.5V. ds099.pdf p47 have an illustration on this. Example .ut file: -g CclkPin:PULLUP -g TdoPin:PULLNONE -g M1Pin:PULLDOWN -g DonePin:PULLUP -g StartUpClk:JTAGCLK -g M0Pin:PULLUP -g M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g LCK_cycle:NoWait -g Security:NONE -m -g Persist:No And don't forgett that pesky Electrostatic-Sensitive-Devices during rework ;)Article: 128797
hilo_pupu@hotmail.com wrote: > Hi all, > > I am currently building a Digital Down Converter on Xilinx System > Generator 9.1 platform which unfortunately overshot resources provided > by mt target Virtex 4 chip by 400%. Is there any optimization way to > shrink it down.? If your DDS is synthesizing a frequency that divides the main clock evenly, you can implement it as a small lookup table. Otherwise, I'd advise using a first-order Taylor series sin/cos calculation. This takes only a single BRAM and a I think three multipliers (which may be shared based on the folding factor). To ensure that you are using the minimum number of filters in your filter chain, read Crochiere and Rabiner's 1975 paper "Optimum FIR Digital Filter Implementations for Decimation, Interpolation, and Narrow-Band Filtering". And read this appnote, which includes a SysGen design that you can modify: http://www.xilinx.com/support/documentation/application_notes/xapp1018.pdf -KevinArticle: 128798
I would like some guidline on writing a function or process to generate a sine wave and cosine wave. I want to include this into my library. Each time this function/process is called, I would like sine and cosines wave generated. Are there any functions in VHDL which would help us do so. I know there is a function UNIFORM to generate random numbers, not sure if there is anything available for sine and cosine. Your comments are appreciated. AnujaArticle: 128799
I would like to use the CORDIC function available in math_real to generate the sine and cosine wave. Any inputs on if this is possible would be appreciated.
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