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On Apr 13, 1:09=A0pm, gabor <ga...@alacron.com> wrote: > On Apr 13, 11:37=A0am, axr0284 <axr0...@yahoo.com> wrote: > > > > > > > Hi, > > =A0I am trying to access a flash device from a microblaze processor on = a > > Spartan 3E device. In Xilinx XPS, I instantiated the IP "External > > Memory Controller" with the following attributes > > > BEGIN xps_mch_emc > > =A0PARAMETER INSTANCE =3D flash_16Mx8b > > =A0PARAMETER HW_VER =3D 2.00.a > > =A0PARAMETER C_NUM_BANKS_MEM =3D 1 > > =A0PARAMETER C_NUM_CHANNELS =3D 0 > > =A0PARAMETER C_MEM0_WIDTH =3D 8 > > =A0PARAMETER C_MAX_MEM_WIDTH =3D 8 > > =A0PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 =3D 1 > > =A0PARAMETER C_TCEDV_PS_MEM_0 =3D 75000 > > =A0PARAMETER C_TAVDV_PS_MEM_0 =3D 75000 > > =A0PARAMETER C_THZCE_PS_MEM_0 =3D 25000 > > =A0PARAMETER C_THZOE_PS_MEM_0 =3D 120000 > > =A0PARAMETER C_TWC_PS_MEM_0 =3D 1200000 > > =A0PARAMETER C_TWP_PS_MEM_0 =3D 1200000 > > =A0PARAMETER C_TLZWE_PS_MEM_0 =3D 0 > > =A0PARAMETER C_MCH_PLB_CLK_PERIOD_PS =3D 62500000 > > =A0PARAMETER C_MEM0_BASEADDR =3D 0x80000000 > > =A0PARAMETER C_MEM0_HIGHADDR =3D 0x80ffffff > > =A0BUS_INTERFACE SPLB =3D mb_plb > > =A0PORT RdClk =3D sys_clk_s > > =A0PORT Mem_A =3D flash_16Mx8b_Mem_A > > =A0PORT Mem_DQ =3D flash_16Mx8b_Mem_DQ > > =A0PORT Mem_WEN =3D flash_16Mx8b_Mem_WEN > > =A0PORT Mem_OEN =3D flash_16Mx8b_Mem_OEN > > =A0PORT Mem_CEN =3D flash_16Mx8b_Mem_CEN > > END > > > The flash documentation states that Write cycle should be a minimum of > > 60 ns so I put 120 ns for C_TWC_PS_MEM_0 just in case > > > In the code, I use the following to try to write to the Flash > > XIo_Out8(FLASHBASEADDR,0x0090); // Request Device ID > > > I then probed the WE# input pin of the flash with an oscilloscope but > > I see a low pulse of only 16 ns. I tried changing the parameters but > > nothing seems to affect the time the WE# signal is held low. > > > Why doesn't the parameters I set up affect the time the WE# signal is > > held low? > > Thanks for any answer > > Amish > > Are you really running the PLB at 16 MHz? =A0Theoretically > the timing numbers are divided by the PLB clock period to > generate the times you want using an integral number of > bus clock cycles. > > Unless I'm reading this wrong you have: > > PARAMETER C_MCH_PLB_CLK_PERIOD_PS =3D 62500000 > > which to me would mean 62.5 ns or 16 MHz. > > Regards, > Gabor- Hide quoted text - > > - Show quoted text - Thanks a lot for pointing that out. This is exactly what it was. I really appreciate this. It saved me a lot of time. AmishArticle: 139776
JSreeniv wrote: > Hi all, > Could anyone please explain this requirement in detail or by steps: > > <Bit 16 of the rcom_ctl_sts register shall return a 0 within 1us when > a Manchester error has been acknowledged by the processor writing a 1 > to bit 16 of the rcom_ctl_sts register> > > I am waiting for the response...its Urgent > > Sreeniv Are you joking? You give basically no context about your question, but hope, that somebody will quickly take out his crystal ball, guess the context and answer your urgent question. Just guessing now, as I do not have a crystal ball, but a few spare minutes: It seems to be about a hardware module to be designed and being connected to a processor. In this design a 'manchester error' (whatever it is) can occur. the user of the module can 'acknowledge' this error by setting bit 16 of a certain register to 1. To say it one way: if the processoer were reading the same register one microsecond later it should no more read the '1' it has written to bit 16 of rcom_ctl_sts, but a '0'. To say it another way. The module should then (after the processor wrote bit 16 of rcom_ctl_sts as acknowledgement of a Manchester error) within 1 micro-second make sure, that any read access from the processor will return a '0' in bit 16. bye NArticle: 139777
On Apr 13, 5:16=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Apr 13, 5:47=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > > > > > > Xilinx COE memory initialization files... > > > ...support at least four data formats. > > > PATTERN and BRANCH_LENGTH_VECTOR formats > > are too specialized to concern me right now. > > > MEMORY_INITIALIZATION_VECTOR is easy enough. > > > But what's the point of COEFDATA? =A0Isn't it just > > another way to specify a bunch of numbers in a memory? > > > Any pointers into the Xilinx docs would be appreciated. =A0 > > The best I found was an informative, but far from > > complete, page on "COE File Syntax". > > > Am I right in guessing that Coregen uses the > > "coefficient" data in various different ways, > > depending on what sort of filter it's creating, > > and there may not necessarily be a one-to-one > > correspondence between coefficient values and > > memory contents? > > > Thanks in advance > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > dont ever use COE unless needed for some special reason > > Antti- Hide quoted text - > > - Show quoted text - Antti WHY? I use them in FIR filters and they seems to work fine. Otherwise you need to input them before use. But the thruth is that I had some problems in sumulation of older versions of MAC FIR Coregen filters. Cheers, AlesArticle: 139778
On Apr 13, 5:16=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Apr 13, 5:47=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > > > > > > Xilinx COE memory initialization files... > > > ...support at least four data formats. > > > PATTERN and BRANCH_LENGTH_VECTOR formats > > are too specialized to concern me right now. > > > MEMORY_INITIALIZATION_VECTOR is easy enough. > > > But what's the point of COEFDATA? =A0Isn't it just > > another way to specify a bunch of numbers in a memory? > > > Any pointers into the Xilinx docs would be appreciated. =A0 > > The best I found was an informative, but far from > > complete, page on "COE File Syntax". > > > Am I right in guessing that Coregen uses the > > "coefficient" data in various different ways, > > depending on what sort of filter it's creating, > > and there may not necessarily be a one-to-one > > correspondence between coefficient values and > > memory contents? > > > Thanks in advance > > -- > > Jonathan Bromley, Consultant > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > dont ever use COE unless needed for some special reason > > Antti- Hide quoted text - > > - Show quoted text - And I use only a non-symetric FIR variant because of that. Cheers, AlesArticle: 139779
On Mon, 13 Apr 2009 10:11:02 -0700 (PDT), ivan <ivan.sovic@gmail.com> wrote: >Hi, >I've been playing around with ISE 10.1 (and also 9.2i) and Spartan 3- >AN. >When I open Project Navigator, synthesize my design and program it >into FPGA using iMPACT, everything works fine. But, if I change >something in the design (like, for instance, turn on the LED that was >previously off), and start iMPACT again (it offers me to choose the >bit file, as it did the first time), for some reason it only downloads >the old design to the board, no matter that I chose the new bit file. >Things work normally when I close Xilinx altogether and start it up >again. > >Is this a bug, or did I skip some setup options? > >Please help, it's REALLY annoying to have to turn of the hole ISE >everytime I wan't to try something new! > > >Thanks, >Ivan. What should happen is you save your source, then when you run Impact it runs all the processes needed. If you didn't save the source it should prompt you.Article: 139780
On 13 tra, 23:22, Mike Harrison <m...@whitewing.co.uk> wrote: > > What should happen is you save your source, then when you run Impact it runs all the processes > needed. If you didn't save the source it should prompt you. No, that's not it. I mean, i can't programm the board twice in a row. Impact reports a blue message 'Program succeeded' every time, but only the first time does it transfer the new design. For every next time, it just keeps transfering the original, that is - the first transfered design since the ISE was loaded. So, that has nothing to do with saving the project, or running all the steps for synthesis/implementation/generation. Just to mention, I do save all the files before proceeding with other steps. Always. Thanks, Ivan.Article: 139781
Guys, Wanted to let you know abou the FPGA Twitter at http://twitter.com/fpga , it is a great way to follow what is hapenning in the FPGA world.. -VikramArticle: 139782
On Mon, 13 Apr 2009 07:59:49 -0700 (PDT), JSreeniv <sreenivas.jyothi@gmail.com> wrote: >Hi all, >Could anyone please explain this requirement in detail or by steps: > ><Bit 16 of the rcom_ctl_sts register shall return a 0 within 1us when >a Manchester error has been acknowledged by the processor writing a 1 >to bit 16 of the rcom_ctl_sts register> > >I am waiting for the response...its Urgent > >Sreeniv This page has some information about the Manchester Mark 1 and errors on its main storage system. http://www.computer50.org/mark1/MM1.html It might be of some help. - BrianArticle: 139783
On Apr 13, 4:58=A0pm, ivan <ivan.so...@gmail.com> wrote: > On 13 tra, 23:22, Mike Harrison <m...@whitewing.co.uk> wrote: > > > > > What should happen is you save your source, then when you run Impact it= runs all the processes > > needed. If you didn't save the source it should prompt you. > > No, that's not it. I mean, i can't programm the board twice in a row. > Impact reports a blue message 'Program succeeded' every time, but only > the first time does it transfer the new design. For every next time, > it just keeps transfering the original, that is - the first transfered > design since the ISE was loaded. > > So, that has nothing to do with saving the project, or running all the > steps for synthesis/implementation/generation. Just to mention, I do > save all the files before proceeding with other steps. Always. > > Thanks, > Ivan. Thinking as Impact and ISE are the two separated tools, and you yourself are the user You would use ISE to generate the bit file, and you use IMPACT to download any bit file to an X-device, make sure you have selected the desired bit file everytime you wanna to load it btw, have you updated to the latest service pack yet ?Article: 139784
On Mon, 13 Apr 2009 15:22:01 -0700 (PDT), Vikram <vkr101@gmail.com> wrote in comp.dsp: > Guys, > > Wanted to let you know abou the FPGA Twitter at http://twitter.com/fpga > , it is a great way to follow what is hapenning in the FPGA world.. No, it is not. Do you think everyone is as idiotic as you are? -- Jack Klein Home: http://JK-Technology.Com FAQs for comp.lang.c http://c-faq.com/ comp.lang.c++ http://www.parashift.com/c++-faq-lite/ alt.comp.lang.learn.c-c++ http://www.club.cc.cmu.edu/~ajo/docs/FAQ-acllc.htmlArticle: 139785
On Apr 13, 11:58=A0pm, ales.gor...@gmail.com wrote: > On Apr 13, 5:16=A0pm, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Apr 13, 5:47=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > > wrote: > > > > Xilinx COE memory initialization files... > > > > ...support at least four data formats. > > > > PATTERN and BRANCH_LENGTH_VECTOR formats > > > are too specialized to concern me right now. > > > > MEMORY_INITIALIZATION_VECTOR is easy enough. > > > > But what's the point of COEFDATA? =A0Isn't it just > > > another way to specify a bunch of numbers in a memory? > > > > Any pointers into the Xilinx docs would be appreciated. =A0 > > > The best I found was an informative, but far from > > > complete, page on "COE File Syntax". > > > > Am I right in guessing that Coregen uses the > > > "coefficient" data in various different ways, > > > depending on what sort of filter it's creating, > > > and there may not necessarily be a one-to-one > > > correspondence between coefficient values and > > > memory contents? > > > > Thanks in advance > > > -- > > > Jonathan Bromley, Consultant > > > > DOULOS - Developing Design Know-how > > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > > The contents of this message may contain personal views which > > > are not the views of Doulos Ltd., unless specifically stated. > > > dont ever use COE unless needed for some special reason > > > Antti- Hide quoted text - > > > - Show quoted text - > > And I use only a non-symetric FIR variant because of that. > > Cheers, > > Ales Ales, the FILTERS is the special reason i mentioned :) if you make just a block ram with init values with coregen, then it is mostly easier, better use other methods for init than COE specially if the ram is used as instruction storage for a soft processor its relativly easy to add .BMM file to ISE project and run data2mem post implementation to update the memory AnttiArticle: 139786
Since the Cyclone III is now 2 years on the market I wonder whether Altera's low-cost line is the Arria branch (with Arria II recently announced) or whether there will be Cyclone IV. Since we see the Spartan VI coming from Xilinx this year, one would expect a competing Altera product as well.Article: 139787
On Apr 14, 9:31=A0am, acd <acd4use...@lycos.de> wrote: > Since the Cyclone III is now 2 years on the market I wonder whether > Altera's low-cost line is > the Arria branch (with Arria II recently announced) or whether there > will be Cyclone IV. > Since we see the Spartan VI coming from Xilinx this year, one would > expect a competing Altera product > as well. interesting yes. i made a april fools joke about next Altera thing to be flash based and have ColdFire hard core, but on the serious side it pretty interesting yes.. s-6 are not yet there, and on some points Cyclone-III are better than S-6 so the new Altera low cost family could be REALLY interesting !! AnttiArticle: 139788
acd <acd4usenet@lycos.de> writes: > (with Arria II recently announced) URL? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 139789
On Apr 14, 10:35=A0am, Petter Gustad <newsmailco...@gustad.com> wrote: > acd <acd4use...@lycos.de> writes: > > (with Arria II recently announced) > > URL? > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? www.altera.comArticle: 139790
Hi all, We are developing a new Spartan3A DSP board with DDR. Since we need a x32 DDR a good and low cost option seems low power mobile DDR SDRAM like this: http://www.micron.com/products/partdetail?part=MT46H16M32LFCM-6%20IT It seems to be very popular since it has very low power comsumption (1.8V), high bandwidth and low cost; Beagle Board, DSP boards... Problem: It is not directly supported by Xilinx MIG (memory interface generator) . The question is: did anyone sucesfully use MIG core with such SDRAM? Cheers, AlesArticle: 139791
On Apr 14, 11:19=A0am, ales.gor...@gmail.com wrote: > Hi all, > > We are developing a new Spartan3A DSP board with DDR. Since we need a > x32 DDR a good and low cost option seems low power mobile DDR SDRAM > like this:http://www.micron.com/products/partdetail?part=3DMT46H16M32LFCM= -6%20IT > It seems to be very popular since it has very low power comsumption > (1.8V), high bandwidth and low cost; Beagle Board, DSP boards... > > Problem: It is not directly supported by Xilinx MIG =A0(memory interface > generator) . > The question is: did anyone sucesfully use MIG core with such SDRAM? > > Cheers, > > Ales well even Cyclone-II can do mobile DDR with northwest IP core http://www.altera.com/products/ip/iup/memory/m-nwl-mobile-ddr-sdram.html so one could think Xilinx FPGA's can do it as well.. but all Xilinx docs say it not tested to work on Xilinx, only that it MAY but needs customer qualifications, etc :( if mobile DDR will also not be supported on S-6 then, well it could be a turning point to choose Altera ;) of course it could that the mobile DDR will work ok, and Xilinx just doesnt want to bother to add the support for it... AnttiArticle: 139792
Are there any press releases etc. which indicates that the Arria II will be competing with Cyclone III in price, e.g. that a 2AGX125 costs less than (or the same as) an EP3C120? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 139793
On 14 Apr., 13:02, Petter Gustad <newsmailco...@gustad.com> wrote: > Are there any press releases etc. which indicates that the Arria II > will be competing with Cyclone III in price, e.g. that a 2AGX125 costs > less than (or the same as) an EP3C120? The description of the Arria products states that they target cost- sensitive applications. "Arria=AE II GX FPGAs are the lowest power FPGAs with up to 3.75-Gbps transceivers. Designed for cost-sensitive applications, Arria II GX FPGAs are based on a 40-nm, full-featured FPGA architecture that includes adaptive logic modules (ALMs), digital signal processing (DSP) blocks, embedded RAM, and a hard PCIe IP core. This FPGA family provides the optimal logic, memory, and DSP capabilities to address your needs. Unlike other 3-Gbps FPGAs, Arria II GX FPGAs offer improvements in usability that allow you to complete your projects faster." http://www.altera.com/products/devices/arria-fpgas/arria-ii-gx/aiigx-index.= jsp But of course, the high-speed links make the devices more expensive. AndreasArticle: 139794
On Apr 14, 10:39=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Apr 14, 11:19=A0am, ales.gor...@gmail.com wrote: > > > Hi all, > > > We are developing a new Spartan3A DSP board with DDR. Since we need a > > x32 DDR a good and low cost option seems low power mobile DDR SDRAM > > like this:http://www.micron.com/products/partdetail?part=3DMT46H16M32LF= CM-6%20IT > > It seems to be very popular since it has very low power comsumption > > (1.8V), high bandwidth and low cost; Beagle Board, DSP boards... > > > Problem: It is not directly supported by Xilinx MIG =A0(memory interfac= e > > generator) . > > The question is: did anyone sucesfully use MIG core with such SDRAM? > > > Cheers, > > > Ales > > well even Cyclone-II can do mobile DDR with northwest IP corehttp://www.a= ltera.com/products/ip/iup/memory/m-nwl-mobile-ddr-sdram.html > > so one could think Xilinx FPGA's can do it as well.. but all Xilinx > docs say > it not tested to work on Xilinx, only that it MAY but needs customer > qualifications, etc :( > > if mobile DDR will also not be supported on S-6 then, well it could be > a turning point to choose Altera ;) > > of course it could that the mobile DDR will work ok, and Xilinx just > doesnt want to bother to add the support for it... > > Antti Yes Antti, we heard all that. I am more interested in any experience from anyone who has already done this sucesfully. AlesArticle: 139795
On Apr 14, 2:08=A0pm, acd <acd4use...@lycos.de> wrote: > On 14 Apr., 13:02, Petter Gustad <newsmailco...@gustad.com> wrote: > > > Are there any press releases etc. which indicates that the Arria II > > will be competing with Cyclone III in price, e.g. that a 2AGX125 costs > > less than (or the same as) an EP3C120? > > The description of the Arria products states that they target cost- > sensitive applications. > "Arria=AE II GX FPGAs are the lowest power FPGAs with up to 3.75-Gbps > transceivers. Designed for cost-sensitive applications, Arria II GX > FPGAs are based on a 40-nm, full-featured FPGA architecture that > includes adaptive logic modules (ALMs), digital signal processing > (DSP) blocks, embedded RAM, and a hard PCIe IP core. This FPGA family > provides the optimal logic, memory, and DSP capabilities to address > your needs. Unlike other 3-Gbps FPGAs, Arria II GX FPGAs offer > improvements in usability that allow you to complete your projects > faster."http://www.altera.com/products/devices/arria-fpgas/arria-ii-gx/ai= igx-... > > But of course, the high-speed links make the devices more expensive. > > Andreas well at EW2009 there was a guy who claimed he got 10$ pricing for smallest Arria II (50k pcs) that is well below Lattice price what would be 17$ (1KLUT/1$) AnttiArticle: 139796
On Apr 14, 2:38=A0pm, ales.gor...@gmail.com wrote: > On Apr 14, 10:39=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Apr 14, 11:19=A0am, ales.gor...@gmail.com wrote: > > > > Hi all, > > > > We are developing a new Spartan3A DSP board with DDR. Since we need a > > > x32 DDR a good and low cost option seems low power mobile DDR SDRAM > > > like this:http://www.micron.com/products/partdetail?part=3DMT46H16M32= LFCM-6%20IT > > > It seems to be very popular since it has very low power comsumption > > > (1.8V), high bandwidth and low cost; Beagle Board, DSP boards... > > > > Problem: It is not directly supported by Xilinx MIG =A0(memory interf= ace > > > generator) . > > > The question is: did anyone sucesfully use MIG core with such SDRAM? > > > > Cheers, > > > > Ales > > > well even Cyclone-II can do mobile DDR with northwest IP corehttp://www= .altera.com/products/ip/iup/memory/m-nwl-mobile-ddr-sdram.html > > > so one could think Xilinx FPGA's can do it as well.. but all Xilinx > > docs say > > it not tested to work on Xilinx, only that it MAY but needs customer > > qualifications, etc :( > > > if mobile DDR will also not be supported on S-6 then, well it could be > > a turning point to choose Altera ;) > > > of course it could that the mobile DDR will work ok, and Xilinx just > > doesnt want to bother to add the support for it... > > > Antti > > Yes Antti, we heard all that. I am more interested in any experience > from anyone who has already done this sucesfully. > > Ales hm try contacting northwest directly? they should know if mobile DDR on S3 is doable AnttiArticle: 139797
On Apr 13, 10:21=A0pm, halong <cco...@netscape.net> wrote: > On Apr 13, 4:58=A0pm, ivan <ivan.so...@gmail.com> wrote: > > > > > > > On 13 tra, 23:22, Mike Harrison <m...@whitewing.co.uk> wrote: > > > > What should happen is you save your source, then when you run Impact = it runs all the processes > > > needed. If you didn't save the source it should prompt you. > > > No, that's not it. I mean, i can't programm the board twice in a row. > > Impact reports a blue message 'Program succeeded' every time, but only > > the first time does it transfer the new design. For every next time, > > it just keeps transfering the original, that is - the first transfered > > design since the ISE was loaded. > > > So, that has nothing to do with saving the project, or running all the > > steps for synthesis/implementation/generation. Just to mention, I do > > save all the files before proceeding with other steps. Always. > > > Thanks, > > Ivan. > > Thinking as Impact and ISE are the two separated tools, and you > yourself are the user > > You would use ISE to generate the bit file, and you use IMPACT to > download any bit file to an X-device, make sure you have selected the > desired bit file everytime you wanna to load it > > btw, have you updated to the latest service pack yet ?- Hide quoted text = - > > - Show quoted text - Are you abolutely sure the bit file on the hard drive has been updated. Maybe something went wrong during bitgen. Check the logs Check the time stamp of the bit file right after you do a compile. Technically, Impact checks that the file on the disk is different from the file you downloaded before and would give you a pop up message mentioning that fact.Article: 139798
acd wrote: > On 14 Apr., 13:02, Petter Gustad <newsmailco...@gustad.com> wrote: >> Are there any press releases etc. which indicates that the Arria II >> will be competing with Cyclone III in price, e.g. that a 2AGX125 costs >> less than (or the same as) an EP3C120? > > The description of the Arria products states that they target cost- > sensitive applications. > "Arria® II GX FPGAs are the lowest power FPGAs with up to 3.75-Gbps > transceivers. Designed for cost-sensitive applications, Arria II GX > FPGAs are based on a 40-nm, full-featured FPGA architecture that > includes adaptive logic modules (ALMs), digital signal processing > (DSP) blocks, embedded RAM, and a hard PCIe IP core. This FPGA family > provides the optimal logic, memory, and DSP capabilities to address > your needs. Unlike other 3-Gbps FPGAs, Arria II GX FPGAs offer > improvements in usability that allow you to complete your projects > faster." > http://www.altera.com/products/devices/arria-fpgas/arria-ii-gx/aiigx-index.jsp > > But of course, the high-speed links make the devices more expensive. > > Andreas My understanding is that the Arria are a bit more expensive than Cyclones, but much cheaper than Stratix devices. The two things that make them more expensive (but worth more) are the high speed links and the faster logic (they use Stratix-style ALMs rather than Cyclone-style LEs. So if you need fast links, they are "low-cost". If not, they are not as low cost as the Cyclones. But maybe that will change with the Arria II and future families.Article: 139799
On Apr 14, 4:19=A0am, ales.gor...@gmail.com wrote: > Hi all, > > We are developing a new Spartan3A DSP board with DDR. Since we need a > x32 DDR a good and low cost option seems low power mobile DDR SDRAM > like this:http://www.micron.com/products/partdetail?part=3DMT46H16M32LFCM= -6%20IT > It seems to be very popular since it has very low power comsumption > (1.8V), high bandwidth and low cost; Beagle Board, DSP boards... > > Problem: It is not directly supported by Xilinx MIG =A0(memory interface > generator) . > The question is: did anyone sucesfully use MIG core with such SDRAM? > > Cheers, > > Ales What speed are you running the DDR memory at? I have used Mobile DDR with Lattice ECP2, and found that their fancy DDR I/O built into the part does not work with LVCMOS because it needed a "preamble detector" that uses low voltage (1/4 Vcc) as a detection mechanism. I ended up rolling my own using generic DDR I/O and without using DQS as an input clock, but I should preface this with the fact that I only clock the parts at 125 MHz (DDR 250). You could theoretically use MIG to generate sources and then modify it yourself. The power-up reset sequence is very different for Mobile vs Standard DDR. Check the data sheets. If you're not up to the task of rolling your own, though I would suggest looking at DDR2 instead. It runs at the same voltage and is very well supported by MIG. For a single-chip solution with very short routes, you don't even need to use external terminating resistors. Just set the IO standard to SSTL type I (low drive) and set the lowest drive on the DDR2 chip. You still use more pins to get Vref, etc. but you might get the bandwidth you need in a narrower (16b vs. 32b) package. regards, Gabor
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