Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Mar 12, 1:05=A0pm, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote: > hi > > i have a question on how to infer a block ram with mismatched ports. <snip> > could somebody help me out how to modify this so that the data width > on port A is 32 bits and on port B 8 bits. > sorry but i could not find an example for this or figure it out > myself. 1. Infer 4 dual memories that are each 8 bits wide (i.e. the width of the smaller port, in this case the 'B' side). 2. Use the lower two bits of the B side address gated with the 'B' side write enable to generate 4 individual write enables for the above mentioned 4 dual port memories. 3. The 'A' side write enable goes to each of the four dual port memories. 4. During a 'B' side read, read from all 4 memories in parallel and then again using the lower 2 'B' side address bits, mux the appropriate byte to the 'B' side data out port. There are other ways of doing this but the above is fairly forward to follow. The key ideas here are: - If you want to use FPGA internal memory and it doesn't happen to support mismatched data widths, then you have to instantiate multiple smaller memories that have a data width that matches your smaller data width. - Wrap logic around those multiple memories to give the whole thing the appearance of implementing dual port with mismatched data width sizes. Kevin JenningsArticle: 130001
I am going to address these out of order. 3) I can understand not having a budget. Since my college was using a parallel port logic analyzer on the PC(cheap and limited input), I assumed you may have had access to some older technology like this. Just laying around in the labs. 2) The Spartan3e development kit is $150 each. Your students can certainly buy their own if they want. That is only one engineering book in cost. Some of your students may want to do that. You may want to list places where your students can order the boards. Since, you are a Xilinx XUP, I doubt you will be the only professor looking to use the tools at hand. A good student may see this as a sound investment, especially if the boards you have available in the labs are limited in number and availability. 1) I agree the soft core will give you more flexibility for observation. I don't think that writing a new GUI for chipscope versus extra explanation written in the lab guides is worth the effort. Have fun torturing....I mean educating your students. ;-) "wicky" <wicky.zhang@gmail.com> wrote in message news:4ef30bf0-e18c-43f0-b082-05188f210ee9@i29g2000prf.googlegroups.com... In the course about 8086/8088 processor, I just plan to introduce this CPU and its bus transactions. if those younker are interested in more about FPGA, i think "no problem", :-) The reason why I choose FPGA for the course lab is: 1) Soft core 8086/8088 is more flexible, we could monitor the bus transactions and even the cpu internal signal. Furthermore, we could introduce other processor system based on the same hardware platform. 2) We are a member of Xilinx XUP, we have several V2PRO and Spartan3E boards. 3) We have no budget to prepare logic analyzer for every student Btw: There is a opensource 8086/8088 for FPGA in this web: http://www.ht-lab.com/freecores/cpu8086/cpu86.html Many thanks! Wicky On Mar 12, 1:42 am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > Uhm....Do you really need chipscope for this? Is the purpose to introduce > the students to FPGAs or to introduce them to the 8086/8088 processor and > their bus transactions? > > Granted it has been a bit more than 10 years since I was in college. But I > had multiple courses dealing with the 8086/8088 as well as courses with > the > 6800 Motorola processor. I even had a DSP course with a TI processor. > Seeing the BUS transaction during those classes was a simple lab > introducing > us to a digital logic analyzer. > > Seems to me throwing the FPGA and Chipscope in when it may not need to be > there is overly complex. > > If the purpose is to introduce them to FPGAs, then I think it is better to > keep the students using the standard tools they can download from xilinx. > Just have a good lab write up and there shouldn't be a problem. I remember > many a lab where the tool used was complex, but the Lab kept us to a small > subset of the functionality as an introduction to the tool. Adding a new > yet simpler GUI, will only hinder the students wehn they start going to > job > interviews and say they know how to use chipscope version "easy_mode". > > "wicky" <wicky.zh...@gmail.com> wrote in message > > news:c388a3b0-f07f-4572-8c61-a49743aaa57c@s13g2000prd.googlegroups.com... > > > > >I found Chipscope is too difficult to learn for college students, it > > has too much options. I want to develop a simple gui software and > > using it in a 8086/8088 FPGA embedded system. For example, students > > can understand a bus transaction with just a simple mouse click in > > this software, instead of setting so much options in the tranditional > > Chipscope software. Can anyone give me some information about this > > work? Thank you! > > > Best Regards, > > > Wicky- Hide quoted text - > > - Show quoted text -Article: 130002
On 10 Mrz., 18:35, austin <aus...@xilinx.com> wrote: > John_H, > > Aye, that is the rub: success. > > Austin Austin, if their silicon works at all, and is low cost as advertized, it will defenetly find some happy customers just because the PACKAGE options alone: 3500 cells, 10 Kbyte RAM ==> 3x4 mm !!! 15000 cells, 32 Kbyte RAM ==> 5x6 mm if I compare that with Spartan-3A family ?? Actel is supposed to have now IGLOO15 in 4x4 package but that as tiny as hell, so doesnt really count, so as do not Altera MAX2's in 6x6 Doesnt even matter how bad the tools, for this size:package density options the silicon will find instant customers very quickly in my opinion. So would Xilinx sell S4 to new customers if only the package options would be better than S3 of course. AnttiArticle: 130003
On Mar 12, 4:27 am, StYm <satyam.dwiv...@gmail.com> wrote: > On Mar 12, 2:34 am, sky46...@trline4.org wrote: > > > > > satyam <satyam.dwiv...@gmail.com> wrote: > > >I want to interface matlab with the Xilinx Virtex-II pro board. Intent > > >is to give input from matlab to the FPGA and to read the ouput of FPGA > > >in matlab. > > >Problem is in interfacing speed. I need high speed interface, of the > > >order of 2 mega bits per second (Mbps). Seems RS-232 will be > > >inadequate for my purpose. From Documents interface through ethernet > > >seems to be a viable option but I am not sure. To summarize I want > > >answers and suggestions on following: > > >1). FPGA to PC communication by ethernet ? > > > Yes works. > > > >2). What can be the maximum speed ? > > > 1000Mbps depending on your ethernet chip(s). > > > >3). How to transfer data on ethernet by matlab ? > > > C socket programming > > > >4). Is it possible to write inputs (60 Mega bits) to some memory on > > >FPGA board and then read it from there to do the computation ? > > > If your ethernet PHY manages 100 Mbps in full duplex, then yes. Ethernet is a complex and expensive protocol (in terms of time) to implement. How about the opencores USB 1.1 PHY/IP and using libusb on the PC side? It seems to me this would be much less time consuming than ethernet. > > > >Please let me know if you have any suggestion for me. > > > Do you need realtime or synchronous operation? > > > Btw, there's lots of good stuff to be found via the google force luke ;) > > Dear Dave and sky46, thank you for responding. > > Seems Matlab has something in intrument control toolbox. I need to > explore this. > How about ethernet core for FPGA. The core provided by xilinx is too > expensive to buy. Have found an ethernet from opencore website. > Trying to make it work.Article: 130004
On Mar 12, 2:29=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > On 10 Mrz., 18:35, austin <aus...@xilinx.com> wrote: > > > John_H, > > > Aye, that is the rub: =A0success. > > > Austin > > Austin, > > if their silicon works at all, and is low cost as advertized, it will > defenetly find some happy customers just because the PACKAGE options > alone: > > 3500 cells, 10 Kbyte RAM =A0 =3D=3D> 3x4 mm !!! > 15000 cells, 32 Kbyte RAM =3D=3D> 5x6 mm > > if I compare that with Spartan-3A family ?? > > Actel is supposed to have now IGLOO15 in 4x4 package but that as tiny > as hell, so doesnt really count, so as do not Altera MAX2's in 6x6 > > Doesnt even matter how bad the tools, for this size:package density > options the silicon will find instant customers very quickly in my > opinion. > > So would Xilinx sell S4 to new customers if only the package options > would be better than S3 of course. > > Antti Antti, when a much smaller company (like Actel) wants to compete and survive in this field, it must pick a protected niche. (Ultra- small size, lowest power, non-volatility, different logic-to-pin ratio, you name it!). It is up to Xilinx and Altera to evaluate these "niches" and assess whether they are attractive for us. Sometimes they are, sometimes they are not. What is right for Actel is not necessarily right for Xilinx and Altera. The user, however, benefits from the variety made possible by the wide differences between companies, and their genetic diversification. "Survival of the fittest" combined with a diverse gene-pool. It works for plants and animals... Peter AlfkeArticle: 130005
Wicky, You can try to use Scanseer boundary-scan software instead of ChipScope. Scanseer can display waveforms for FPGA pins and it's quite easy-to-use. But, unfortunately, it can't show internal FPGA's signals. Scanseer home is http://www.scanseer.com Kind regards, SK On Mar 11, 4:58 pm, wicky <wicky.zh...@gmail.com> wrote: > I found Chipscope is too difficult to learn for college students, it > has too much options. I want to develop a simple gui software and > using it in a 8086/8088 FPGA embedded system. For example, students > can understand a bus transaction with just a simple mouse click in > this software, instead of setting so much options in the tranditional > Chipscope software. Can anyone give me some information about this > work? Thank you! > > Best Regards, > > WickyArticle: 130006
On 12 Mrz., 23:32, Peter Alfke <pe...@xilinx.com> wrote: > On Mar 12, 2:29 pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 10 Mrz., 18:35, austin <aus...@xilinx.com> wrote: > > > > John_H, > > > > Aye, that is the rub: success. > > > > Austin > > > Austin, > > > if their silicon works at all, and is low cost as advertized, it will > > defenetly find some happy customers just because the PACKAGE options > > alone: > > > 3500 cells, 10 Kbyte RAM ==> 3x4 mm !!! > > 15000 cells, 32 Kbyte RAM ==> 5x6 mm > > > if I compare that with Spartan-3A family ?? > > > Actel is supposed to have now IGLOO15 in 4x4 package but that as tiny > > as hell, so doesnt really count, so as do not Altera MAX2's in 6x6 > > > Doesnt even matter how bad the tools, for this size:package density > > options the silicon will find instant customers very quickly in my > > opinion. > > > So would Xilinx sell S4 to new customers if only the package options > > would be better than S3 of course. > > > Antti > > Antti, when a much smaller company (like Actel) wants to compete and > survive in this field, it must pick a protected niche. (Ultra- small > size, lowest power, non-volatility, different logic-to-pin ratio, you > name it!). > It is up to Xilinx and Altera to evaluate these "niches" and assess > whether they are attractive for us. Sometimes they are, sometimes they > are not. What is right for Actel is not necessarily right for Xilinx > and Altera. The user, however, benefits from the variety made possible > by the wide differences between companies, and their genetic > diversification. > "Survival of the fittest" combined with a diverse gene-pool. It works > for plants and animals... > Peter Alfke Peter, would you describe "CONSUMER" as a niche market? sorry, I could not resist. Xilinx, Altera, Actel, Lattice have nothing to compete with the SiliconBlue, the only one possible having competing solutions is QuickLogic (ArticLink). Sure SiliconBlue is not targetting the general purpose FPGA market, so you can call it niche. But consumer market is a pretty damn big niche! AnttiArticle: 130007
On Mar 12, 8:11=A0pm, ghel...@lycos.com wrote: > On Mar 12, 3:42 am, sdf <drop...@gmail.com> wrote: > > > Hi. > > Got this board. > > Two questions. > > 1. Is it possible to use this board as prototype of some USB device > > without any solder rewiring? > > 2. Is it possible to have, let's say, nios2-terminal.exe on computer > > side, computer connected to board by USB and have *something* but not > > Nios2 to communicate with nios2-terminal.exe? In any words, it's > > possible to use JTAG wire as RS232 port without using Nios2 CPU? > > 1: No. =A0The USB port is only for programming. > > 2: No. =A0Well, not really no, but you would need to replicate the way > Altera/NIOS tunnels the serial port through JTAG, and I think it's > highly unlikely that you will find documentation on that. I found that: USB <-> FT245BL <-> EPM3128ATC100 <- JTAG -> EP3C25F324NES I probably will need to do something with EPM3128 and use JTAG link.. if someone have the same intentions as me, it will be interesting to hear any suggestions.Article: 130008
Peter Alfke wrote: > Antti, when a much smaller company (like Actel) wants to compete and > survive in this field, it must pick a protected niche. (Ultra- small > size, lowest power, non-volatility, different logic-to-pin ratio, you > name it!). > It is up to Xilinx and Altera to evaluate these "niches" and assess > whether they are attractive for us. Sometimes they are, sometimes they > are not. What is right for Actel is not necessarily right for Xilinx > and Altera. The user, however, benefits from the variety made possible > by the wide differences between companies, and their genetic > diversification. > "Survival of the fittest" combined with a diverse gene-pool. It works > for plants and animals... and, of course, Xilinx could always Buy them out. They did that to get Coolrunner, and Coolrunner is now looking 'long in the tooth' [in FPGA terms] with no recent advances. MAX IIZ and MachXO are in a space Xilinx is missing. -jgArticle: 130009
Antti wrote: > Austin, > > if their silicon works at all, and is low cost as advertized, it will > defenetly find some happy customers just because the PACKAGE options > alone: > > 3500 cells, 10 Kbyte RAM ==> 3x4 mm !!! > 15000 cells, 32 Kbyte RAM ==> 5x6 mm Hi Antti, I have not seen price promises, or package info yet. Got any links for this ? (or send me a PDF ?) -jgArticle: 130010
I am trying to interface a 32 bit blockram to microblaze (spartan 3E), using the User-Address ip support in the "Create and import peripheral". I have instantiated a black box blockram 32x256 and it works fine with read and write operations of 32bit datawidth. But how can i perform 8bit write and read operations? i know there are the BE (byte_enable) bus, but i cant see how this can work with a single block ram .. i would need 4 block ram=B4s inorder to perform byte write and reads or what? i can see that in the never FPGA`s (according to Block Memory Generator 2.6 .pdf) that block ram supports Byte-Writes, which is EXACTLY what i need .. but im using the spartan 3E which dosent support this feature .. are there any work around so i dont need 4 block ram=B4s of 8x256 instead of a single 32x256 ? ... is there a way to create more than one block ram instance that only uses one block-ram in hardware? Regards KimArticle: 130011
We use xilinx xaui core in our Ethernet design, we choose XGMII as our internal interface. And now, I am confused. I found that the data between START(0xfb) andTERMINATE(0xfd) will all be transmit through XAUI. So, if we use xaui core in Ethernet design, do we need to transmit preamble, sfd and FCS? Now, I think may be we need preamble and sfd to meet XGMII standard, but what about FCS. In 802.3ae chapter46, it said CRC is done by RS.Please help me to make sure frame format, Thank you!Article: 130012
Sorry, I don't think that I describe my idea clearly because of my poor english. First, the XUP lab now serves for other course such as "introduction to VHDL" and so on. Now I hope we can utilize this lab more effectively. From the 8086/8088 lab on, we may port a serials of course to this lab and form a more close relation among those courses. As for 8086/8088 lab which is not so much relative with fpga technology, a more simple debugging software will facilitate to most students. This course will focus on 8086/8088 system only, but with a soft core 8086/8088 lab, I think it will be helpful for the successive FPGA relative courses in which students will use those special software such as chipscope. Many thanks! Wicky On Mar 13, 4:17=A0am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > I am going to address these out of order. > 3) I can understand not having a budget. =A0Since my college was using a > parallel port logic analyzer on the PC(cheap and limited input), I assumed= > you may have had access to some older technology like this. Just laying > around in the labs. > > 2) The Spartan3e development kit is $150 each. Your students can certainly= > buy their own if they want. =A0That is only one engineering book in cost. = Some > of your students may want to do that. =A0You may want to list places where= > your students can order the boards. > Since, you are a Xilinx XUP, I doubt you will be the only professor lookin= g > to use the tools at hand. A good student may see this as a sound investmen= t, > especially if the boards you have available in the labs are limited in > number and availability. > > 1) I agree the soft core will give you more flexibility for observation. I= > don't think that writing a new GUI for chipscope versus extra explanation > written in the lab guides is worth the effort. > > Have fun torturing....I mean educating your students. ;-) > > "wicky" <wicky.zh...@gmail.com> wrote in message > > news:4ef30bf0-e18c-43f0-b082-05188f210ee9@i29g2000prf.googlegroups.com... > In the course about 8086/8088 processor, I just plan to introduce this > CPU and its bus transactions. if those younker are interested in more > about FPGA, i think "no problem", :-) > > The reason why I choose FPGA for the course lab is: > > 1) Soft core 8086/8088 is more flexible, we could monitor the bus > transactions and even the cpu internal signal. =A0 Furthermore, we could > introduce other processor system based on the same hardware platform. > > 2) We are a member of Xilinx XUP, we have several V2PRO and Spartan3E > boards. > > 3) We have no budget to prepare logic analyzer for every student > > Btw: There is a opensource 8086/8088 for FPGA in this web: > > http://www.ht-lab.com/freecores/cpu8086/cpu86.html > > Many thanks! > > Wicky > > On Mar 12, 1:42 am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote: > > > > > Uhm....Do you really need chipscope for this? Is the purpose to introduc= e > > the students to FPGAs or to introduce them to the 8086/8088 processor an= d > > their bus transactions? > > > Granted it has been a bit more than 10 years since I was in college. But= I > > had multiple courses dealing with the 8086/8088 as well as courses with > > the > > 6800 Motorola processor. I even had a DSP course with a TI processor. > > Seeing the BUS transaction during those classes was a simple lab > > introducing > > us to a digital logic analyzer. > > > Seems to me throwing the FPGA and Chipscope in when it may not need to b= e > > there is overly complex. > > > If the purpose is to introduce them to FPGAs, then I think it is better = to > > keep the students using the standard tools they can download from xilinx= . > > Just have a good lab write up and there shouldn't be a problem. I rememb= er > > many a lab where the tool used was complex, but the Lab kept us to a sma= ll > > subset of the functionality as an introduction to the tool. Adding a new= > > yet simpler GUI, will only hinder the students wehn they start going to > > job > > interviews and say they know how to use chipscope version "easy_mode". > > > "wicky" <wicky.zh...@gmail.com> wrote in message > > >news:c388a3b0-f07f-4572-8c61-a49743aaa57c@s13g2000prd.googlegroups.com...= > > > >I found Chipscope is too difficult to learn for college students, it > > > has too much options. I want to develop a simple gui software and > > > using it in a 8086/8088 FPGA embedded system. For example, students > > > can understand a bus transaction with just a simple mouse click in > > > this software, instead of setting so much options in the tranditional > > > Chipscope software. Can anyone give me some information about this > > > work? Thank you! > > > > Best Regards, > > > > Wicky- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > - Show quoted text -Article: 130013
No Virtex-5/FX has been, or ever will be, released. ... If you mean the Virtex-5/FXT, then that's a whole 'nother story :) Last November, I heard "soon", as in, synchronized with the next major release of ISE (10.1?) I hope Xilinx introduces Systemverilog synthesis with ISE 10.1 -- competitor Altera has been taking the lead for so long now in that area... (whether anyone actually uses Systemverilog synthesis in a large FPGA-project, is a debate for another day...) "Udo" <WeikEngOff@aol.com> wrote in message news:3faa5be2-29b9-4e51-b4fc-a0b7f94e9bd6@u69g2000hse.googlegroups.com... > Hello Antti, Peter and ..., > > yep, meanwhile many, many months later - the same question... > V5-FX? > > Thanks and greetings > UdoArticle: 130014
I thought Altera uses one of FTDI 's USB/RS-232 bridge-chips in their programming solution. <ghelbig@lycos.com> wrote in message news:d5104cd3-98c1-449d-85ff-ebc074207564@e23g2000prf.googlegroups.com... > On Mar 12, 3:42 am, sdf <drop...@gmail.com> wrote: >> Hi. >> Got this board. >> Two questions. >> 1. Is it possible to use this board as prototype of some USB device >> without any solder rewiring? >> 2. Is it possible to have, let's say, nios2-terminal.exe on computer >> side, computer connected to board by USB and have *something* but not >> Nios2 to communicate with nios2-terminal.exe? In any words, it's >> possible to use JTAG wire as RS232 port without using Nios2 CPU? > > 1: No. The USB port is only for programming. > > 2: No. Well, not really no, but you would need to replicate the way > Altera/NIOS tunnels the serial port through JTAG, and I think it's > highly unlikely that you will find documentation on that. > > Sorry.Article: 130015
Please, please, please fix the DVD installation-wizard, so that you can install the 32-bit (Webpack) tools on a 64-bit platform. (This goes for both MS Windows and Linux.) I really hate having to manually traverse the bin/lin32 subdir (or bin/nt) on the DVD, because the toplevel installer determines I have a 64-bit OS/platform, then cryptically tells me "registration ID not valid!" (I'd be nice if the installer said the Evaluation-ID is only good for the 32-bit version of the tools, rather than producing a totally misleading error-message.) An little checkbox in the installer-GUI that lets the user override the installer's platform-autodetect would be really nice : "install 32-bit tools?"Article: 130016
On 2008-03-12, wicky <wicky.zhang@gmail.com> wrote: > In the course about 8086/8088 processor, I just plan to introduce this > CPU and its bus transactions. if those younker are interested in more > about FPGA, i think "no problem", :-) > > The reason why I choose FPGA for the course lab is: > > 1) Soft core 8086/8088 is more flexible, we could monitor the bus > transactions and even the cpu internal signal. Furthermore, we could > introduce other processor system based on the same hardware platform. > > 2) We are a member of Xilinx XUP, we have several V2PRO and Spartan3E > boards. > > 3) We have no budget to prepare logic analyzer for every student > > Btw: There is a opensource 8086/8088 for FPGA in this web: > > http://www.ht-lab.com/freecores/cpu8086/cpu86.html That is an interesting idea, I have been thinking about exactly the same thing actually as we currently use a rather old platform for our bus transaction lab here which make it hard to demonstrate more interesting features such as bus mastering. (Although we would probably use the tg68 core instead, as our current course material is heavily based on the MC68000. Anyway, if you know that you are only interested in bus transactions you could use a synthesized logic analyzer that is instantiated in your design. Look at for example http://www.ise.pw.edu.pl/~wzab/fpgadbg/ for something which seems fairly reasonable although I haven't tried it myself. If you need to select signals dynamically I agree with other posters that chipscope shouldn't be that hard to setup/use. However, if you find that you have very special needs that cannot be taken care of by chipscope it is actually possible to make your own logicanalyzer that you can dynamically insert into a design. I have an example of how to do that at the following URL: http://www.da.isy.liu.se/~ehliar/pyxdl/ And a screenshot of the tool: http://www.da.isy.liu.se/~ehliar/stuff/logicanalyzer.png The current version presents an ASCII interface to the logic analyzer but it should be quite simple to write a waveform viewer although I haven't had time to worry about that. (The Python code is quite ugly but I thought that it was better to release the code than to just let it collect dust in my home directory.) /AndreasArticle: 130017
Using registers is probably the best way to go. You avoid the marketing mathematics of any given vendor, and to be honest with fmax being primarily limited by routing now, it seems that designs have very few levels of logic meaning the logic:register ratio is close to 1:1 for high performance IP.Article: 130018
On Mar 13, 2:31 am, lm317t <lm3...@gmail.com> wrote: > On Mar 12, 4:27 am, StYm <satyam.dwiv...@gmail.com> wrote: > > > On Mar 12, 2:34 am, sky46...@trline4.org wrote: > > > > satyam <satyam.dwiv...@gmail.com> wrote: > > > >I want to interface matlab with the Xilinx Virtex-II pro board. Intent > > > >is to give input from matlab to the FPGA and to read the ouput of FPGA > > > >in matlab. > > > >Problem is in interfacing speed. I need high speed interface, of the > > > >order of 2 mega bits per second (Mbps). Seems RS-232 will be > > > >inadequate for my purpose. From Documents interface through ethernet > > > >seems to be a viable option but I am not sure. To summarize I want > > > >answers and suggestions on following: > > > >1). FPGA to PC communication by ethernet ? > > > > Yes works. > > > > >2). What can be the maximum speed ? > > > > 1000Mbps depending on your ethernet chip(s). > > > > >3). How to transfer data on ethernet by matlab ? > > > > C socket programming > > > > >4). Is it possible to write inputs (60 Mega bits) to some memory on > > > >FPGA board and then read it from there to do the computation ? > > > > If your ethernet PHY manages 100 Mbps in full duplex, then yes. > > Ethernet is a complex and expensive protocol (in terms of time) to > implement. How about the opencores USB 1.1 PHY/IP and using libusb > on the PC side? It seems to me this would be much less time consuming > than ethernet. > > Dear lm317t, can you give me instructions as to how to setup USB 1.1 PHY/IP ? What files to download, from where ?? and how to make it work ? Thank you in advance. StYm > > > >Please let me know if you have any suggestion for me. > > > > Do you need realtime or synchronous operation? > > > > Btw, there's lots of good stuff to be found via the google force luke ;) > > > Dear Dave and sky46, thank you for responding. > > > Seems Matlab has something in intrument control toolbox. I need to > > explore this. > > How about ethernet core for FPGA. The core provided by xilinx is too > > expensive to buy. Have found an ethernet from opencore website. > > Trying to make it work.Article: 130019
Hi. I see how Quartus synthesizer removes unused parts of algorithm implemented in HDL, optimizes it and so on. Other synthesizers probably do the same. My question is almost offtopic: is there any method to do the same in software code? Is the starting point is in compiler theory or there're also another topics?Article: 130020
On 13 Mrz., 09:45, sdf <drop...@gmail.com> wrote: > Hi. > I see how Quartus synthesizer removes unused parts of algorithm > implemented in HDL, optimizes it and so on. > Other synthesizers probably do the same. > My question is almost offtopic: is there any method to do the same in > software code? > Is the starting point is in compiler theory or there're also another > topics? Compiler optimizations are done differently. Each method it self is a lot more primitive than what is done for hardware optimization, but a decent compiler uses a larger set of these optimization strategies. I did many years of research in circuit optimization and allways wondered whether it would be fruitful to apply more computational intensive algorithms to critical code in software. A starting point could be the work done in compiling software descriptions to hardware. UC Berkeley for example simulates the code and postulates theories on the data range of variables. (e.g. int x is allways smaller than 100). They then use solvers to proof these assumptions. If proven, the information can be used for optimization. This approach is computationally very expensive. Also: It turns out that many variable are only written once during program execution. This means that there is a big optimization potential to optimize a program after startup. Java and .NET do this to some extend but in principle you could also do with C and other languages. Kolja SulimmaArticle: 130021
On 13 Mrz., 05:29, bku...@engineer.com wrote: > meaning the logic:register ratio is close to > 1:1 for high performance IP. As a counter example: The ration is almost 2:1 in the example given by the OP. Kolja SulimmaArticle: 130022
On Mar 13, 11:05=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > Also: It turns out that many variable are only written once during > program execution. This means that there > is a big optimization potential to optimize a program after startup. > Java and .NET do this to some extend > but in principle you could also do with C and other languages. It looks like a paradox, but it looks like functional programming. Paradox is in likeness of such low-level computation device and such high-level methods... I just noticed that if to transform algorithm written in C to something which looks like FP program, it is then can be more easily rewritten into HDL, manually, of course.Article: 130023
I generate PCI-Express PHY with GTP wizard.the datawidth is selected
8bit or 16bit. but ,both the phy wrapper MAXDELAY constrain are
"1.0" ! as you know,it is hard to meet the timing. I expect the 16 bit
datawidth can reduce Clk Freq.
(* MAXDELAY="1.0" *) wire tile0_txcharisk0_r;
(* MAXDELAY="1.0" *) wire tile0_txdetectrx0_r;
(* MAXDELAY="1.0" *) wire tile0_txelecidle0_r;
(* MAXDELAY="1.0" *) wire tile0_txchardispmode0_r;
(* MAXDELAY="1.0" *) wire [7:0] tile0_txdata0_r;
(* MAXDELAY="1.0" *) wire tile0_txchardispmode1_r;
(* MAXDELAY="1.0" *) wire tile0_txcharisk1_r;
(* MAXDELAY="1.0" *) wire tile0_txdetectrx1_r;
(* MAXDELAY="1.0" *) wire [7:0] tile0_txdata1_r;
(* MAXDELAY="1.0" *) wire tile0_txelecidle1_r;
can it modified 2.0 or commented out?
Article: 130024USB 1.1 PHY core in Verilog: http://www.opencores.org/projects.cgi/web/usb_phy/overview You can do your own IP from usb specs or use the USB 1.1 IP on opencores.org. How to use an AVR to implement USB gives lots of helpful info on USB protocol http://www.obdev.at/products/avrusb/index.html Libusb for the PC: http://sf.net/projects/libusb Libusb doesn't run on windows, just mac, linux, bsd Also the super simple route is to use a USB-UART chip like the ft232rl from digikey. They go up to 3 Mbps. No driver writing for you if you go this route. On Mar 13, 3:24 am, StYm <satyam.dwiv...@gmail.com> wrote: > On Mar 13, 2:31 am, lm317t <lm3...@gmail.com> wrote: > > > On Mar 12, 4:27 am, StYm <satyam.dwiv...@gmail.com> wrote: > > > > On Mar 12, 2:34 am, sky46...@trline4.org wrote: > > > > > satyam <satyam.dwiv...@gmail.com> wrote: > > > > >I want to interface matlab with the Xilinx Virtex-II pro board. Intent > > > > >is to give input from matlab to the FPGA and to read the ouput of FPGA > > > > >in matlab. > > > > >Problem is in interfacing speed. I need high speed interface, of the > > > > >order of 2 mega bits per second (Mbps). Seems RS-232 will be > > > > >inadequate for my purpose. From Documents interface through ethernet > > > > >seems to be a viable option but I am not sure. To summarize I want > > > > >answers and suggestions on following: > > > > >1). FPGA to PC communication by ethernet ? > > > > > Yes works. > > > > > >2). What can be the maximum speed ? > > > > > 1000Mbps depending on your ethernet chip(s). > > > > > >3). How to transfer data on ethernet by matlab ? > > > > > C socket programming > > > > > >4). Is it possible to write inputs (60 Mega bits) to some memory on > > > > >FPGA board and then read it from there to do the computation ? > > > > > If your ethernet PHY manages 100 Mbps in full duplex, then yes. > > > Ethernet is a complex and expensive protocol (in terms of time) to > > implement. How about the opencores USB 1.1 PHY/IP and using libusb > > on the PC side? It seems to me this would be much less time consuming > > than ethernet. > > Dear lm317t, > > can you give me instructions as to how to setup USB 1.1 PHY/IP ? What > files to download, from where ?? and how to make it work ? > > Thank you in advance. > StYm > > > > > >Please let me know if you have any suggestion for me. > > > > > Do you need realtime or synchronous operation? > > > > > Btw, there's lots of good stuff to be found via the google force luke ;) > > > > Dear Dave and sky46, thank you for responding. > > > > Seems Matlab has something in intrument control toolbox. I need to > > > explore this. > > > How about ethernet core for FPGA. The core provided by xilinx is too > > > expensive to buy. Have found an ethernet from opencore website. > > > Trying to make it work.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z