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On Sep 29, 11:33 am, emu <e...@ecubics.com> wrote: > Personally, I don't like the proprietary USB-JTAG interface on the > nexys boards. One more piece of software to maintain. Would prefer > just the standard 20 pin header I could connect the standard > programming cable. It's not really proprietary. Well, the software is, but the hardware isn't - the nexys schematics show the USB details, unlike for the xilinx-partnered boards where the USB page is missing. I was able to get the open source xc3sprog utility working with it. It is kind of nice to have both power and programming in the USB cable. But nexys also has the same single inline .100" header as the old spartan 3 kit, so you can buy their parallel port cable for $12 and use impact if you prefer. Having both a plain spartan 3 kit and a nexys available, I find that for some purposes one is preferable, and for some the other... both were quite affordable (but would second the recommendation for the largest device each board supports)Article: 124876
Well, All Virtex 5 family members: LX, LXT, SX, SXT are all now in full production. Stratix 3 is sampling the first (and simplest) device. There are no transceivers planned for Stratix 3. Virtex 5 FXT is scheduled to be released, soon, for initial engineering samples. Contact your FAE for the early access program. Other than actually having and shipping 65nm parts for almost one and one half years with no competition at all, as opposed to just releasing the first 65nm high performance FPGA one and one half years late to market (which speaks to supply, and available feature sets and available parts): you haven't given us enough information to really help you. AustinArticle: 124877
Dan, I recommend the Digilent Spartan 3, or 3E, boards. I have used them in tutorials, and find that there is a lot of collateral available as these are used by many colleges and schools, also. The boards will support the MicroBlaze(tm) soft processor which is a RISC 32 bit style machine, for which there is a c compiler, and many tools available. Austin dan.walmsley@gmail.com wrote: > i have downloaded the xilinx webpack and gone through a few tutorials > on the software can anyone recommend a good starter board, that would > cope with trying a small softcore microcontroller. > > If anyone has any good tutorials or educational material on FPGAs > please could you email me. > > Any advice would be greatly appreciated. > > Dan Walmsley >Article: 124878
On 9 Okt., 16:57, austin <aus...@xilinx.com> wrote: > Well, > > All Virtex 5 family members: LX, LXT, SX, SXT are all now in full > production. ALL 5 ? I count 4 ? AnttiArticle: 124879
Hello newsgroup, I am trying to understand the Xilinx reference design (XAPP391: Design of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)). When performing the functional simulation (which is included in the download files) the error detection signal of the decoder becomes active on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE and 0x2BE. The testbench provided with the design connects the encoder and the decoder, so that only legal 10bit words get into the decoder. 8bit --> enc --> 10bit --> dec --> 8bit So why does these errors occur ? Has someone already used that reference design and has met difficulties in simulation or real hardware implementation ? Thank you. Best regards AndreArticle: 124880
Hi I'm using Cyclone II EP2C8 in PQFP208 package and DDR DIMM. And I'm wondering how to distribute clock signal. DIMM has 6 clock signals (3 differential pairs). I figure out two solution: 1. Use differential output PLL_OUT and split signals to three DIMM input. 2. Use 6 general purpose FPGA IO to distribute three pairs of clock and shifted clock. (This IO pins will be single-ended not differential) Which soulution is better and will have lower skew to other DDR signals? Or maybe do that on different way? -- PGWArticle: 124881
On Tue, 09 Oct 2007 08:32:09 -0700, "ALuPin@web.de" <ALuPin@web.de> wrote: >Hello newsgroup, > >I am trying to understand the Xilinx reference design (XAPP391: Design >of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)). >When performing the functional simulation (which is included in the >download files) the error detection signal of the decoder becomes >active >on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE >and 0x2BE. > >The testbench provided with the design connects the encoder >and the decoder, so that only legal 10bit words get into the decoder. >8bit --> enc --> 10bit --> dec --> 8bit > >So why does these errors occur ? Has someone >already used that reference design and has met >difficulties in simulation or real hardware implementation ? > Is it possible that there is error verification conditions in the testbench, ie. the errors are injected on purpose to see if error checking works?Article: 124882
15 family members is what I count from the data sheet.... There is no such thing as SX (no transceivers). Sorry about that, SX always is SXT. http://direct.xilinx.com/bvdocs/publications/ds100.pdf page 2, Table 1. Austin Antti wrote: > On 9 Okt., 16:57, austin <aus...@xilinx.com> wrote: >> Well, >> >> All Virtex 5 family members: LX, LXT, SX, SXT are all now in full >> production. > > ALL 5 ? > I count 4 ? > > Antti >Article: 124883
Group, I have the need to copy a Max 7000s device that was originally developed under Max+Plus II. I am not able to locate the original project file (my bad) but I do have a working device that I can copy from. Originally the device was programmed under Max+Plus II using a byteblaster cable, but today I only have a USB blaster. My problem appears to be a double whammy: that Max+Plus II does not seem to support the USB Blaster and Quartus does not support the Examine feature for 7000S devices (according to what I discovered in a search of this group). I am presenlty at a loss for ideas. If anyone has any suggestions of how I could copy this device, I would greatly appreciate your help.Article: 124884
> Grumps wrote: >> [posted to comp.arch.fpga + comp.lang.vhdl] >> Hi All >> I've had a quote from a 3rd party to develop a floating point FFT core >> for us (1Mpt). Probably for a Xilinx Virtex5 SXT. >> Obviously I'd like to get some more quotes, but would like to know if you >> have any recommendations? >> Thanks. 4DSP offers a floating point FFT and it seems like the only one available today with true IEEE-754 (float) arithmetic for FPGA devices. The same Commercial Off The Shelf core can be used for FFT ranging from 256 points to 1M points in Virtex-4 and Virtex-5 FPGA. No need for expensive redesign! Documentation and a bit true model are available on 4DSP's website: http://www.4dsp.com/fft.htm Cheers PierrickArticle: 124885
LowSNR <jkrauss@lowsnr.com> writes: > I've been doing some development work over the past year or so on the > Atmel FPSLIC platform. I've run out of time on the license for the > Mentor software that came with the dev kit, and am wondering if there > are any open-source projects that can handle VHDL design for the > FPSLIC. I've looked at Slipway, and that looks promising for the > backend, but as far as I can tell it only supports Icarus Verilog > entry? Porting my design to Verilog isn't something I'd like to do, > so any suggestions would be greatly appreciated. Hi LowSNR, Sorry about the month-late reply... Unfortunately at this point the slipway/abits combination isn't really ready to replace Atmel's tools. And, given their total apathy towards the chip and positive developments elsewhere, this may continue to be the case indefinitely. I should mention, however, that they recently published a new version of their software suite, and I think they switched synthesis tool vendors. You might be able to cajole another demo license out of them... - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 124886
Andreas Ehliar <ehliar@lysator.liu.se> writes: > I have also seen that some people have reverse engineered part of the > Xilinx bitstream format. There was a link to a "debit" utility posted > a couple of month ago which could take a .bit file and present a view > similar to the FPGA editor. The website was quickly taken down and the > author said that he didn't intend the tool to become publicly known > before it was more finished if I remember correctly. Debit was > available at http://www.ulogic.org/trac before it disappeared. It appears to be back now. - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380Article: 124887
"Pierrick" <pierrickv@4dsp.com> wrote in message news:1191953351.407840.18230@22g2000hsm.googlegroups.com... >> Grumps wrote: >>> [posted to comp.arch.fpga + comp.lang.vhdl] >>> Hi All >>> I've had a quote from a 3rd party to develop a floating point FFT core >>> for us (1Mpt). Probably for a Xilinx Virtex5 SXT. >>> Obviously I'd like to get some more quotes, but would like to know if >>> you >>> have any recommendations? >>> Thanks. > > 4DSP offers a floating point FFT and it seems like the only one > available today with true IEEE-754 (float) arithmetic for FPGA > devices. The same Commercial Off The Shelf core can be used for FFT > ranging from 256 points to 1M points in Virtex-4 and Virtex-5 FPGA. No > need for expensive redesign! Documentation and a bit true model are > available on 4DSP's website: http://www.4dsp.com/fft.htm Thanks. Have you used this core before?Article: 124888
Noway2 wrote: > Group, > > I have the need to copy a Max 7000s device that was originally developed > under Max+Plus II. I am not able to locate the original project file > (my bad) but I do have a working device that I can copy from. Originally > the device was programmed under Max+Plus II using a byteblaster cable, > but today I only have a USB blaster. > > My problem appears to be a double whammy: that Max+Plus II does not seem > to support the USB Blaster and Quartus does not support the Examine > feature for 7000S devices (according to what I discovered in a search of > this group). Both pathways must have a means to verify a device. The question you need to ask, is "has the device you have been secured?" > I am presenlty at a loss for ideas. Surely not ? Idea #1 : Find/Build a cable that MAX+II does support Idea #2 : Look harder for the source file(s) > > If anyone has any suggestions of how I could copy this device, I would > greatly appreciate your help. -jgArticle: 124889
Pierrick wrote: > 4DSP offers a floating point FFT and it seems like the only one > available today with true IEEE-754 (float) arithmetic for FPGA > devices. That is a bold statement and I would be interested which other available cores you compared yours to and ruled out that they do not support true IEEE-754 arithmetic? Cheers, GuenterArticle: 124890
I am working with an EDK design that utilizes an MPMC2 core. There are several clocks associated with this core. All of the clocks are created using DCM's and inverters. I am failing timing b/c cross- clock domain paths are being analyzed and are failing. My first question is: Should these paths be analyzed for this core? I didn't see any info in the documentation. I know the calibration routine/architecture is supposed to take care of finding the sweet spot to sample data so a TIG should apply for that logic. But I am not certain if every cross-domain path in the core is a TIG. Second question: If all the paths are indeed TIG's, then is there an easy way to make the constraints? The only timing constraint currently implemented is the input clock to the FPGA that is fed to the DCM chain. Then all other clocks constraints are automatically determined by the tools. Is there a similar feature where I can tell the tools to apply TIG constraints to certain DCM-derived clock paths? Thanks!Article: 124891
On Oct 9, 12:53 pm, Guenter Dannoritzer <kratfkryk...@spammotel.com> wrote: > Pierrick wrote: > > 4DSP offers a floating point FFT and it seems like the only one > > available today with true IEEE-754 (float) arithmetic for FPGA > > devices. > > That is a bold statement and I would be interested which other available > cores you compared yours to and ruled out that they do not support true > IEEE-754 arithmetic? > > Cheers, > > Guenter Fair enough! The message however is related to the original thread where the user is looking for a 1M points FFT. It looks indeed as if there are some alternatives for shorter lengths FFTs (<32k points).Article: 124892
Hi all, Just read an interesting article in Xilinx's xcel publication. Lots of technical detail, and no "marketing" to speak of. http://www.xilinx.com/publications/magazines/dsp_03/xc_pdf/p42-44-3dsp-andraka.pdf After reading this I had a couple of burning questions I'm wondering if anyone, or Ray himself, can shed some light on 1) 1.2 Gsamples/s seems like a pretty high input data rate - no doubt there are a few applications around that need it. But what about the 1.2Gsamples/sec data output rate? What systems can take the FFT outputs at this rate, and do something sensible with the data? Although the FFT engine has done a bunch of processing, it hasn't really reduced the amount of data in any way? I mean you can't go hookup 1.2Gsps to a pc based platform. Even 10 gigabit ethernet cannot transport this amount of data, let alone the cpu do much processing with it. 2)I didn't understand the comparison between the 66 Gflop fpga FFT core and the 48 GFLOP Cell processor implementation. Was the cell processor implementation processing samples at 1.2Gsps? was it also at from 32 to 2048 point transform? Cheers AndrewArticle: 124893
This may be out of the question (due to school/corporate politics), but you'll save a lot of time and money if you just get your own desktop-PC Intel Core 2 Duo E6850 (3.0GHz) . Although I haven't tried Quartus II, for Xilinx Webpack 9.2i.03 and Sysnopsys Design Compiler, the E6850 is roughly 50-60% faster than our old AMD SocketAM2 X2/5200+ (2.6GHz, 2x1MB cache.) In other words a 100 minute job on the X2/5200+ took only 65 minutes on the Intel E6850. Both machines were configured the same: 8GB DDR2/667 ECC unbuffered RAM, Centos 4.5 x86_64 same hard-drive (moved it from one PC to the other) (^^^Centos 4.5 is an open-source clone of Redhat Enterprise Linux 4 update 5) <jjohnson@cs.ucf.edu> wrote in message news:1191621614.063609.92350@57g2000hsv.googlegroups.com... > > Thanks in advance for the help! > ---------------------------------------- > > My employer just acquired a SunFire server w 16 dual-core Opterons > (model 8220, 2.8 GHz) and 128GB of RAM. > > Despite the faster clock and memory interface, it's running my Quartus > jobs slower than a 2-year old dual-core Opteron (2.4 GHz Model 250). > > > Can anyone suggest the biggest-bang-for-the-buck things to look at? > > I don't have root privelege, but I'm trying to help the I.T folks > along. > > uname -a: > Linux monster 2.6.9-55.ELlargesmp #1 SMP Fri Apr 20 16:46:56 EDT 2007 > x86_64 x86_64 x86_64 GNU/Linux Heh, looks like you're running Redhat Enterprise Linux 4 Update 5.Article: 124894
Quartus-II 7.2 has improved upon Quartus's Systemverilog preprocessor:
`define SET_REG( x, y ) reg_``y <= x
`define CONCAT( x, y, z ) x``_``y``_``z
assign `CONCAT( bus0, func1, endpoint0 ) = 1'b0;
and named 'end' blocks:
module x;
...
always_comb begin : my_junk
end : my_junk
endmodule : x
But 7.2 still doesn't like inline (automatic) variable declarations:
for ( int i = 0; i < 32; ++i ) // <-- 'int i' causes ERROR
Article: 124895On 9 Okt., 18:55, mk <kal*@dspia.*comdelete> wrote: > On Tue, 09 Oct 2007 08:32:09 -0700, "ALu...@web.de" <ALu...@web.de> > wrote: > > > > > > >Hello newsgroup, > > >I am trying to understand the Xilinx reference design (XAPP391: Design > >of a 16b/20b Encoder/Decoder Using a CoolRunner-II CPLD)). > >When performing the functional simulation (which is included in the > >download files) the error detection signal of the decoder becomes > >active > >on decoding of 10bit words 0x1C7, 0x1BE, 0x13E, 0x0BE > >and 0x2BE. > > >The testbench provided with the design connects the encoder > >and the decoder, so that only legal 10bit words get into the decoder. > >8bit --> enc --> 10bit --> dec --> 8bit > > >So why does these errors occur ? Has someone > >already used that reference design and has met > >difficulties in simulation or real hardware implementation ? > > Is it possible that there is error verification conditions in the > testbench, ie. the errors are injected on purpose to see if error > checking works?- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - I think that there is no error injection in the testbench. In the error cases the 8bit words presented by the decoder are OK.Article: 124896
I need to find a cheap UK supplier for a spartan 3 development kit, prepherably USB, it needs to be suitable to implement a small softcore processor and ideal for someone with no previous experience. I can find lots of products in the US but none in the UK. Dan WalmsleyArticle: 124897
Greatest. SystemVerilog looks much attractive than conventional VHDL \Verilog and even SystemC. There is only one reason why I haven't started yet synthesable altera project in SV: I wasn't sure about claimed support SV by the Quartus. Tell us please, have you got already successful completed at least one altera's SV project? Digitally yours, Michael Tsvetkov http://www.jpegls.com On Oct 10, 9:44 am, "Systemv User" <syst...@nowhere.net> wrote: > Quartus-II 7.2 has improved upon Quartus's Systemverilog preprocessor: > > `define SET_REG( x, y ) reg_``y <= x > `define CONCAT( x, y, z ) x``_``y``_``z > > assign `CONCAT( bus0, func1, endpoint0 ) = 1'b0; > > and named 'end' blocks: > > module x; > ... > always_comb begin : my_junk > > end : my_junk > > endmodule : x > > But 7.2 still doesn't like inline (automatic) variable declarations: > > for ( int i = 0; i < 32; ++i ) // <-- 'int i' causes ERRORArticle: 124898
Hi all,
I meet some problems in the P&R process of my design.
The Place & Route Report shows the following messages. Because it stoped at
Phase 6 for a long time, I paused it and it shows there's 1 net unrouted.
----------------- Place & Route Report ------------------------
Phase 6: 2645 unrouted; (0) REAL time: 17 secs
Ctrl-C interrupt detected.
Please choose one of the following options:
1. Ignore interrupt and continue processing.
2. Exit program normally at next checkpoint.
This will save the best results so far
after concluding the current processing.
3. Exit program immediately.
4. Cancel the current job and move to the next one
at the next check point.
Enter choice --> 2
User requested termination
Phase 7: 1 unrouted; (0) REAL time: 3 mins 2 secs
-------------------------------------------------------------------------
I opened the ncd file and shows the Unrouted Nets visually. I changed the
position of one of the SLICE and then it automatically re-route. The
previously Unrouted Nets dissapered and are no longer listed.
But I'm not completely sure that all of the nets have been routed properly,
because in the following step, Generated Programming File, it complains that
ERROR:PhysDesignRules:801 - The network <digital_inst/inst1/fir1/N42592> has
<1> routing conflicts.
ERROR:PhysDesignRules:801 - The network <digital_inst/inst1/fir1/N42591> has
<1> routing conflicts.
ERROR:Bitgen:25 - DRC detected 2 errors and 24 warnings.
I checked the ncd file again in the FPGA Editor, however, it seems these two
nets have already been routed. what is "the routing conflicts" meant to? Any
possible solutions?
I would appreciated your help,
Ju, Jian
Article: 124899On Oct 9, 10:24 pm, austin <aus...@xilinx.com> wrote: > 15 family members is what I count from the data sheet.... > > There is no such thing as SX (no transceivers). > > Sorry about that, SX always is SXT. > > http://direct.xilinx.com/bvdocs/publications/ds100.pdf > > page 2, Table 1. > > Austin > > Antti wrote: > > On 9 Okt., 16:57, austin <aus...@xilinx.com> wrote: > >> Well, > > >> All Virtex 5 family members: LX, LXT, SX, SXT are all now in full > >> production. > > > ALL 5 ? > > I count 4 ? > > > Antti thanks friends Our intention is to use the kit for embedded applications. The choice is "Virtex-5 LXT ML505 Evaluation Platform (HW-V5-ML505- UNI-G)". Is there any other FPGA kit which has better configuration(and feautures) in Altera than Virtex-5 specially for embedded applications.
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Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z