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hi I think I am close to get it fully working, but some things are still messy MPMC2 has only verilog but EDK simulation works better in VHDL, so so far all attempts to get the all thing to work on init the onchip memories in simulator still fail when toplevel is VHDL memory init would work, but mpmc2 verilog doesnt load properly in simulator, or it loads after manual fix, but the it doesnt see the glbl.v :( when having the toplevel as verilog then the EDK system and MPMC2 and DDR2 simulation models all load properly in simulator, but then I cant init the onchip memories any more. so what is the proper way to simulate such designs? AnttiArticle: 112551
Hi to everyone, I'm trying to generate a 5-10 ns pulse width out of an edge, without the use of any clock, just with internal delays. Unfortunately I can imagine how much this delay will depend on temperature and voltage and how much the width will be affected, but still I have some margins (anyway everything will be tested in a thermal chamber to verify functionalities). So far I developed a sort of a "ripple-counter" with an auto-reset for each FF (Q(0) will asynchronously reset Q(0)) so that I can start an internal oscillation (a clock!). After that a normal counter can be realized on the basis of this clock, allowing to build a pulse. Once the pulse is over a reset is generated to stop asynchronously all the FFs. Does it make sense at all? I think no! :-) Any ideas? thanks a lot Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 112552
Austin Lesea wrote: > Andrew, > > What version of software are you using? > > If you read the link: > > http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=1&sTechX_ID=al_slack > > you would see that 1/2 the total system jitter is what should be your > slack (at least), or shortening your clock constraint by 1/2 your p-p > system jitter. > > This answer record details how uncertainty is dealt with by the tool: > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23710 > > Austin Hi Austin, I'm using ISE 8.2i targetting a Spartan 3 device. I was not surprised to see the 800ps jitter treated as 400ps uncertainty, because I read about the factor 1/2 in your article. I was glad to fail timing closure, because now, when I get it to pass, I know jitter has been factored-in. Thanks, Andrew.Article: 112553
Hi. Is there any ready open source (or not so open) logic analyzers based on FPGA + (S|D)RAM? I mean, we need to connect bunch of wires to FPGA, record all samples to RAM and download it somehow to PC. Also, is there any good starting points and/or known pitfalls, e.g. what should I read first? Thanks in advance.Article: 112554
"Davy" <zhushenli@gmail.com> writes: > But as we know, there is no xxxx signal in real digital world. So is > there any better method to solve the problem? Maybe: case(branch) ... ... [all the possible branch] ... ... // synthesis translate_off default: signal = 8'bx; // synthesis translate_on endcase I wish simulators could have a switch or similar to make sure that if you had something like: somesel = 1'bx; if (somesel) somevar = something; else someelsevar = somethingelse; would case ALL assigned vars in BOTH if branches to become x. Same thing for the ? operator. Of course one can write the above as if statement as case(somesel). Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 112555
Davy wrote: > Hi all, > > I always found people like to add default branch like below: > case(branch) > ... ... > [all the possible branch] > ... ... > default: signal = 8'bx; > > And my friend told me it's for simulation cause. When branch not hit > all the possible case, the branch must have something like xxxx. So we > set signal to xxxx to let xxxx pass go on and help us to find the bug. > > If I set default: signal = 0; the xxxx problem will be hidden and hard > to find the bug. > > But as we know, there is no xxxx signal in real digital world. So is > there any better method to solve the problem? > > Best regards, > Davy In addition to "xxxxx" there may be some other choices. 1. (simulation debug) Use $display instead of signal assignment, for example: default: $display ($time,"<%m> ERROR: non-speicified branch is taken"); Synthesis tools drop all $display statements, while simulators report about an error in a runtime. It eliminates the need to observe "x" on selected signals in the waveform viewer. Also, in some cases "x" may propagate to "signal" from the previos logic (such as unitialized memory arrays). Use of "$display" will isolate bugs better. 2. (emulation debug) Create observable error status register, associate each one of register's bit with different "case" statements and set them to "1" when corresponding default branch is taken: default: uncomplete_case_reg[0] <= 1'b1; Finally, some synthesis tools (such as Synopsys DC) produce warnings for case statements in which not all possible cases are covered. To get this reporting, you have to use pragma "// synopsys full case" with the case statement. Regards, -AlexArticle: 112556
> I'd like to protect theses IP as much as I can. You should make up your mind about what the threats are. This is called a "threat model". Write down a list of who might want to violate your licensing terms and what his incentive is (eg quantity of money gained or not spent). Now figure out how each of the threats can complete, and how you can protect against that. A protection is usually good enough, if it raises the bar higher than the incentive of the attacker (eg more expensive to copy than to buy). Writing netlist obfuscation tools costs time, and with "found somewhere on the net" grade tools you risk delivered product quality. It may well be that you are wasting resources on this one, while your threat actually is completely different. Just image a customer who pays 10 units but produces 10000. No obfuscation tool will keep him from doing that. It won't even raise his cost (=lower his incentives to do it). A proper threat model helps you to identify where your threats are and which ones are effective to counter. Don't spend your resources on measures that counter nothing. Kind regards, MarcArticle: 112557
On Fri, 24 Nov 2006 17:28:40 GMT, "Homer J Simpson" <nobody@nowhere.com> wrote: > >"John Fields" <jfields@austininstruments.com> wrote in message >news:9ijdm2t4l2ee5cik1vlhhotrh9m6v3l6aj@4ax.com... > >>>You seem to have a fixation about where YOUR next banana will be inserted. > >> Not me.. > >And yet you constantly make comments about other people being gay, comments >based solely on your own fixations. Based on experience? --- In a sense, in that I emailed one of your posts over to a gay friend of mine for him to read and he said that you were definitely queer but that he wouldn't touch you with a ten-foot pole. -- JFArticle: 112558
Have a look at ST M25Pxx devices. Although Altera don't say it, these devices are compatible with EPCSx ... but at a much lower price ;o) Check EPCS and M25P datasheet to convince yourself. ---------------------------------------------- Posted with NewsLeecher v3.5 Beta 5 * http://www.newsleecher.com/?usenetArticle: 112559
"Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message news:4566d05d$0$11352$3b214f66@tunews.univie.ac.at... > Is it essential to connect the unused OE and GCLR-Pins of an Altera > MAX3000A to ground??? > the Quartus Pin-file shows GND+ for this pins, with the following meaning > of GND+: > -- GND+ : Unused input pin. It can also be used to report unused > dual-purpose pins. > -- This pin should be connected to GND. It may also be connected to a > -- valid signal on the board (low, high, or toggling) if that > signal > -- is required for a different revision of the design. > Can I turn on/off the usage of this OE-Pins somewhere in Quartus or where > can I see the usage??? > > Thanks, Manfred > The unused inputs do not affect internal logic; but if you leave a CMOS input floating, there is a risk of charge build-up on the gate capacitance of the input transistors. If the gate voltage is somewhere in-between Vdd and Vss, both the N-channel and P-channel transistors conduct, cuasing an increase in power consumption.Article: 112560
Al wrote: > Hi to everyone, I'm trying to generate a 5-10 ns pulse width out of an > edge, without the use of any clock, just with internal delays. > Unfortunately I can imagine how much this delay will depend on > temperature and voltage and how much the width will be affected, but > still I have some margins (anyway everything will be tested in a thermal > chamber to verify functionalities). > So far I developed a sort of a "ripple-counter" with an auto-reset for > each FF (Q(0) will asynchronously reset Q(0)) so that I can start an > internal oscillation (a clock!). > After that a normal counter can be realized on the basis of this clock, > allowing to build a pulse. Once the pulse is over a reset is generated > to stop asynchronously all the FFs. > Does it make sense at all? I think no! :-) > > Any ideas? > > thanks a lot > > Al > Take a look at the DCM_STANDBY macro Xilinx uses as a workaround for Virtex4 DCM problems. They have a circuit in there (ringosc.vhd) that provides a clock even if no external clock is present. See http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=21127Article: 112561
Petter Gustad wrote: > > I wish simulators could have a switch or similar to make sure that if > you had something like: ... > would case ALL assigned vars in BOTH if branches to become x. Same > thing for the ? operator. The ?: operator does that already. In fact, it is significantly smarter than that. If the condition is x, it only produces an x at the outputs for bits that don't match between the two selected values. That keeps the result from being overly pessimistic. This cannot be generalized to if-statements, because you can do arbitrarily complex things in an if-statement, not just assign to variables. How do you maybe-display something? How do you maybe-call a task? How do you maybe-disable a block? How do you maybe-execute more nested conditionals that would only assign to some variables but not others? If you assume the worst, the result could be far too pessimistic. It could be so pessimistic that you cannot make any progress in simulation. If an outer condition is X, but a nested condition is false, you would be Xing out a variable that could not actually have been assigned. Or the design might only assign to some bits of a vector or array, but you end up Xing out the whole thing because it was potentially assigned. It might be impossible to simulate your design being initialized. You could waste a lot of time tracking down problems that turned out not to be real problems on closer examination, eventually giving up and turning off this special switch. The over-optimism of Verilog if-statements with X conditions is a problem in the language, but I don't think that this frequently heard suggestion would provide a viable solution. Another possible approach would be to add an optional elsex to the if-statement syntax, to allow the user to specify the behavior to take on an X (similar to using a default in a case). Then the user could use their better understanding of the situation to decide what to do, and avoid over-pessimism.. The problem with this is that it is not automatic. The user has to remember to do it for each if-statement, and correctly figure out what result they want. Note that switching if-statements containing assignments into assignment statements containing ?: where possible would give better results, but at the cost of making the code harder to read. I have yet to hear a good solution to this if-statement problem, which is probably why it works the way it does, even though it is flawed.Article: 112562
"John Fields" <jfields@austininstruments.com> wrote in message news:dujem21f677h2vec8hu7nuu3fodllja2ne@4ax.com... > In a sense, in that I emailed one of your posts over to a gay friend > of mine for him to read and he said that you were definitely queer > but that he wouldn't touch you with a ten-foot pole. No, he said YOU were gay and he wasn't interested.Article: 112563
> In addition to "xxxxx" there may be some other choices. > 1. (simulation debug) Use $display instead of signal assignment, for > example: > > default: $display ($time,"<%m> ERROR: non-speicified branch is > taken"); > > Synthesis tools drop all $display statements, while simulators report > about an error in a runtime. It eliminates the need to observe "x" on > selected signals in the waveform viewer. Also, in some cases "x" may > propagate to "signal" from the previos logic (such as unitialized > memory arrays). Use of "$display" will isolate bugs better. This sort of thing can end up with lots of false positives though, that can obscure the real bugs. (i.e. you'll get lots of these printed before reset, etc) Cheers, Jon From null@example.net Fri Nov 24 14:56:27 2006 Path: newssvr21.news.prodigy.net!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newsfeed.telusplanet.net!newsfeed2.telusplanet.net!newsfeed.telus.net!cycny01.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny04.POSTED!dd653b87!not-for-mail From: Richard The Dreaded Libertarian <null@example.net> Subject: Re: board - T562.jpg User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2006.11.24.22.56.50.591939@example.net> Newsgroups: alt.binaries.schematics.electronic,comp.arch.fpga,sci.electronics.design References: <4563f1a6$0$486$cc7c7865@news.luth.se> <Xr19h.59126$r4.34900@newsfe3-gui.ntli.net> <vp29h.39$p9.4@edtnps82> <ooe9m2ld470u6rg7tqku3vfchh83960698@4ax.com> <GF79h.100$p9.93@edtnps82> <dlvam25q5c9n959lsspek87p0v8bkgie21@4ax.com> <kQk9h.176$p9.1@edtnps82> <4e1cm2ph7tkl0pm0ek7hin684pquochl58@4ax.com> <uVn9h.217$p9.135@edtnps82> <ph5cm2lv6pguo2rlnnqnc1q0pievcv5cgk@4ax.com> <HIp9h.232$p9.43@edtnps82> <9ijdm2t4l2ee5cik1vlhhotrh9m6v3l6aj@4ax.com> <cZF9h.1872$p9.802@edtnps82> <dujem21f677h2vec8hu7nuu3fodllja2ne@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 24 Date: Fri, 24 Nov 2006 22:56:27 GMT NNTP-Posting-Host: 71.103.148.12 X-Complaints-To: abuse@verizon.net X-Trace: trndny04 1164408987 71.103.148.12 (Fri, 24 Nov 2006 17:56:27 EST) NNTP-Posting-Date: Fri, 24 Nov 2006 17:56:27 EST Xref: prodigy.net alt.binaries.schematics.electronic:127472 comp.arch.fpga:123573 sci.electronics.design:725168 On Fri, 24 Nov 2006 14:05:17 -0600, John Fields wrote: > On Fri, 24 Nov 2006 17:28:40 GMT, "Homer J Simpson" >>"John Fields" <jfields@austininstruments.com> wrote in message >> >>>>You seem to have a fixation about where YOUR next banana will be inserted. >> >>> Not me.. >> >>And yet you constantly make comments about other people being gay, comments >>based solely on your own fixations. Based on experience? > > In a sense, in that I emailed one of your posts over to a gay friend > of mine for him to read and he said that you were definitely queer > but that he wouldn't touch you with a ten-foot pole. Boy, you sure do spend a lot of time focusing on the pretty boys, don't you? Hmmmmm..... Cheers! RichArticle: 112564
I agree with Jon. Most of the comments in this thread are related to simulation, but finally we design the circuits with HDL languages to synthesize them. Setting x to the default case also lets the synthesis tool produce faster/smaller circuits, because the synthesis tool has in that case the freedom to optimize the circuit according to internal optimization algorithms. It also can make the design more robust, because the verification engineer will try to remedy the case and thus design bugs can be localised better (probably at the expense of time to debug, which is worth having it). Utku. Jon Beniston schrieb: > Davy wrote: > > Hi all, > > > > I always found people like to add default branch like below: > > case(branch) > > ... ... > > [all the possible branch] > > ... ... > > default: signal = 8'bx; > > > > And my friend told me it's for simulation cause. When branch not hit > > all the possible case, the branch must have something like xxxx. So we > > set signal to xxxx to let xxxx pass go on and help us to find the bug. > > > > If I set default: signal = 0; the xxxx problem will be hidden and hard > > to find the bug. > > > > But as we know, there is no xxxx signal in real digital world. So is > > there any better method to solve the problem? > > What is the problem with this? It does not matter that this doesn't > correspond to a real world value. The synthesis tool will see that it > is a don't care, and hopefully should optimise the logic accordingly, > giving you the smallest / fastest circuit. > > Cheers, > JonArticle: 112565
"why and how the FPGA will affect this measurement" Why does FPGA add jitter to combinational paths? As someone else pointed out: rise times and thresholds. Not only those of IO pins but also those of every path taken by the relevant signals within the routing fabric and logic cells within the FPGA. Each of these nodes has both an input and output. Every input will have its own threshold voltage and every output will also have a slightly different slew rate. Both parameters will be affected to some extent to variations in operating parameters including internal power distribution noise, minute junction temperatures fluctuations, fabrication process variations, etc. From input to output, your signal goes through an IOB, at least one H-line and one V-line to reach the logic cell, then it goes through the cell's input S-box, LUT inputs, LUT outputs, the cell's output S-box, at least another pair of H-V routes and finally the output IOB. In-to-out delay may be over 500ps but as you said, this can be overcome by calibration. However, due to all the routing nodes your signal passes through within the FPGA, jitter around this (hypothetical) 500ps delay can easily exceed 100ps. Achieving 25ps jitter may be possible if you cherry-pick your IOBs, routing and logic cells through trial-and-error to find a path that meets your requirements and do some supercooling. However, electromigration as the de device ages may also ruin your initial efforts at some point in the future. IIRC, IOB bandwidth on V4 is 625MHz. Imagine how much jitter you would be getting right here by relying on edges that fall so far beyond the IOB's capabilities. FPGAs are not meant for ultra-high-speed asynchronous signal routing or measurement of said signals. Al wrote: > John_H wrote: >> It seems the lot here is convinced that you shouldn't use FPGAs to >> generate a signal to do precision time measurements. You should have >> expertise within your organization that can help underscore the issues >> you'e facing. If the number of responses on this newsgroup telling you >> not to go down the road you're travelling without reevaluating your >> path doesn't convince you that you should reevaluate your path, you >> need the face-to-face interaction that will help you understand that >> you cannot achieve your goals without rethinking your approach. >> > > I do see the warning and I do am worried, just because this part of the > design is already been designed by somebody else and I didn't want to > take over it again. > Tipically my approach is such that if someone did something he had his > motivations to do that, the same as all these replies, that's why I'm > trying to evaluate why and most important how much this will affect my > project. > That's why I'm reading carefully all these posts and try to evaluate > somebody else's experience, I cannot simply trust (at least it's out of > my attitudes). > Thanks for your explanation, by the way "why and how the FPGA will > affect this measurement" is still an open issue to me. > Thanks > > Al >Article: 112566
On Fri, 24 Nov 2006 22:56:27 GMT, Richard The Dreaded Libertarian <null@example.net> wrote: >On Fri, 24 Nov 2006 14:05:17 -0600, John Fields wrote: >> On Fri, 24 Nov 2006 17:28:40 GMT, "Homer J Simpson" >>>"John Fields" <jfields@austininstruments.com> wrote in message >>> >>>>>You seem to have a fixation about where YOUR next banana will be inserted. >>> >>>> Not me.. >>> >>>And yet you constantly make comments about other people being gay, comments >>>based solely on your own fixations. Based on experience? >> >> In a sense, in that I emailed one of your posts over to a gay friend >> of mine for him to read and he said that you were definitely queer >> but that he wouldn't touch you with a ten-foot pole. > >Boy, you sure do spend a lot of time focusing on the pretty boys, don't >you? --- You think Homer's pretty? Eeewwww!!! --- >Hmmmmm..... --- Indeed. -- JFArticle: 112567
"John Fields" <jfields@austininstruments.com> wrote in message news:8e0fm29edjrukt15o3kt2sk24h8gh7hmkm@4ax.com... > You think Homer's pretty? > > Eeewwww!!! Women do.Article: 112568
On Fri, 24 Nov 2006 21:47:21 GMT, "Homer J Simpson" <nobody@nowhere.com> wrote: > >"John Fields" <jfields@austininstruments.com> wrote in message >news:dujem21f677h2vec8hu7nuu3fodllja2ne@4ax.com... > >> In a sense, in that I emailed one of your posts over to a gay friend >> of mine for him to read and he said that you were definitely queer >> but that he wouldn't touch you with a ten-foot pole. > >No, he said YOU were gay and he wasn't interested. --- Homer, I'm embarrassed for you. You're nothing more than a parrot and I weep for the students who are forced to attend your classes. Keep it up and you'll probably find out what's in those baggies. -- JFArticle: 112569
of course I did all this but something must have gone wrong though. Anyway I got it now , found the xil... directories and deleted them. There are 3!! options now in XP to prevent files from beeing shown (american programming logic :x) But now let`s step away from this windows issue ... I again unpacked the rar to the root directory, double clicked the ise, but still have now hdls. the project only shows "spartan 3e" and "xa2c*.**". No "test" or anyting like that. Anybody has a 100% worling example? From null@example.net Fri Nov 24 17:46:23 2006 Path: newssvr21.news.prodigy.net!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!pd7cy5no!shaw.ca!nx02.iad01.newshosting.com!newshosting.com!130.81.64.211.MISMATCH!cycny01.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny04.POSTED!dd653b87!not-for-mail From: Richard The Dreaded Libertarian <null@example.net> Subject: Re: board - T562.jpg User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2006.11.25.01.46.43.983645@example.net> Newsgroups: alt.binaries.schematics.electronic,comp.arch.fpga,sci.electronics.design References: <vp29h.39$p9.4@edtnps82> <ooe9m2ld470u6rg7tqku3vfchh83960698@4ax.com> <GF79h.100$p9.93@edtnps82> <dlvam25q5c9n959lsspek87p0v8bkgie21@4ax.com> <kQk9h.176$p9.1@edtnps82> <4e1cm2ph7tkl0pm0ek7hin684pquochl58@4ax.com> <uVn9h.217$p9.135@edtnps82> <ph5cm2lv6pguo2rlnnqnc1q0pievcv5cgk@4ax.com> <HIp9h.232$p9.43@edtnps82> <9ijdm2t4l2ee5cik1vlhhotrh9m6v3l6aj@4ax.com> <cZF9h.1872$p9.802@edtnps82> <dujem21f677h2vec8hu7nuu3fodllja2ne@4ax.com> <pan.2006.11.24.22.56.50.591939@example.net> <8e0fm29edjrukt15o3kt2sk24h8gh7hmkm@4ax.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 29 Date: Sat, 25 Nov 2006 01:46:23 GMT NNTP-Posting-Host: 71.103.148.12 X-Complaints-To: abuse@verizon.net X-Trace: trndny04 1164419183 71.103.148.12 (Fri, 24 Nov 2006 20:46:23 EST) NNTP-Posting-Date: Fri, 24 Nov 2006 20:46:23 EST Xref: prodigy.net alt.binaries.schematics.electronic:127481 comp.arch.fpga:123580 sci.electronics.design:725250 On Fri, 24 Nov 2006 17:42:03 -0600, John Fields wrote: > On Fri, 24 Nov 2006 22:56:27 GMT, Richard The Dreaded Libertarian >>On Fri, 24 Nov 2006 14:05:17 -0600, John Fields wrote: >>> On Fri, 24 Nov 2006 17:28:40 GMT, "Homer J Simpson" >>>>"John Fields" <jfields@austininstruments.com> wrote in message >>>> >>>>>>You seem to have a fixation about where YOUR next banana will be inserted. >>>> >>>>> Not me.. >>>> >>>>And yet you constantly make comments about other people being gay, comments >>>>based solely on your own fixations. Based on experience? >>> >>> In a sense, in that I emailed one of your posts over to a gay friend >>> of mine for him to read and he said that you were definitely queer >>> but that he wouldn't touch you with a ten-foot pole. >> >>Boy, you sure do spend a lot of time focusing on the pretty boys, don't >>you? > > You think Homer's pretty? > I have no idea what he looks like - "pretty-boy" is the term for the kinds of people whose sex life you seem to be obsessed with. Thanks, RichArticle: 112570
spartanius@arcor.de wrote: > of course I did all this but something must have gone wrong though. > Anyway I got it now , found the xil... directories and deleted them. > There are 3!! options now in XP to prevent files from beeing shown > (american programming logic :x) But now let`s step away from this > windows issue ... > > I again unpacked the rar to the root directory, double clicked the ise, > but still have now hdls. > the project only shows "spartan 3e" and "xa2c*.**". No "test" or > anyting like that. > > Anybody has a 100% worling example? What good does it do you if we have working examples? Right out of the box, it worked. Right out of the box, I could modify the starter kit design and it worked. How can my having an example that works - the one that ships with the box - possibly help you in your situation? You have the same tools and same files at your disposal.Article: 112571
"John Fields" <jfields@austininstruments.com> wrote in message news:qj6fm2l042v4gmu7cd1nvcg96uc7ijg5j6@4ax.com... > Homer, I'm embarrassed for you. You embarass yourself - constantly. > You're nothing more than a parrot and I weep for the students who > are forced to attend your classes. No, it's YOUR students who are forced to attend. Mine are all paying volunteers. > Keep it up and you'll probably find out what's in those baggies. ??? Head injury recently?Article: 112572
John_H schrieb: What I basically wanted to learn from a working project, is the correct project tree including pinout/ucf, constraints and such things. It is easier to start from that point rather than doing everything from scratch. > Right out of the box, I could modify the starter kit design and it worked. You surely mean the s3eskstart? I wonder why there is no *.ise file included. (How did the creator handle the project?) --- Anyway, I do not want to start with THIS particular design, but have a starting point for every design, i will create with this board. Therefore, I need the correct project settings for this FPGA and a pin definition of 100% coverage for the particular wiring of this board, switching off inactive functions explicitely. Searching the docs of the starter kit, I found and example ucf. According to my understanding, it seems to cover all available pins and functions (?). What I now need , is a hdl-design acting as the toplevel. Can this be created automatically from out of the ucf?Article: 112573
spartanius@arcor.de wrote: > John_H schrieb: > > What I basically wanted to learn from a working project, is the correct > project tree including pinout/ucf, constraints and such things. It is > easier to start from that point rather than doing everything from > scratch. > >> Right out of the box, I could modify the starter kit design and it worked. > > You surely mean the s3eskstart? I wonder why there is no *.ise file > included. (How did the creator handle the project?) > > --- > > Anyway, I do not want to start with THIS particular design, but have a > starting point for every design, i will create with this board. > Therefore, I need the correct project settings for this FPGA and a pin > definition of 100% coverage for the particular wiring of this board, > switching off inactive functions explicitely. > > Searching the docs of the starter kit, I found and example ucf. > According to my understanding, it seems to cover all available pins and > functions (?). What I now need , is a hdl-design acting as the > toplevel. Can this be created automatically from out of the ucf? The documentation shows that the needed files are s3esk_startup.vhd control.vhd kcpsm3.vhd and s3esk_startup.ucf where you need to download the free PicoBlaze cores as well (kcpsm3.vhd). Create a new project. Specify VHDL flow. Choose the XC3S500E-4FG320. Add the VHDL files to the project. Add the .ucf to the project. And implement. The .ise file tends to be a very large binary file that doesn't zip well and you need to be at least familiar enough with the tools to take the first step of creating the project or the rest of the journey will not go very well. The reference design is found at http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm and includes the s3esk_startup_rev2.pdf file for quick instructions including where to find picoblaze. I don't have ISE installed on my home system at the moment. If you can't even get to where the project can synthesize, let us know. It should be quick.Article: 112574
Hi in quartus II .I want to see the entire delay between two nodes after post fitting.I am unable to find it.Can anyone help me how to do it.Can anyone give material on how to do place and routing on FPGA or atleast tips. Thanking you kumar
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