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Gabor wrote:
> PeteS wrote:
>> Martin Thompson wrote:
>>> burn.sir@gmail.com writes:
>>>
>>> {about Lattice}
>>>> They use Synplify (and Precision) for synthesis. Not as good as Quartus
>>>> or XST, but it does the job. Might need some tweaking however when
>>>> inferring memories.
>>>>
>>> Can you provide more details? My experience to date has been that
>>> Synplify is better than XST, especially on runtime, and almost all the
>>> time on size & speed.
>>>
>>> Cheers,
>>> Martin
>>>
>> Thanks for the answers, chaps.
>>
>> I can now be a little more confident of using the devices. I have the
>> time to do a migration (well, a clean new design as it happens) if I
>> start now, and most of that extra time should (hopefully) be merely tool
>> related.
>>
>> I'll talk to my friendly vendor about pricing etc., tomorrow.
>>
>> That doesn't mean I won't use the other brands; in this particular case
>> it may make more sense to use brand L.
>>
>> Cheers
>>
>> PeteS
>
> I've been using Xilinx parts for some time, and started using the ECP
> series from Lattice recently. So far there have been some bumps in
> the implementation software (crash during P&R, timing anomalies),
> but the latest tools version appears to be more solid. There are still
> issues with "TRACE" (timing analysis) and related clocks. For instance
> when I have a 200 MHz clock at 0 phase and another at 270 degrees,
> I would expect a signal traveling from the 0 phase domain to the
> 270 degree domain to have 3/4 clock period or 3.75 nS from
> clock edge to clock edge (less uncertainties, etc.). TRACE seems
> to think the signal should be allowed 1 3/4 periods or 8.75nS.
> Additionally if I place a "MULTICYCLE" constraint from the 0
> phase clock to the 270 degrees phase clock, it is ignored and
> the 8.75nS constraint is still used. In my case the 270 degree
> clock is for output registers only, so I don't need a real
> PERIOD constraint on it. Thus I managed to trick the TRACE
> tool into giving me the 3.75nS clock to clock path by setting
> the PERIOD to 2.143nS on the 270 degree clock. Strangely
> the tools seem happy with this even though it should know that
> the two clocks should be at the same frequency.
>
> Also I've noticed the documentation is still a bit weak, but getting
> better. It's currently a mix of HTML and .pdf files. Information on
> library components is spread among a number of technical notes,
> although a complete listing (without full details) is available for
> each part series.
>
> If you've worked with Xilinx you'll recognize the tool flow because
> both tools were developed at NeoCAD. Lattice's GUI has a lot
> of similarity to ISE, with a process flow window. It took me a
> while to find out that not all settings in the flow can be reached
> by right clicking an object and selecting properties. TRACE
> parameters are only available through the menu bar.
>
> For programming, ispVM seems simpler to use than iMPACT. Once
> you get the hang of it you'll like the features like being able to have
> more than one setup open at a time.
>
> I can't really comment on Symplify vs. XST, because I'm only
> working on new designs with Lattice, so I didn't really compare
> apples to apples. My gut feeling is that it's at least as good
> as the recent release of XST, which is already much improved
> over the version 6 XST.
>
> If you don't already have a non-branded ModelSim seat, the
> base tools (not free web version, but still inexpensive) come
> with a Lattice-branded ModelSim license that doesn't have
> the annoying slow-down you get with the X-brand license.
> I'm assuming it nails you by stopping to work at some
> design size, but I haven't run into that yet.
>
> Finally I think you'll find that Lattice is very aggressive with
> pricing. Like I said we've been using Xilinx for some time
> now, and we don't pay the web price for their parts. Still
> for the same functionality it seems Lattice can offer significant
> savings over Xilinx.
>
Hi Gabor
That's _very_ useful feedback.
Thanks a lot!
Cheers
PeteS
Article: 112901
fl wrote:
> Because the
> fmax I get is lower (only 59.52 MHz from timing analyzer) than that in
> the book, I want to know the difference.
I don't have the book, but what do you get
if you do it like this?
http://home.comcast.net/~mike_treseler/add16.vhd
-- Mike Treseler
Article: 112902jez-smith@hotmail.co.uk schrieb: > Andrew Holme schrieb: > > > Target = XC3S400 Spartan 3 > > Tool = ISE 8.2i > > > > If I understand correctly, the DCM does not use a PLL to multiply-up the > > input frequency; it's a DLL and it generates all required frequencies/phases > > by selecting outputs from a tapped delay line. I heard these taps are only > > tens of picoseconds apart. Is this so? Why then is the peak-to-peak > > jitter, as calculated by the DCM wizard, so large e.g. hundreds of ps? > > > > For Spartan 3 designs, the tools do not automatically take DCM jitter into > > account. To get it included, I've manually added INPUT_JITTER 0.82 to the > > end of my external clock constraint: > > > > TIMESPEC "TS_EXT_CLK" = PERIOD "EXT_CLK" 20 ns HIGH 50 % INPUT_JITTER 0.82; > > > > Half of this figure then appears as "clock uncertainty" on the timing > > analysis report, and PAR works that much harder to get closure. I don't > > like including DCM jitter this way. The input clock is clean. Is there a > > neater way to specify it on the DCM outputs where it belongs? > > > > TIA > > Andrew. > > > If its any help you can look at the source code for the unisim or > simprim simulation model for the dcm in those respective library > sources,I remember looking at them some time ago so it may help to get > a better understanding. Sorry to have to add to my last post but yes the clock manager is based on a delay locked loop rather than a phase locked loop as the phase noise is lower with a DLL than a PLL.Article: 112903
Andrew, Yes, the taps are only 10 ps apart, but the control required to generate any M/D of the input clock is unable to be perfect for the DCM DFS output. I refer to the algorithm as a "tap dance." One creates a tapped ring oscillator out of the tapped delay line. If the output frequency is greater than the M/D times the input frequency, the period is made longer by changing taps. In the same way if the frequency is lower than the optimal value, the tap is moved to a shorter point. In order to know that the frequency is high or low, one requires a frequency detector, which means you have to integrate time (count, and wait). Once you have your answer, it is too late to do anything that will correct right away, and you can only nudge towards the proper rate. The DCM DFS uses a fairly sophisticated prediction method to drop/add tap changes as appropriate (reference the patents if interested), but yet is still not able to get the tap precision as the dominant jitter contributor. Rather, the DCM output jitter on the synthesized frequency output is mostly from not knowing when to zig, or zag, combined with jitter from the clock in, and not being perfectly accurate in knowing if the frequency is larger, or smaller (you sometimes make a mistake, unavoidably, because you can't wait too long! but you must wait to know anything at all). The DCM DLL outputs do have a much more well behaved and bounded jitter output, which is precisely 5 steps (at most) in jitter plus your input clock jitter, as you are either one high, or one low, or you are two high (because your phase detector guessed wrong), or two low (again because a phase detector in the presence of jitter is also an imperfect arbiter). AustinArticle: 112904
Hi, does anybody know how to switch of the LVDS output pins of a Cyclone II? I use the "alt_lvds" megafunction but there are no inputs to this megafuction to enable or disable the LVDS output pins. I thought about writing my own serializer as a workaround but I have no idea how this is done. But it should be possible by using the double data rate IOs and some shift registers. Thanks. -- --------------------------------- --- -- - Posted with NewsLeecher v3.7 Final Web @ http://www.newsleecher.com/?usenet ------------------- ----- ---- -- -Article: 112905
Hi, say would I use the SerialLite II megafunction to drive my data out of the FPGA to my fiber-optic transceiver? I'm not doing SONET or ATM or any particular protocol. The fiber-optic transceiver I plan to use is PECL or CML. joe Ben Twijnstra wrote: > Hi Joe, > > > Hello, I'm looking to do a design involving data rates near 4Gbps and > > was looking at using Altera's Stratix II GX transceivers to drive the > > data to a 4Gbps single-mode fiber-optic transceiver. I'm interested in > > how well the Stratix can perform this task, if anyone has some > > experience using the transceivers could you please let me know how well > > it worked for you? I've read the Altera's web site on the Stratix II GX > > and it sounds very promising, I just want to make sure that is does > > what it says it can. > > I've been toying around with Altera's own Signal Integrity board, and 6GBps > over 40" of trace plus 2ft of copper interconnect through SMAs works just > fine. 4GBPS over optic should be relatively easy. > > Feed the GX 100MHz of clock, put the PLLs into 40x, set the ALTGXB > transceiver interface to double-width mode (200MHz is workable in the core, > 400MHz is really, really stressing things), and as long as you properly do > your power decoupling and PCB layout you should have a working design. You > may need to tweak the pre-emphasis and/or equalization settings a bit to > get the best results, but so far the transceivers seem to be rock-solid. > > Best regards, > > > Ben > > > Best to contact your local (disti) FAE to provide you with the reference > schematic and board layout files of the SI board for reference.Article: 112906
Thank you, Mike. You are so kind. I get the same fmax, i.e. 59.52 MHz (period=3D16.8 ns). fmax is the same even though I constraint fmax to 75 MHz in the dialog box Clock Settings: Default required fmax: 75 MHz. The slack is -3.467 ns. The device is FLEX10K: EPF10K20RC240-4. Because the result of fmax is the same, there may be something wrong in the utilization of Quartus II 6.0 webpack, Windows XP. Why? Thank you Mike Treseler a =E9crit : > fl wrote: > > > Because the > > fmax I get is lower (only 59.52 MHz from timing analyzer) than that in > > the book, I want to know the difference. > > I don't have the book, but what do you get > if you do it like this? > > http://home.comcast.net/~mike_treseler/add16.vhd >=20 >=20 > -- Mike TreselerArticle: 112907
Hi Chris, >> That's interesting - what memory configuration? We have a single >> MT47H32M16CC-37E and just cannot get any sense out of it. >> >> Addressing looks all wrong - it reads back the same data value at 4 >> consecutive >> dword addresses (offset 0x00 -> 0x0c) >> >> Writing is unreliable, if you write 0xffffffff it just randomly >> twiddles a few >> of the top 16 bits, but not in any discernable pattern. >> >> I've tried more combinations that I care to admit - differential DQS >> on vs off, >> timing params exact according to Micron datasheet vs more >> conservative, you name >> it. Triple-checked UCF pin assignments, blah blah blah. > > It sounds like your read data isn't getting aligned properly. You > should try tweaking the parameters C_CTRL_Q10_DELAY and > C_CTRL_DP_RDFIFO_WHICHPORT_DELAY. If your running DDR2 at 200MHz, you > probably want to decrement those by 1. The parameters can be found in > the mpmc2_ctrl_path_params.v file in the verilog directory. HTH. Thanks for the reply -however I am actually using the EDK's mch_opb_ddr2 controller, not the MPMC2. I haven't gone source diving in the controller's VHDL yet, will see how I go with a webcase first. Thanks again, JohnArticle: 112908
Ray Andraka wrote: > Looks like Xilinx has pulled the old XCell journals off the website. > Someone was asking about my article on downconverters in issue #38, and > I sent them there since I do not have an electronic copy of the article. > Well, it is gone. Anybody out there have a pdf of that article? > > Xilinx, why are the older Xcell journals gone? Surely the space they > occupy isn't ridiculously large, and even though they refer to sunset > devices, many of the articles are still applicable to the current devices. Thanks all. I'm surprised Xilinx didn't chime in though.Article: 112909
fl wrote:
> Thank you, Mike. You are so kind. I get the same fmax, i.e. 59.52 MHz
> (period=16.8 ns). fmax is the same even though I constraint fmax to 75
> MHz in the dialog box Clock Settings: Default required fmax: 75 MHz.
> The slack is -3.467 ns. The device is FLEX10K: EPF10K20RC240-4.
> Because the result of fmax is the same, there may be something wrong in
> the utilization of Quartus II 6.0 webpack, Windows XP.
Or maybe the author was using a faster speed grade
or a different device.
With an epm240f100c4 I got 197.51 MHz ( period = 5.063 ns )
In any case, I think he was doing it the hard way.
Good luck.
-- Mike Treseler
Article: 112910Hi, If you can live with latency, here is a noteworthy alternative: ring-bus. m1 -> m2 -> m3 -> m1 When pipelined, a ring-bus allows higher operating frequencies and lower routing utilization. However, ring-bus interfaces do consume a few FFs and LUT and how much this may be depends on how simple/complex your implementation is. In one of my own designs, I have used a pipelined 8bits ring-bus. Each hop consumed about 70 slices (32bits tap IO port) and the whole ring should have been able to run run at 170MHz on a V2P30-7 according to STA. If you put together a similar bus with 16bits IO ports, you might be able to do something similar under 50 slices. Jürgen Böhm wrote: > hi, > > currently I am working on a small hobby project with the Spartan 3 > Starter Kit board from Xilinx. I use ISE WebPack 8.1i and Verilog as a > language. > > Now some questions have come up during this:Article: 112911
Peter chiming in. I was on vacation until yesterday, and I was determined to do something about the sad state of the older XCell issues. (I started that magazine in 1989, much thinner, less glossy, and more technical.) I will still try to make the access to old issues more obvious and user-friendly. Regarding another promise: Watch DigiKey! They promise to have an extensive array of modern Xilinx chips in their next catalog. With their usual next-day delivery... Peter Alfke, Xilinx Applications, back in town. On Nov 30, 4:40 pm, Ray Andraka <r...@andraka.com> wrote: > Ray Andraka wrote: > > Looks like Xilinx has pulled the old XCell journals off the website. > > Someone was asking about my article on downconverters in issue #38, and > > I sent them there since I do not have an electronic copy of the article. > > Well, it is gone. Anybody out there have a pdf of that article? > > > Xilinx, why are the older Xcell journals gone? Surely the space they > > occupy isn't ridiculously large, and even though they refer to sunset > > devices, many of the articles are still applicable to the current devices.Thanks all. I'm surprised Xilinx didn't chime in though.Article: 112912
Hi, Our hardware engineer got *.vcd file from Xilinx ChipScope, then I swithced the *.vcd file to *.wlf file in ModelSim using vcd2wlf command. After getting *.wlf file, I combined a lot of signals, added color, changed their display format and so on. After that I would like to save the file for later use. But I couldn't find any appropriate tools in ModelSim to save the *.wlf file. The only file that can be exported from ModelSim is *.bmp. Do you know any better method? Thank you. WengArticle: 112913
Setting an output pin to LVDS is not part of the megafunction. You can use the assignment editor to accomplish what you want. Writing your own serailizer usually takes a fairly good understanding of the hardware, setup/hold times, and jitter. "tentacle" <onlyspam@online.ms> wrote in message news:5a2cd$456f558e$54965988$20070@nf4.news-service.com... > Hi, > > does anybody know how to switch of the LVDS output pins of a Cyclone > II? > > I use the "alt_lvds" megafunction but there are no inputs to this > megafuction to enable or disable the LVDS output pins. > > I thought about writing my own serializer as a workaround but I have > no idea how this is done. But it should be possible by using the > double data rate IOs and some shift registers. > > Thanks. > > > -- > --------------------------------- --- -- - > Posted with NewsLeecher v3.7 Final > Web @ http://www.newsleecher.com/?usenet > ------------------- ----- ---- -- - >Article: 112914
I know I can do so, but it took weeks to be delivered. Hence I figured this could be an alternative. I will properly cite every thesis that I'll use. My email is ameliaw.azman@gmail.com. Thank you. wallge wrote: > whats your project? > you can search through lots of online theses > through your university library system. > I can send you mine if you like, > whats your email? > I can answer some questions too... > Just cite my work if you use it. > > my thesis is titled > EMBEDDED PATTERN RECOGNITION WITH > FIELD PROGRAMMABLE GATE ARRAYS > > thanks, > > --geoff > wallge@gmail.com >Article: 112915
Andrew Holme wrote: > Target = XC3S400 Spartan 3 > Tool = ISE 8.2i > > If I understand correctly, the DCM does not use a PLL to multiply-up the > input frequency; it's a DLL and it generates all required frequencies/phases > by selecting outputs from a tapped delay line. I heard these taps are only > tens of picoseconds apart. Is this so? Why then is the peak-to-peak > jitter, as calculated by the DCM wizard, so large e.g. hundreds of ps? > > For Spartan 3 designs, the tools do not automatically take DCM jitter into > account. To get it included, I've manually added INPUT_JITTER 0.82 to the > end of my external clock constraint: > > TIMESPEC "TS_EXT_CLK" = PERIOD "EXT_CLK" 20 ns HIGH 50 % INPUT_JITTER 0.82; > > Half of this figure then appears as "clock uncertainty" on the timing > analysis report, and PAR works that much harder to get closure. I don't > like including DCM jitter this way. The input clock is clean. Is there a > neater way to specify it on the DCM outputs where it belongs? > > TIA > Andrew. No answer? If you have access to the hotline, you may actually get a decent response. Constraints are something those guys may be well trained on (versus the complex design de jour from a random customer). There are even some decent documents on constraints that might otherwise be hard to find. Clocking constraints - including the override of internally implied constraints - should be covered. Somewhere. Also, if you have a relationship with your FAE, you might get good help there as well. I had issues trying to trace constraints through a BUFGMUX and got some decent help pretty quickly. Constraints are tricky, particularly when you want to change the implied values.Article: 112916
John Williams schrieb: > Hi Chris, > [] > Thanks for the reply -however I am actually using the EDK's mch_opb_ddr2 > controller, not the MPMC2. I haven't gone source diving in the controller's > VHDL yet, will see how I go with a webcase first. > > Thanks again, > > John John, did you try reversing the ddr2 address bus bit endianess? eg A12>A0 .. A0>A12 if the sdram address bus endianswapped then same data appears on multiply location, exactly as in your case AnttiArticle: 112917
I am interested in this... Please send me more information I will definetly able to do the FPGA program (xilinx) rgds bijoyArticle: 112918
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1164938845.207923.209380@79g2000cws.googlegroups.com... > Hi, > Our hardware engineer got *.vcd file from Xilinx ChipScope, then I > swithced the *.vcd file to *.wlf file in ModelSim using vcd2wlf > command. After getting *.wlf file, I combined a lot of signals, added > color, changed their display format and so on. After that I would like > to save the file for later use. But I couldn't find any appropriate > tools in ModelSim to save the *.wlf file. > > The only file that can be exported from ModelSim is *.bmp. > > Do you know any better method? > > Thank you. > > Weng > Using 6.2d, log signals, run your simulation, select the workspace window go to file and hit the save option.... alternative have a look in the user manual :-) Hans www.ht-lab.comArticle: 112919
austin wrote: > I always enjoy reading patents that claim to eliminate metastability. > Seems that the patent office has never figured this one out: they did > make it a law that perpetual motion machines are not patentable, but > there is no such restriction for metastability "eliminators" (all of > which don't work!). I first heard about metastability in a discussion about the PDP-10 (KA10), which apparently had no metastability problem. The solution to metastability is asynchronous logic (also called self-timed logic). That doesn't seem to have convinced very many people, though. -- glenArticle: 112920
Well, you have to use some more effort. Use Chipscope (or a logic analyser) for hardware debug and watch IO signals to/from SDR. If your simulation works for only half of memory than you are missing one address line. Cheers, guru cippalippa wrote: > Hello to all, > > I'm new in this forum; In a Project I need to write and read from a > Micron DDR memory (I have a Spartan 3E starter kit wit a Micron > 46V32M16); I tried to use the Opencores DDR Sdram controller and the > simulation with my code was fine (the ddr controller is for a 46V16M16 > but I see that the only difference is the half memory space). > When I try to Implement the code in the board the controller don't work > properly; I write some data in different address but I read alwais the > last data writted. > I use the Xilinx ISE Webpack 8.2.03i. > May sameone help me please? > Thanks in advance for all. > > DanieleArticle: 112921
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:NO-dnQz0batcbvLYnZ2dnUVZ_rOdnZ2d@comcast.com... > austin wrote: > >> I always enjoy reading patents that claim to eliminate metastability. > >> Seems that the patent office has never figured this one out: they did >> make it a law that perpetual motion machines are not patentable, but >> there is no such restriction for metastability "eliminators" (all of >> which don't work!). > > I first heard about metastability in a discussion about the PDP-10 (KA10), > which apparently had no metastability problem. The solution > to metastability is asynchronous logic (also called self-timed logic). > > That doesn't seem to have convinced very many people, though. > > -- glen > Hi Glen, Are you joking around? If not, I'll bite. I challenge you to design a metastability free traffic light controller from 'metastability solved' asynchronous logic. The lights are at a crossroads out in the sticks with low traffic volume. They are nomally both set RED until a car comes along. The lights then go GREEN in the direction from which a vehicle comes from. Make sure your logic doesn't go metastable when two cars arrive simultaneously from two orthogonal directions. Your controller must work no matter with whatever time difference the two cars arrive, and must work on EVERY occasion for EVERY car arrival timing scenario. Even one mistake in the lifetime of the universe is FAR, FAR too often for this junction! Good luck, Syms. p.s. I'm really in two minds about posting this, these threads grow like wildfire, and I don't want to be the arsonist. Needless to say, asynchronous design is NOT the 'solution' to metastability. Metastability always has a non-zero probability.Article: 112922
Hans schrieb:
> "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message
> news:1164938845.207923.209380@79g2000cws.googlegroups.com...
>> Hi,
>> Our hardware engineer got *.vcd file from Xilinx ChipScope, then I
>> swithced the *.vcd file to *.wlf file in ModelSim using vcd2wlf
>> command. After getting *.wlf file, I combined a lot of signals, added
>> color, changed their display format and so on. After that I would like
>> to save the file for later use. But I couldn't find any appropriate
>> tools in ModelSim to save the *.wlf file.
>>
>> The only file that can be exported from ModelSim is *.bmp.
>>
>> Do you know any better method?
>>
>> Thank you.
>>
>> Weng
>>
>
> Using 6.2d, log signals, run your simulation, select the workspace window go
> to file and hit the save option.... alternative have a look in the user
> manual :-)
>
> Hans
> www.ht-lab.com
>
>
Hi Hansn and Weng,
unless the 6.2d version is different in that point, all versions of
Modelsim I know just save the format information in a do-file when using
the file->save menu entry.
Of course it can be helpful, when it's ok to live with 2 files.
The original vcd-file, and the format do-file (manually extended with
the vcd2wlf comand at the top of the file.). My understanding of Wengs
question is, that he wants to save everything in one file, and expects
the wlf-file to do the trick.
For saving the wlf-file there used to be a "Save Dataset" command in the
File menu. I didn't find it in 6.0d anymore. But even then I think you
need 2 files, because the wlf-file only contains the bare data of the
simulated signals and knows nothing about signal combinations, colors,
cursors etc.. But I may be wrong...
Have a nice Simulation
Eilert
Article: 112923Hi, I still cannot get better performance, even for your code. The following is part of the info in listpath. Why there is so much IC and CELL delay? Could you guess that? I doubt there are some settings I must set besides fmax setting. Thank you very much. Info: Clock "clk" has Internal fmax of 59.52 MHz between source register "\only:x_v[0]" and destination register "\only:sum_v[14]" (period=3D 16.8 ns) Info: + Longest register to register delay is 13.200 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) =3D 0.000 ns; Loc. =3D LC6_F16; Fanout =3D 2; REG Node =3D '\only:x_v[0]' Info: 2: + IC(2.200 ns) + CELL(1.200 ns) =3D 3.400 ns; Loc. =3D LC1_F13; Fanout =3D 2; COMB Node =3D 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]' Info: 3: + IC(0.000 ns) + CELL(0.300 ns) =3D 3.700 ns; Loc. =3D LC2_F13; Fanout =3D 2; COMB Node =3D 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]' Mike Treseler a =E9crit : > fl wrote: > > Thank you, Mike. You are so kind. I get the same fmax, i.e. 59.52 MHz > > (period=3D16.8 ns). fmax is the same even though I constraint fmax to 75 > > MHz in the dialog box Clock Settings: Default required fmax: 75 MHz. > > The slack is -3.467 ns. The device is FLEX10K: EPF10K20RC240-4. > > Because the result of fmax is the same, there may be something wrong in > > the utilization of Quartus II 6.0 webpack, Windows XP. > > > Or maybe the author was using a faster speed grade > or a different device. > With an epm240f100c4 I got 197.51 MHz ( period =3D 5.063 ns ) > > In any case, I think he was doing it the hard way. > Good luck. >=20 > -- Mike TreselerArticle: 112924
Does anyone know what is the difference between connecting a peripheral to the PowerPC (Virtex-II Pro) by using an OPB (On-chip Peripheral Bus) or a PLB bus (Peripheral Local Bus)? Most of the peripherals in the EDK support both ways for connecting to the PowerPC.
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