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Robin Bruce schrieb: > I didn't mean to come crashing in so hard on your statement, so hope I > didn't offend. No, you did not - in no way. > I tend to prefer the term "blank canvas" for describing FPGAs to the > uninitiated myself. It makes the whole process sound much more creative > :-) So you are similar to these medieval-age monks, that paint pictures over pictures. ;-) RalfArticle: 112951
I do have a interesting project. I am planing to wire my house with duplex multimode fiber. I would like to send from a central location of the house multiple broadcast video and audio signals. The video should be either 10 or 12bit digital stream. With the help of a FPGA we should multiplex I would say up to 5 digital parallel video streams(each around 200Mbs, with 16M clk and 3Mbs for four audio channels). The mux out should be 16 or 20bit data stream.Article: 112952
lubot77 wrote: > I do have a interesting project. I am planing to wire my house with duplex > multimode fiber. I would like to send from a central location of the house > multiple broadcast video and audio signals. The video should be either 10 or > 12bit digital stream. > With the help of a FPGA we should multiplex I would say up to 5 digital > parallel video streams(each around 200Mbs, with 16M clk and 3Mbs for four > audio channels). The mux out should be 16 or 20bit data stream. > > Are all the streams synchronous to each other? If not you'll have to synchronise the streams with an overhead channel (probably). Cheers PeteSArticle: 112953
Yes, I use the simulation model that I found with opencores IP; and with this model the controller work perfectly. When I implement the core and I downloaded the bitstream in the FPGA the controller don't work. The memory that I have isn't the same of the simulation model but the version with duble memory; this memory however have identical timing so if I use half memory I think that the memory must work. When I try to write and read from this memory I only read always the last data writted. Vangelis ha scritto: > Did you use a simulation model for you memory module?Article: 112954
Does anyone know if the LATTICE ECP2M FPGA's have on die Digitally Controlled Impedance (DCI) matching for input LVDS? I am designing a x4 lane PCIe digitiser card with the National 500MSPS ADC and the ECP2M FPGA. The ADC output 32 pair LVDS and I have read the FPGA datasheet but there is no mention of DCI?? Thanks slkjasArticle: 112955
They will be synchronous to each other. I am planning to use four either 10 or 12 bit video ADC's, and sixteen audio ADC's . The 20 bit data out of the FPGA will feed the Agilent chip set that will drive the laser. On the receiver side the signal will be demuxed from the FPGA and will feed Video and Audio DAC's. I do not have a big experience with programmable devices, so I was wondering if there are any standard engineering techniques and tricks to do that. Thanks "PeteS" <peter.smith8380@ntlworld.com> wrote in message news:Ucgch.3131$3P4.55@newsfe7-gui.ntli.net... > lubot77 wrote: >> I do have a interesting project. I am planing to wire my house with >> duplex multimode fiber. I would like to send from a central location of >> the house multiple broadcast video and audio signals. The video should be >> either 10 or 12bit digital stream. >> With the help of a FPGA we should multiplex I would say up to 5 digital >> parallel video streams(each around 200Mbs, with 16M clk and 3Mbs for four >> audio channels). The mux out should be 16 or 20bit data stream. > > Are all the streams synchronous to each other? If not you'll have to > synchronise the streams with an overhead channel (probably). > > Cheers > > PeteSArticle: 112956
cippalippa wrote: > Hello to all, > > I'm new in this forum; In a Project I need to write and read from a > Micron DDR memory (I have a Spartan 3E starter kit wit a Micron > 46V32M16); I tried to use the Opencores DDR Sdram controller and the > simulation with my code was fine (the ddr controller is for a 46V16M16 > but I see that the only difference is the half memory space). > When I try to Implement the code in the board the controller don't work > properly; I write some data in different address but I read alwais the > last data writted. > I use the Xilinx ISE Webpack 8.2.03i. > May sameone help me please? > Thanks in advance for all. > > Daniele As far as I know, the Xilinx Webpack can generate Memory Controller according to the given parameters like bus width etc. So there is no need to write your own controller anymore, except you want to optimize something specific to your application. StevenArticle: 112957
The details can be found in the Quartus Handbook at http://www.altera.com/literature/hb/qts/qts_qii53001.pdf Hope this helps, Subroto Datta Altera Corp. "ram" <vsrpkumar@rediffmail.com> wrote in message news:1165028275.314021.115460@j44g2000cwa.googlegroups.com... > Hi > I am using modelsim for simulation and quartus 6.0 for remaining.I have > generated custom netlist ffrom quartus.I want to simulate in modelsim > .How to link library of cyclone device.How to do that.Can anybody help > me.Thanking you >Article: 112958
cippalippa wrote: > When I try to Implement the code in the board the controller don't work > properly; I write some data in different address but I read alwais the > last data writted. Do you use a clock of 133 MHz? Xilinx provides a reference design, which works with an external 133 MHz clock: http://www.xilinx.com/support/software/memory/protected/index.htm If it doesn't produce too much jitter, maybe it works with a DCM generated 133 MHz clock from the on-board 50 MHz clock, too? -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 112959
Hey ppl
Is there a way we can have a control over the input order of the
LUTs...I see that eventhough we specify the inputs in the VHDL code
(I0, I1, I2 and I3), during the mapping process, the tool automatically
makes modifications and the routed design has a different order than
the one specified in the VHDL code....
Thanks in Advance
Mr.B
Article: 112960I'm trying to use a FPGA to control a flat panel display that has LVDS inputs. Displays try to draw current from active LVDS lines if the power supply of the panel is switched off. That is very harmful for the TFT and sooner or later it gets destroyed. That is why I have to tri-state the LVDS outputs. Every LVDS driver IC on the market has an "output enable" signal. So why shouldn't this be possible with an FPGA? -- --------------------------------- --- -- - Posted with NewsLeecher v3.7 Final Web @ http://www.newsleecher.com/?usenet ------------------- ----- ---- -- -Article: 112961
Sorry, that should have been ftp://ftp.xilinx.com/pub/utilities/fpga/install_drivers.tar.gz Incidentally, that tarball also has 32- & 64-bit cable drivers.Article: 112962
Why do you care? The software tries to get the best routing, and may modify the LUT inputs (and the LUT content)accordingly. The LUT inputs can have individually different delays, and the software knows that also. Peter Alfke, Xilinx Applications On Dec 2, 12:06 pm, bharadwaj...@gmail.com wrote: > Hey ppl > > Is there a way we can have a control over the input order of the > LUTs...I see that eventhough we specify the inputs in the VHDL code > (I0, I1, I2 and I3), during the mapping process, the tool automatically > makes modifications and the routed design has a different order than > the one specified in the VHDL code.... > > Thanks in Advance > > Mr.BArticle: 112963
tentacle (onlyspam@online.ms) wrote: > I'm trying to use a FPGA to control a flat panel display that has LVDS > inputs. Displays try to draw current from active LVDS lines if the power > supply of the panel is switched off. > > That is very harmful for the TFT and sooner or later it gets destroyed. > > That is why I have to tri-state the LVDS outputs. Didn't know that > Every LVDS driver IC on the market has an "output enable" signal. So why > shouldn't this be possible with an FPGA? Well, I know that a lot of Philips TFT panels are driven by a Cyclone II, but then again, these Cyclones get their current from the same supply as the panel so the TFT can try to draw current until it hurts, but the Cyclone will have nothing to give ;-) Alternatively you could use SSTL2, which basically has the same electrical characteristics but is available as a bidirectional IO buffer. Setting OE to 0 in this mode would effectively tristate the buffer. Drive strength is limited to 15mA though. Best regards, BenArticle: 112964
bharadwaj.sr@gmail.com wrote: > Hey ppl > > Is there a way we can have a control over the input order of the > LUTs...I see that eventhough we specify the inputs in the VHDL code > (I0, I1, I2 and I3), during the mapping process, the tool automatically > makes modifications and the routed design has a different order than > the one specified in the VHDL code.... > > > Thanks in Advance > > Mr.B > Yes, there is with a little bit of hand-waving. The PAR software does not lock inputs for a standard LUT, however it does lock inputs for an SRL16E, because there the order of the inputs are important. The SRL16E behaves like a LUT4 as long as the write enable input is held low. The trick, therefore to locking the LUT pin assignments is to replace the LUTs with SRL16E's with the enable control grounded. I haven't tried this on recent versions of ISE, but I know it worked in versions up through 6.3.Article: 112965
The "LOCK_PINS" constraint should take care of this. Check it out in the constraint user guide. Depending on ISE version, you may need to set it to different values. HTH, Jim http://home.comcast.net/~jimwu88/tools/ bharadwaj.sr@gmail.com wrote: > Hey ppl > > Is there a way we can have a control over the input order of the > LUTs...I see that eventhough we specify the inputs in the VHDL code > (I0, I1, I2 and I3), during the mapping process, the tool automatically > makes modifications and the routed design has a different order than > the one specified in the VHDL code.... > > > Thanks in Advance > > Mr.BArticle: 112966
When I was trying to lock down only 2 pins out of 4, I had no problems for a while, then I couldn't get them to work; it might have been a software change. For this delay-matching circuit (to a first order approximation) I had to use the LOCK_PINS:ALL constraint to map I0-I3 to A1-A4... all 4 pins even though only 2 were critical. There are very few applications that benefit from locking down the pins, but they do exist. Jim Wu wrote: > The "LOCK_PINS" constraint should take care of this. Check it out in > the constraint user guide. Depending on ISE version, you may need to > set it to different values. > > HTH, > Jim > http://home.comcast.net/~jimwu88/tools/ > > bharadwaj.sr@gmail.com wrote: >> Hey ppl >> >> Is there a way we can have a control over the input order of the >> LUTs...I see that eventhough we specify the inputs in the VHDL code >> (I0, I1, I2 and I3), during the mapping process, the tool automatically >> makes modifications and the routed design has a different order than >> the one specified in the VHDL code.... >> >> >> Thanks in Advance >> >> Mr.BArticle: 112967
Well, depending on how you define "best routing", swapping LUT pins may or may not be a godd thing. Cheers, Jim http://home.comcast.net/~jimwu88/tools/ Peter Alfke wrote: > Why do you care? > The software tries to get the best routing, and may modify the LUT > inputs (and the LUT content)accordingly. > The LUT inputs can have individually different delays, and the software > knows that also. > Peter Alfke, Xilinx Applications > > On Dec 2, 12:06 pm, bharadwaj...@gmail.com wrote: > > Hey ppl > > > > Is there a way we can have a control over the input order of the > > LUTs...I see that eventhough we specify the inputs in the VHDL code > > (I0, I1, I2 and I3), during the mapping process, the tool automatically > > makes modifications and the routed design has a different order than > > the one specified in the VHDL code.... > > > > Thanks in Advance > > > > Mr.BArticle: 112968
Kev, Please contact me through the FMF website. We have received no bug reports on this model. Although the VITAL2000 issue is common, it is limited to modelsim. I will help you workout whatever other issues you have. If there is an actual bug, we are under contract from Spansion to fix it. Rick Munden Niv wrote: > wallge wrote: >> I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM >> that I want to be able to control via an FPGA on the same PCB. >> I am having trouble with the verilog model. I have used both a samsung >> and a micron model for the part (two compatible parts). Unfortunately >> these models are not available in VHDL, and my verilog is pretty weak. >> >> I wondered if any one had some experience with memory models, both in >> terms of using them to design memory controllers and debugging them >> when they spit out spurious timing violations. >> These verilog models in particular seem to send out all manner of >> timing violations or functional problems that don't seem to be in line >> at all with what the data sheet says regarding the timing and command >> and control procedures (for doing a full page read or write, for >> instance). >> >> Has any one else had trouble with bad/buggy models? What is the best >> way to solve this problem? >> What is the best way to go about designing a memory controller (I have >> seen an example on Altera's website in VHDL (but it sucks), as well as >> some others in open cores and one written for a homebrew graphics >> accelerator card (manticore). I find the documentation and/or >> functionality lacking in most of the aforementioned existing reference >> designs. >> >> thanks > > Hi, I'm trying to use an AMD (Spansion) FLASH model, and it's just one > BIG headache. > Despite following all their advice and recompiling lots of libraries > with vital2000, the model > still falls over immediately in modelsim. > > It's really poor putting out models that just don't work, IMO. > > Kev P. >Article: 112969
What partnumber do you need to simulate? wallge wrote: > I am trying to write an SDRAM controller in VHDL for a mobile SDR SDRAM > that I want to be able to control via an FPGA on the same PCB. > I am having trouble with the verilog model. I have used both a samsung > and a micron model for the part (two compatible parts). Unfortunately > these models are not available in VHDL, and my verilog is pretty weak. > > I wondered if any one had some experience with memory models, both in > terms of using them to design memory controllers and debugging them > when they spit out spurious timing violations. > These verilog models in particular seem to send out all manner of > timing violations or functional problems that don't seem to be in line > at all with what the data sheet says regarding the timing and command > and control procedures (for doing a full page read or write, for > instance). > > Has any one else had trouble with bad/buggy models? What is the best > way to solve this problem? > What is the best way to go about designing a memory controller (I have > seen an example on Altera's website in VHDL (but it sucks), as well as > some others in open cores and one written for a homebrew graphics > accelerator card (manticore). I find the documentation and/or > functionality lacking in most of the aforementioned existing reference > designs. > > thanks >Article: 112970
Hi All, I had to integrate a VHDL testbench of complex system with the Python software (which is used to control the real hardware). Additionally it had to be done in portable way. Therefore I've decided to use pipes to establish communication between the Python software and VHDL simulator. Everything works perfectly with GHDL (I can share my solution if anyone is interested in it) but when I tried to use it with Modelsim in our lab, I faced serious problem. It seems, that there is something wrong with reading from the pipe in the Modelsim. The Modelsim reads only a few messages form the pipe, and then it claims, that the end of file has been reached, even though the sending end of the pipe is still active. Maybe Modelsim opens the pipe in non-blocking mode? Or maybe there is something wrong with the endfile function? Unfortunately Modelsim is not opensource, so probably it will be difficult to fix the problem, but maybe someone has found any workaround? Maybe the problem may be fixed by wrapping any libc routines with dynamic library preloaded with LD_PRELOAD? Maybe the problem maybe fixed somehow in the textio package? -- TIA & Regards, Wojtek ZabolotnyArticle: 112971
Hi, thanks for the answer. However I already see the Xilinx reference design but I have a bad experience with this kind of design. I don't need particular performace; 100 MHz speed and burst 2 for me is enaught. I see that opencores IP seems simple and Xilinx IP with MIG seems complicate; I ask to Xilinx Field Application engineer if this IP generated from Xilinx MIG works and they ask me: "I don't know"; so if I'm not sure that this controller work I prefer to use Opencore IP. Sameone have already use the Opencore DDR sdram controller? If so how I must modify the design for the sintesis? Thanks DanieleArticle: 112972
> Unfortunately Modelsim is not opensource, so probably it will be difficult > to fix the problem, but maybe someone has found any workaround? > Maybe the problem may be fixed by wrapping any libc routines with dynamic > library preloaded with LD_PRELOAD? > Maybe the problem maybe fixed somehow in the textio package? Send them a bug report and test case. Cheers, JonArticle: 112973
Hi all, for the picoblaze funs... you can download the latest version of picoblaze C compiler on my website www.poderico.co.uk the latest version is 1.8.4 In this version you have the optimizer (just started) I've got an example how to use the LCD IF on the Spartan3E starter kit... if you want to have a try.. please send me an email for any suggestions... or improvement... Have fun, FrancescoArticle: 112974
The project sounds interesting but why send raw video? Isn't it easier if it is compressed and then sent over a low bandwidth wifi network? lubot77 wrote: > I do have a interesting project. I am planing to wire my house with duplex > multimode fiber. I would like to send from a central location of the house > multiple broadcast video and audio signals. The video should be either 10 or > 12bit digital stream. > With the help of a FPGA we should multiplex I would say up to 5 digital > parallel video streams(each around 200Mbs, with 16M clk and 3Mbs for four > audio channels). The mux out should be 16 or 20bit data stream.
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Compare FPGA features and resources
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