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Webpack as already suggested is a good choice. It is the same now as the ISE full toolset but with a more limited range of devices supported and does cover the board I'm about to suggest. For a board I will of course suggest our Raggedstone1 GBP=A350(+VAT if applies) - approximately US$95 for the RS1-400(Spartan-3 XC3S400-4FG456C) and if you want to work outside of a PC get the PCI I/O Header as it also gives you circa 50 I/O that are 5V tolerant as a side benefit. Bundle price is GBP=A365 - also currently a slightly better offer if join our newsletter subscription. Details here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html. Low cost worldwide shipping is GBP=A310 or approx US$19. John Adair Enterpoint Ltd. frankgerlach@gmail.com wrote: > Hello folks, > I have done FPGA design some years ago using a Schematic Design tool > from Xilinx, so I am not totally "green". What I now want to do is to > specify a design in VHDL and synthesize it into an FPGA. I am doing > this as a hobby venture, so I can't pay thousands of $$ for design > software. Can the experts of this newsgroup suggest a demo board and > free/cheap software that fulfill those requirements ? Maybe a board > from Xilinx and their ISE software? (I could not find out whether ISE > actually includes VHDL synthesis...) As an alternative, I would be > willing to specify my design in C if there is a free/cheap synthesis > tool...Article: 104351
Rich Grise wrote: > On Wed, 21 Jun 2006 23:17:30 +0000, Duane Clark wrote: >> If you do want to use those tools, then Xilinx requires that you >> recompile the drivers against your kernel, if you are using a kernel >> different from the one the compiled against. Kind of annoying, and >> hopefully one of these days Xilinx will do it right. >> >> If you have not recompiled your own kernel, then you probably just need >> to install the kernel sources corresponding to the kernel you have, and >> compile the drivers. I don't use Slackware, so I don't know how it is >> done there. I see that this is crossposted to alt.os.linux.slackware, so >> someone there could probably help with that. > > I have no problem with compiling from source, on my current kernel, but > does Xilinx let us D/L source? Sorta. The "source" is actually the source for a compatibility layer. The bulk of the driver is an x86 object module that the source code invokes. Thus, no AMD64 support. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 104352
I'm looking for the simplest and highest performance possible way to create a PRBS-7 sequence in a Virtex4 FPGA. Any good articles or code snippets anyone can point to? Thanks!Article: 104353
Pseudo-Random Bit Sequences are also called Linear-Feedback Shift Registers. Look at my old app note: http://www.xilinx.com/bvdocs/appnotes/xapp052.pdf Seven bits is one of the simplest designs: Build a 7-bit shift register and form the XOR (or XNOR) of the two rightmost bits, and feed the result into the left-side input. (XOR makes all-zero the lock-up state, XNOR makes all-ones the lock-up state, which I prefer. You can even add a lock-up detector/eliminator) Using SRL16, you can implement it in two Logic Cells. If you want to be less clever, it takes seven Logic Cells (seven flip-flops plus one LUT) Either way, it's a trivial design, and it will run at many hundred MHz. Peter Alfke, Xilinx =================== avl wrote: > I'm looking for the simplest and highest performance possible way to create a PRBS-7 sequence in a Virtex4 FPGA. > > Any good articles or code snippets anyone can point to? > > Thanks!Article: 104354
Thanks for posting the answer - so many do not bother. cheers, /MikeJ > Of course, 5 minutes after I posted the message I found the answer. > > I was never asserting the ENPCOMMAALIGN signal to the RocketIO, > so it never really appeared to sync to the incoming data stream. > > It now looks OK. > > John P > >Article: 104355
John Adair wrote: > Webpack as already suggested is a good choice. It is the same now as > the ISE full toolset but with a more limited range of devices supported > and does cover the board I'm about to suggest. Well, err, and how am I supposed to program your board ? Maybe your solution is indeed better than Xilinx's offering, so please tell us about your VHDL compiler and synthesis tools !Article: 104356
Some other questions to the experts: When I worked with those FPGAs a couple of years ago (I think that were the XC3000s), I used a 10/100Mhz (repeating) Scope and an HP16500 logic analyzer. Well, now I am working as a software engineer and don't have access to that machinery. What do you experts think is the minimum required equipment for FPGA hobby development ? I guess I could do quite a few things with a used 50Mhz analog scope, a soldering iron and some kind of TTL multiplexing circuits attached to the PC parallel port. What do you suggest ?Article: 104357
Webpack contains all the tools for VHDL or Verilog synthesis, back end mapping, place and route and not to forget programming. The Raggedstone1 comes with a parallel port cable (Cable III look alike) to make the physical connection.Webpack is "free" to download from Xilinx. As to comparisons of boards they vary with what you think you need. Our philosophy is to provide a minimalist board but with a big FPGA (for the price target) and a lot more of I/O compared to our competitors. We also support stripboard add-ons by virtue that our I/O is on simple 0.1 inch spaced headers. These headers will even take directly 3.3V DIL based components if you can find some still out there. John Adair Enterpoint Ltd. frankgerlach@gmail.com wrote: > John Adair wrote: > > Webpack as already suggested is a good choice. It is the same now as > > the ISE full toolset but with a more limited range of devices supported > > and does cover the board I'm about to suggest. > Well, err, and how am I supposed to program your board ? > Maybe your solution is indeed better than Xilinx's offering, so please > tell us about your VHDL compiler and synthesis tools !Article: 104358
I am sure someone will correct me if I am wrong, but I think that the free ModelSim XE will simulate core-generated RAM if you have all the correct (and free) libraries installed. I am using the free versions of all the ISE stuff including ModelSim XE and have successfully simulated designs with core-generated RAM. Check on the Xilinx site for the correct versions of the simulation libraries and you should be OK. Joey blisca wrote: > wich kind of simulator should i download or purchase for include in > simulation the ram genarated with core generator?thanksArticle: 104359
On 25 Jun 2006 02:37:02 -0700, "savs" <vidyutg@gmail.com> wrote: > >basically we are using ddr ram and the multi source error is coming for >the signal sys_clk in dcm module....... > Not much to tell from what you expose, but... Maybe you are calling sys_clk the signal coming from outside into DCM clock input, and also the signal coming out of the DCM and beeng fed back to it. These should be two different signals. This is only a guess from all the information you do not give us. Regards, ZaraArticle: 104360
thanx for the reply .... this is my ports table ..... if it helps .... Port Name Net Name Polarity ________ __________ _________ CLKON dcm_clk_s I CLK0 sys_clk_s O CLK90 clk_90_s O CLK180 sys_clk_n_s O CLK270 clk_90_n_s O CLKFB sys_clk_s I thanx again.... SAVS. Zara wrote: > On 25 Jun 2006 02:37:02 -0700, "savs" <vidyutg@gmail.com> wrote: > > > > >basically we are using ddr ram and the multi source error is coming for > >the signal sys_clk in dcm module....... > > > > Not much to tell from what you expose, but... > > Maybe you are calling sys_clk the signal coming from outside into DCM > clock input, and also the signal coming out of the DCM and beeng fed > back to it. These should be two different signals. > > This is only a guess from all the information you do not give us. > > Regards, > > ZaraArticle: 104361
On 25 Jun 2006 13:39:22 -0700, frankgerlach@gmail.com wrote: >Some other questions to the experts: When I worked with those FPGAs a >couple of years ago (I think that were the XC3000s), I used a 10/100Mhz >(repeating) Scope and an HP16500 logic analyzer. Well, now I am >working as a software engineer and don't have access to that machinery. >What do you experts think is the minimum required equipment for FPGA >hobby development ? I guess I could do quite a few things with a used >50Mhz analog scope, a soldering iron and some kind of TTL multiplexing >circuits attached to the PC parallel port. What do you suggest ? You can often pick up old HP 1650s for peanuts on ebay, especially if you're prepared to improvise some cables as units with these missing go particularly cheaply.Article: 104362
On 26 Jun 2006 01:12:36 -0700, "savs" <vidyutg@gmail.com> wrote: >thanx for the reply .... this is my ports table ..... if it helps .... > >Port Name Net Name Polarity >________ __________ _________ > >CLKON dcm_clk_s I >CLK0 sys_clk_s O >CLK90 clk_90_s O >CLK180 sys_clk_n_s O >CLK270 clk_90_n_s O >CLKFB sys_clk_s I > >thanx again.... >SAVS. > That listing seems OK. Maybe the external clock port to your system has been connected to sys_clk_s instead of dcm_clk_s,as it should. Regards, ZaraArticle: 104363
Hi, thanks for the reply, but i didnt fully understand that.Are you telling that i wont be able to probe the iobs of the ddr_controller using the chipscope?.Or the way i am doing is wrong?. regards Subin Joseph Samson wrote: > subint wrote: > >>"subint" <subin.82@gmail.com> wrote in message > >>news:1150971643.167338.124530@r2g2000cwb.googlegroups.com... > >> > >>>Hi, > >>>I am using the chipshop first time. > >> > >>Hi Subin, > >>I recommend the battered cod. :-) > >> > >> > >>>I am using this one to debug my ddr > >>>controller in the v4 board. When i tried to route the data bus of ddr > >>>through the chipscope it generated ILA and inserted into my design but > >>>when i try to implement(map and par) xilinx ise showing error that the > >>>bidirectional port is being driven by some buffer by the chipscope > >>>module.the ddr bus are bidirectional so what changes needed in the > >>>chipscope setting to route my bidirectional port. > >>>regard > >>>subin > > > Symon replied: > > > >>> > >> > >>I think your problem could be that you're trying to probe the pads of the > >>IOBs. There's no way for ChipScope to connect to this without going > through > >>an input buffer. > > > subint followup: > > Hi, > > i am trying to probe the signal going to the IOB.When i try to probe > > the ddr_dq(the inout port of the ddr) i got this error. > > Started : "Map". > > Using target part "4vlx60ff668-10". > > Mapping design into LUTs... > > Running directed packing... > > ERROR:Pack:1564 - The dual data rate register > > > > mem_interface_top0/main_00/top_00/iobs_00/data_path_iobs_00/v4_dq_iob0/oddr_d > > q failed to join the OLOGIC component as required. The output > > signal for > > register symbol > > > [snip] > > > Symon is right, you've specified an IOB output to probe in ChipScope. > Although ChipScope lets you do this, it's generally a bad idea, > especially if you have an IOB flip-flop. In the case where you're > probing the output of a non-DDR IOB flip-flop, ChipScope connects a > probe to the flip-flop output, but then ISE can't place the flip-flop in > the IOB (because there is no routing resource that ISE can find), so the > flip-flop goes in the fabric. Now, instead of having a nice short > clock-to-output delay, you have a much longer delay through the fabric. > In the case of the DDR IOB flip-flop, there is no DDR flip-flop that ISE > can put in the fabric, so the signal can't be routed. > > > --- > Joe Samson > Pixel VelocityArticle: 104364
hi im using xilinx ISE 7.1i with modelsim XE 6.0 starter in verilog....i have been trying to simulate FFT core on modelsim...also i have downloaded "radix 2 fft core" from xilinx core generator examples on xilinx site but failed to simulate it.the error msg in modelsim is as under... --------------------------------------------------------------------------------------------------------------- Loading f:\Modelsim\win32xoem/../xilinx/verilog/unisims_ver.dcm_clock_lost # Loading f:\Modelsim\win32xoem/../xilinx/verilog/unisims_ver.BUFG # Loading work.my_radix2_xfft1024 # ** Error: (vsim-3033) my_radix2_xfft1024.v(135): Instantiation of 'XFFT_V3_1' failed. The design unit was not found. # Region: /design_top_tb_tf/uut/U3 # Searched libraries: # f:\Modelsim\win32xoem/../xilinx/verilog/xilinxcorelib_ver # f:\Modelsim\win32xoem/../xilinx/verilog/unisims_ver # work # Loading work.glbl # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./design_top_tb_tf.fdo PAUSED at line 9 --------------------------------------------------------------------------------------------------------------- both ways same error comes at the same line ...i.e.."instantiation of XFFT_V3 failed"....whether i generate the core through core generator or download from site.. also i hv downloaded FIFO asynchronous core from core generator examples but it is simulating perfectly...means there is some problem with fft core.. if anyone can help me plz let me kno as soon as possible. thanx alotArticle: 104365
subint wrote: > Hi, > thanks for the reply, but i didnt fully understand that.Are you > telling that i wont be able to probe the iobs of the ddr_controller > using the chipscope?.Or the way i am doing is wrong?. > regards > Subin You won't be able to probe the iobs of the ddr_controller using the chipscope. It cannot be done. --- Joe Samson Pixel VelocityArticle: 104366
Hello all, I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 memory but I can not find anymore the VHDL model on the Micron's website ! Does someone know if it still possible to get a VHDL from Micron ? As there still verilog models on the Micron's website and as my modelsim simulator can handle both vhdl and verilog, can someone give some clues to use this verilog sdram model in my vhdl simulation project ? Thank you. Stéphane.Article: 104367
Hi all,
I encountered problems synthesizing following VHDL-code with Altera
Quartus 5.1. Although simulation with ModelSim was OK, the design in the
FPGA did not work correct.
if ( (x - leftborder(resolution) + BlockCopyPixel > 0) then
...
where
x : integer range -19 to 514; --So x can be negative
leftborder(resolution): integer range 0 to 7;
BlockCopyPixel : integer range 0 to 23;
After tracing my design with SignalTap I found out that the if-test did
not work as expected when x was negative.
It worked as intended when I changed it to:
temp:= resize(to_signed(x,12) - to_signed(leftborder(resolution),12) +
to_signed(BlockCopyPixel,12),12);
if (temp > to_signed(0,12)) then
...
This bug was very hard to trace. Is working with ranged integer types
dangerous or is this a bug in Quartus?
Kind regards,
Hendrik.
Article: 104368sjulhes <t@aol.fr> wrote: >Hello all, >I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 >memory but I can not find anymore the VHDL model on the Micron's website ! >Does someone know if it still possible to get a VHDL from Micron ? >As there still verilog models on the Micron's website and as my modelsim >simulator can handle both vhdl and verilog, can someone give some clues to >use this verilog sdram model in my vhdl simulation project ? Maybe this will work? www.ee.byu.edu/class/ee424/labs/MicronSDRAM/mt48lc32m8a2.vhdArticle: 104369
thank you, joey ,now i have some hope! Joseph <joeylrios@gmail.com> wrote in message 1151287570.550042.204430@r2g2000cwb.googlegroups.com... > I am sure someone will correct me if I am wrong, but I think that the > free ModelSim XE will simulate core-generated RAM if you have all the > correct (and free) libraries installed. I am using the free versions > of all the ISE stuff including ModelSim XE and have successfully > simulated designs with core-generated RAM. Check on the Xilinx site > for the correct versions of the simulation libraries and you should be > OK. > > Joey > > blisca wrote: > > wich kind of simulator should i download or purchase for include in > > simulation the ram genarated with core generator?thanks >Article: 104370
frankgerlach@gmail.com wrote: > Hello folks, > I have done FPGA design some years ago using a Schematic Design tool > from Xilinx, so I am not totally "green". What I now want to do is to > specify a design in VHDL and synthesize it into an FPGA. I am doing > this as a hobby venture, so I can't pay thousands of $$ for design > software. Can the experts of this newsgroup suggest a demo board and > free/cheap software that fulfill those requirements ? Maybe a board > from Xilinx and their ISE software? (I could not find out whether ISE > actually includes VHDL synthesis...) As an alternative, I would be > willing to specify my design in C if there is a free/cheap synthesis > tool... You have certainly picked an appropriate time to get interested in FPGA's as a hobby, as there is a cornucopia of low-cost boards on the market. When I first got involved with FPGA's, you couldn't find an affordable (for most hobbyists) board - and were pretty much restricted to PAL's and xPLD's. Hit the Xilinx web site, and check out development boards. The Spartan 3e "starter kit" is an amazing buy at $150 - and comes with a perfectly serviceable x3s500e FPGA as well 64MB of DDR SDRAM, plenty of buttons an lights, a 16x2 LCD panel, and connectors for ethernet VGA, and serial. However, Xilinx had the board developed by Digilent, who are claiming to have a new version of the board with a larger part. In the past, that meant an extra $50 or so for each step-up, but that was for the Spartan 3 family. If you are looking for cheap(er), Digilent also has a CPLD starter kit with Coolrunner II and XC95 parts for $50, as well as a serviceable Spartan 3 starter kit for $99. The Spartan 3e board is a much better buy, but $99 still gets you a Spartan x3s200, 512KB of SRAM, serial port, VGA port, PS/2 port, and ton of connectivity. If you look around, you might even be able to pick up a Spartan 3e "sample pack" for free (or low cost) - they were a Xilinx promotional board that demostrate the 3e booting from a commodity NOR FLASH. (small part, x3s100e, but still quite useful) Although I haven't used them, XESS makes some low-cost FPGA boards as well. There are others, but they seem to all be overseas (Europe and Australia) Altera's offerings are a little less cheap, but Terasic makes some nifty boards with the Cyclone and Cyclone II devices. I have the DE2 board, which has a Cyclone II 2c35. Minimal RAM and Flash (8MB SDR SDRAM, 4MB FLASH) compared to the starter kit, but the DE2 does have a separate USB host and ethernet controller - which means you don't have to buy or design cores for those functions. It has a nice array of switches and lights, as well as 8 7-segment displays and a 16x2 LCD. A cheaper DE1 is scheduled to be out soon that dispenses with the USB, 16x2 LCD, and ethernet, has a smaller 2c20, but will probably only cost half as much. Otherwise, the core board appears to be the same - AC97 controller, VGA DAC, 8MB SDRAM, 4MB FLASH. The best part is, tools for all of these boards are free. Both Xilinx and Altera have free webpack's of their design tools. Altera even lets you use their SignalTap logic analyzer system if you turn on the talkback feature.Article: 104371
sjulhes wrote: > Hello all, > > I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 > memory but I can not find anymore the VHDL model on the Micron's website ! > > Does someone know if it still possible to get a VHDL from Micron ? I contacted them to get VHDL models just last week and got the following reply: "Unfortunately we no longer support VHDL models, as they have not been actively developed in many years. If you absolutely require a VHDL model, I suggest using a 3rd party model that can be compiled into VHDL (or many other languages). www.denali.com or www.synopsys.com" So unless you can find an older model somewhere (they used to have VHDL models), there's no VHDL from Micron anymore. > As there still verilog models on the Micron's website and as my modelsim > simulator can handle both vhdl and verilog, can someone give some clues to > use this verilog sdram model in my vhdl simulation project ? It's pretty much the same as you would do it with VHDL. Just add it to your project, instantiate it in your VHDL (in your testbench or whatever), and there you go. You just have to be able to "read" Verilog good enough that you can get the port descriptions for the entity. Plus, when you compile the Verilog model you have to specify the speed grade as a define, which you can normally pass to the compiler as a command line argument. cu, SeanArticle: 104372
Hi Guys, I need a C Simulation of some Floating Point Cores from the Xilinx coregen. I thought about automatically converting the behavioral VHDL code to C, e.g. with V2C or VHDL-2-C (found via comp.lang.vhdl FAQ part 3). While I'm investigating this -- has anyone in this group already done something similar, or are there C Simulations of the cores available somewhere? Thanks, SimonArticle: 104373
Hi Simon,
"Simon Heinzle" <sheinzle@inf.ethz.ch> wrote in message
news:449fefd7$1@news1.ethz.ch...
> Hi Guys,
>
> I need a C Simulation of some Floating Point Cores from the Xilinx
coregen.
YHM.
At the risk of being deluged: if anyone else has a similar requirement, now
would be a good time to ask. Reply here or email me directly with details of
what you're looking for...
Cheers,
-Ben-
Article: 104374You mentioned that you were trying to implement a muticore processor. I am not sure what you meant by it, but you could have instantiated two DCM by mistake... You might want to post your MHS file if you want to get more help . /Mikhail
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Compare FPGA features and resources
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