Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 102900

Article: 102900
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: "alpha" <zhg.liu@gmail.com>
Date: 22 May 2006 20:43:34 -0700
Links: << >>  << T >>  << A >>

Tommy Thorn wrote:
> alpha wrote:
> > It's just for fun to run it in a FPGA rather than making an ASIC. I
> > spent almost all Saturdays in the past 1 year for this project.
> > I should say, it has lots challenge than a single-issue one.
>
> Very cool, congratulations.
>
> > True,
> > clock speed is pretty low now now (30-60 Mhz). But I am planning to
> > enhance it by using a smarter compiler to removing some corner case
> > from the design.
>
> How much work would it be to make it fully R3000 compatible (say,
> user-level only)?

[I am not trying to make binary compatiable with R3000. No delay slot.
Right now, total 24 instructions. No multiplication. Actully V4's DSP
core can be used to do multiplication. Precise Interrupt works but not
well tested, I had a timer interrupt. Seems still lots work to be
done.]

>
> > Hopefully I cam make it to 100Mhz range.
> > Also, looks I need to buy an evaluation kit from Altera. Xilinx V4
> > block ram gives me some trouble during instruction fetching.
>
> Care to elaborate?

[The design was orignially tageted an Altera ApexII board, so the
instruiction fetching unit fetch instruction from altera's async block
memory and interface to reorder buffers. Then later on, I switched to
bigger V4 chip. I have to play some trick to make it work with Xilinx's
sync block memory. ]


> > My design is from scratch. Its instruction set is almost same as MIPS
> > 3000 (without Multiplication). Lcc C compilier was ported.
> > I can publish the source verilog files, do we have public domain for
> > this purpose?
>
> Picking a license (eg. GPL, LGPL, BSD, public domain, etc) is a separate
> issue from publishing (opencores, sourceforge, someones own web site
> [I'd be happy to host it for you fx.], etc).  Just be careful about
> third party components (such as LCC) which come with their own licence.
>

[I need think about it, thanks anyway. Of course, I do not want to get
any trouble]

>
> (IMHO: Out-of-Order on an FPGA is very cool, but will probably not lead
> to the best performance/LUT ratio - especially not if you can do
> compiler work also.    For single threaded performance, Nios II and
> MicroBlaze are impressive, as is John Jakson's R16.  A 2- or 4-way LIW
> may also make sense).
>

[This design was started in Modelsim just for fun a year ago. The goal
is to make a out-of-order superscalar processor. I even do not know if
I can systhesis it for a FPGA.
9000 LE(s) is pretty big.  50Mhz * 1.5(IPC) = 75 MIPS.  can not compete
with Microblaze or Nios. But it is a good try.
Agree, a simple 2 or 4 way static scheduled VLIW is really worth to
try. ]


> Tommy


Article: 102901
Subject: Re: CPLD (CoolRunner failures)
From: "Nigel" <neilchamberlain@hotmail.com>
Date: 22 May 2006 20:49:36 -0700
Links: << >>  << T >>  << A >>
the supply is capable of approx 3A fault current. however, the limit
was set to a little over 1A when the fault was first detected.


Article: 102902
Subject: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 22 May 2006 23:18:09 -0700
Links: << >>  << T >>  << A >>
Steve, the OP asked for SPI indirect jtag programming,
this is possible with software from
Altera
Lattice
Xilant

Xilinx is not on the list - and none of the references from your
posting
has relevant info how to implemented the jtag indirect SPI programming

we are using a very simply BSCAN to SPI gateway - available for
download here
http://xilant.com/component/option,com_remository/Itemid,53/func,select/id,4/

and rather simple JTAG programming using custom jtag host software, but
also
it would be possible to convert the programming file to SVF and just
play it agains
the SPI gateway and you get the SPI flash programmed

Antti


Article: 102903
Subject: Re: xilinx pricing discrepancy
From: Kolja Sulimma <news@sulimma.de>
Date: Tue, 23 May 2006 09:24:44 +0200
Links: << >>  << T >>  << A >>
John Adair schrieb:
> Headline pricing often has a date sometime in the future against it. 

But they keep publishing the press release on the website, that's enough
for legal action:
http://www.xilinx.com/prs_rls/silicon_vir/0568fx60_spirent.htm

Apparently:
1. An FX20 did cost 50$ in 25k quantities in december 2005
2. Xilinx has been shipping 10gbps MGTs as early as June 2005.

Now, my FAE tells me that there never have been any Virtex-4 with 10gpbs
MGTs. So Xilinx should really modify that web page.


Kolja Sulimma

Article: 102904
Subject: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 23 May 2006 00:25:56 -0700
Links: << >>  << T >>  << A >>
sorry, sure JTAG Tech, etc also, I left the big JTAG companies out of
the list as I assumed its obvious they support the SPI programming over
boundary scan.

Antti


Article: 102905
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: Eric Smith <eric@brouhaha.com>
Date: 23 May 2006 00:37:22 -0700
Links: << >>  << T >>  << A >>
"alpha" <zhg.liu@gmail.com> writes:
> [I am not trying to make binary compatiable with R3000. No delay slot.
[...]
> [I need think about it, thanks anyway. Of course, I do not want to get
> any trouble]

It appears that you've avoided the unaligned load/store instructions,
which are patented.  Between that and not actually being binary
compatible, I don't think you're likely to get in any trouble if you
choose to publish your design.  Of course, I am not a lawyer.

Eric

Article: 102906
Subject: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 23 May 2006 10:07:24 +0200
Links: << >>  << T >>  << A >>
"Antti" <Antti.Lukats@xilant.com> writes:

> Steve, the OP asked for SPI indirect jtag programming,
> this is possible with software from
> Altera
> Lattice
> Xilant

Also add JTAG Technologies (www.jtag.com). 

> it would be possible to convert the programming file to SVF and just

I've done this for microcontrollers, I2C devices etc (not SPI yet, but
the principle is the same). and used Xilinx, Altera, and JTAG
Technologies software to program the devices.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 102907
Subject: ISE 8.1SP4 PN doesnt start
From: "Antti" <Antti.Lukats@xilant.com>
Date: 23 May 2006 01:13:29 -0700
Links: << >>  << T >>  << A >>
hi

after deleting unused xilinx webpack directory the main ISE doesnt
start anymore
is there some trick except full re-install of ISE and service packs?

at the moment PN starts shows the main gui windows,
an hourglass and consumes 99% of CPU time (winXP)

I already tried to fix the registry to fix-remove the references to
webpack install location but that did not help

Antti


Article: 102908
Subject: Re: Unknown Processor Version (8)
From: "Raymond" <raybakk@yahoo.no>
Date: 23 May 2006 01:26:52 -0700
Links: << >>  << T >>  << A >>
It is very strange. If I change from the USB cable to the Par IV, it
works. And if I change back to the USB again it also works.

But if I compile and download it might not work again and I have to
switch to the Parallellcable again?.?

In this case I can use the ParallellCable, but I would really like to
know why it act so strange with the USB.
(My ParallellCable does not fit on my second board (ML401) so I am most
likely to run in to this problem again :(

Raymond


Article: 102909
Subject: OPB Timer MicroBlaze
From: "Raymond" <raybakk@yahoo.no>
Date: 23 May 2006 02:00:42 -0700
Links: << >>  << T >>  << A >>
Has anyone used the OPB Timer on the MicroBlaze?

I am trying to figure out how it works and by doing that I have
inspected some adresses:

in the xparameters.h
#define XPAR_TESTTIMER_BASEADDR 0x41C00000

in the xtmrctr_l.h
#define XTC_TCSR_OFFSET      0     /**< control/status register */
#define XTC_TLR_OFFSET       4     /**< load register */
#define XTC_TCR_OFFSET       8     /**< timer counter register */

After I have called the function
XTmrCtr_mWriteReg(XPAR_TESTTIMER_BASEADDR, 0, XTC_TLR_OFFSET,
0x0F0F0F0F); I suspected the memory to look like this:

0x41C00000  00 00 00 00 00 00 00 00 0f 0f 0f0f 00 00 00 00
0x41C00010  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

But however it looks like this. Does anyone know whats wrong?

0x41C00000  00 00 00 00 0f 0f 0f 0f 00 00 00 00 00 00 00 00
0x41C00010  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

in the in the xtmrctr_l.h
The function I am calling is defined like this:
#define XTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset,
ValueToWrite)   \
    XIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] +
        \
               (RegOffset)), (ValueToWrite))

The XTmrCtr_Offsets[(TmrCtrNumber)]  is "defined" ekstern
extern Xuint8 XTmrCtr_Offsets[];
Where is it ? Do I need to include some other headers?
I suspect it to be the reason that the memory looks unexpected.

Raymond


Article: 102910
Subject: Re: Unknown Processor Version (8)
From: "Raymond" <raybakk@yahoo.no>
Date: 23 May 2006 02:02:07 -0700
Links: << >>  << T >>  << A >>
Grrrr. The problem comes and goes on the ParalellCable too

Raymond


Article: 102911
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: Kolja Sulimma <news@sulimma.de>
Date: Tue, 23 May 2006 11:40:31 +0200
Links: << >>  << T >>  << A >>
Eric Smith schrieb:
> "alpha" <zhg.liu@gmail.com> writes:

>>[I need think about it, thanks anyway. Of course, I do not want to get
>>any trouble]
> 
> 
> It appears that you've avoided the unaligned load/store instructions,
> which are patented.  Between that and not actually being binary
> compatible, I don't think you're likely to get in any trouble if you
> choose to publish your design.  Of course, I am not a lawyer.

To begin with, it is controversial whether publishing a VHDL text that
describes a patented method infringes the patent.
A patent grants the monopoly for "making, using, selling, offering for
sale, or importing the patented invention for the term of the patent".

Implementing the vhdl in an FPGA probably would be "making".
But just describing the invention in a formal way on your web page
should be OK, as the whole point of the patent system is to publish the
invention. Trade secrets and patents are mutually exclusive.

Kolja Sulimma

Article: 102912
Subject: Re: OPB Timer MicroBlaze
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Tue, 23 May 2006 10:48:06 +0100
Links: << >>  << T >>  << A >>
Hi Raymond,

"Raymond" <raybakk@yahoo.no> wrote in message
news:1148374841.922586.212360@j33g2000cwa.googlegroups.com...
> Has anyone used the OPB Timer on the MicroBlaze?
>
> I am trying to figure out how it works and by doing that I have
> inspected some adresses:

> #define XPAR_TESTTIMER_BASEADDR 0x41C00000
> #define XTC_TCSR_OFFSET      0     /**< control/status register */
> #define XTC_TLR_OFFSET       4     /**< load register */
> #define XTC_TCR_OFFSET       8     /**< timer counter register */

> After I have called the function
> XTmrCtr_mWriteReg(XPAR_TESTTIMER_BASEADDR, 0, XTC_TLR_OFFSET,
> 0x0F0F0F0F); I suspected the memory to look like this:
>
> 0x41C00000  00 00 00 00 00 00 00 00 0f 0f 0f0f 00 00 00 00
> 0x41C00010  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> But however it looks like this. Does anyone know whats wrong?
>
> 0x41C00000  00 00 00 00 0f 0f 0f 0f 00 00 00 00 00 00 00 00
> 0x41C00010  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Nothing is wrong, the memory looks perfect. The "TLR" register is 4 bytes
above the base address and that's where the data got written. Why do you
think the memory should look different? If you wrote to the XTC_TCR_OFFSET
then it would look like what you "suspected" before... did you make a typo?

       -Ben-



Article: 102913
Subject: Re: Possible output drive strength when using Micron DDR and Stratix II DDR Controller
From: "KJ" <kkjennings@sbcglobal.net>
Date: Tue, 23 May 2006 10:06:20 GMT
Links: << >>  << T >>  << A >>
> Ok, I'm fully admitting that I didn't read your post super-carefully
> and I'm not looking at the datasheet, but there is a setting in the
> mode bits for drive strength in those Micron DDR chips.
>

Yep, it's the 'Extended Mode register' which, in simulation at least, gets
set to all 0 by the Altera DDR Controller and that should keep the drive
strength at the 'Class II' level.  Haven't checked yet to see if this is
happening correctly on the real board but I suspect that it is.

KJ



Article: 102914
Subject: someone used FIFO along with the OPB-bus in FPGA ?
From: ivo <ivo@ideas.no>
Date: Tue, 23 May 2006 03:35:00 -0700
Links: << >>  << T >>  << A >>
Hi all,

I am exploring the possibility of using a FIFO between the OPB and my custom IP-core. I want to write data from my IP into the FIFO. I see that the FIFO has an output called RFIFO2IP_WrAck. This is an ackonowledge signal that the fifo asserts when it is ready to read data. According to some examples it seems like this signal can go low randomly, that means regardless of the fifo being full or not. To me this means that the data I want to write to the fifo must be buffered before it enters the fifo, resulting in 2 levels fifos. Then it is better to use a self written FIFO that can accept data all the time(unless when the fifo is full, of course).

Is my assumptions wrong ? In real life, maybe this signal never goes low ?

Article: 102915
Subject: Re: xilinx pricing discrepancy
From: MikeShepherd564@btinternet.com
Date: Tue, 23 May 2006 11:40:11 +0100
Links: << >>  << T >>  << A >>
>On the otherhand there are strong truth in advertising laws...
>...you can issue a PO based on those terms and start designing...

You have a touching notion of how widely these laws extend (if they
exist at all).  The general rule is "caveat emptor" and, in general,
no contract is made until a clear offer has been both made and
accepted.

Instead of playing amateur lawyers, engineers should look to practical
means to keep component costs under control.  Suppliers are dismayed
most (and hence most flexible) when they know you have other options.
This is the best reason to keep proprietary aspects of your design to
a minimum.

Article: 102916
Subject: Re: ISE 8.1SP4 PN doesnt start
From: "Antti" <Antti.Lukats@xilant.com>
Date: 23 May 2006 03:56:12 -0700
Links: << >>  << T >>  << A >>
sorry, problem solved the hard way (it was 8.1SP3 not 4 as my posting
heading was)

attempts to revocer, all failing

1 windows registry clean and fix
2 ISE SP3 re-install
3 8.1 re-install
4 win reboot
5 8.1 de-install
6 8.1 install
7 reboot
8 path and env clean up and fix
9 8.1 webpack install to same path where it was initially
10 reboot

at this point both webpack 8.1 and 8.1 all did FROZE after startup.

I was joking that all that helps is

Format [X] ilinx

but then I tried to double click on .ise file, and ISE started normally

so the all problem was damaged .ise project file that ISE tried to load
as default project.

nasty BUG in ISE - did cost me half a day. :(

Antti


Article: 102917
Subject: FPGA delay generator
From: "amko" <sinebrate@yahoo.com>
Date: 23 May 2006 04:20:55 -0700
Links: << >>  << T >>  << A >>
Hello everybody,

Currently I am  designing  very accurate delay generator, which will be
based on FPGA .
This delay generator should have similar technical  requirements with
DG535 http://www.thinksrs.com/products/DG535.htm.
The major Delay Generator requirements are

=B7	2 ns (1ns is desired, but 2ns will be also ok) time resolution on
delayed channel (it means that time differences between any delayed
channels can be set in 2 ns steps)
=B7	maximal 50 ps - 60ps (RMS) jitter on each output.
=B7	14 delayed ECL channels
=B7	Two high speed  (PECL) inputs (500 Mz ECL clock signal and ECL
trigger)
=B7	Configurable via standard bus (Ethernet/USB/Serial bus)
=B7       Internal trigger with variable rate (DDS)
=B7       Internal clock oscillator
=B7       Clock master or slave

Does anybody know for commercial available FPGA boards (preferred ISA
(PC104) or PCI (PC104 plus) standards) that can be suitable for my
requirements?
Sutiable FPGA for my design is V5 or Stratix 2 GX.

Thank you and Regrads,=20
Amir


Article: 102918
Subject: Re: OPB Timer MicroBlaze
From: "Raymond" <raybakk@yahoo.no>
Date: 23 May 2006 04:44:24 -0700
Links: << >>  << T >>  << A >>
No Ben no typos this time.

This is my fault I counted from the left, not the right sorry.

But thanks for answering :)

Raymond


Article: 102919
Subject: Re: xilinx pricing discrepancy
From: "Marc Randolph" <mrand@my-deja.com>
Date: 23 May 2006 05:16:01 -0700
Links: << >>  << T >>  << A >>

Kolja Sulimma wrote:
> John Adair schrieb:
> > Headline pricing often has a date sometime in the future against it.
>
> But they keep publishing the press release on the website, that's enough
> for legal action:
> http://www.xilinx.com/prs_rls/silicon_vir/0568fx60_spirent.htm
>
> Apparently:
> 1. An FX20 did cost 50$ in 25k quantities in december 2005
> 2. Xilinx has been shipping 10gbps MGTs as early as June 2005.

Howdy Kolja,

While the page is "on the web", I wouldn't call it an active page - you
are looking at a historical document (clearly dated June 2005) about
the current state (as of June 2005) and a future predicted price (as of
June 2005).  I think it would difficult to find any evidence that they
are still making those claims, although I suppose you could argue that
since there is no newer *published* information, by default one would
easily assume that to still be accurate.

Note that I'm not defending these nearly useless press releases, which
are purely a marketing ploy to get an absurdly low price in the minds
of engineers, 99% of whom will never  be able to get anywhere close to
that quantity (and therefore, that price).

> Now, my FAE tells me that there never have been any Virtex-4 with 10gpbs
> MGTs.

It depends on what he means by "never" :-)   They were never shipped as
generally available product to any customer that wanted them (lots of
us wanted them, and still do!).  But I assume that Xilinx had 10 Gbps
prototypes working, and even shipped some of those prototypes to
customers as early as June 2005.  None of these statements, however,
mention anything about general availablity or being in full production.
 They could have shipped just a few parts to a few alpha customers and
that would have fulfilled the statements made.  Unfortunately, these
types of press releases are all too common in the technology world
(actually this one isn't as bad as some, where press releases are put
out for products that aren't even designed yet).

> So Xilinx should really modify that web page.

Again, in this particuar case, it's a press release, which is
historical documentation of a public statement.  You can't go back and
change them - the best you could do would be to put a notice at the top
saying that it had been superceeded by something else, or remove it
completely.

Have fun,

   Marc


Article: 102920
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: "Uncle Noah" <nkavv@skiathos.physics.auth.gr>
Date: 23 May 2006 05:34:13 -0700
Links: << >>  << T >>  << A >>
Xilinx block RAM is synchronous read. Is this the source of your
problem?


Article: 102921
Subject: Re: xilinx pricing discrepancy
From: fpga_toys@yahoo.com
Date: 23 May 2006 05:58:42 -0700
Links: << >>  << T >>  << A >>

MikeShepherd564@btinternet.com wrote:
> >On the otherhand there are strong truth in advertising laws...
> >...you can issue a PO based on those terms and start designing...
>
> You have a touching notion of how widely these laws extend (if they
> exist at all).  The general rule is "caveat emptor" and, in general,
> no contract is made until a clear offer has been both made and
> accepted.
>
> Instead of playing amateur lawyers, engineers should look to practical
> means to keep component costs under control.  Suppliers are dismayed
> most (and hence most flexible) when they know you have other options.
> This is the best reason to keep proprietary aspects of your design to
> a minimum.

Certainly ... on the other hand, I made the final "bait and switch"
complaint that shut one vendors advertising rights down for a year
after talking with the local DAs business and economic crime unit.  So
.... your milage may vary depending on your local officals ... the laws
do exist in some areas which mandate clear "truth in advertising"
requirements. If you have a business, I'd suggest checking up on them
before making press releases and printing advertisements, as somebody
may hold you to the printed word if you refuse a sale.

Other references:

http://www.mlmwatch.org/04C/CT/suit.html
http://www.mlmwatch.org/04C/CT/ruling.html

http://sacramento.bizjournals.com/sacramento/stories/2003/07/14/daily32.html

http://64.233.167.104/search?q=cache:BPtVNZKZ7n8J:reclaimdemocracy.org/nike/pr_seek_truth.html+california+truth+in+advertising&hl=en&gl=us&ct=clnk&cd=49


Article: 102922
Subject: Re: MicroBlaze as SubModule Problem
From: "hitsx@hit.edu.cn" <hitsx@hit.edu.cn>
Date: 23 May 2006 06:02:09 -0700
Links: << >>  << T >>  << A >>
I have solved my problem, the bmm hierarchy should be updated as the mb
is changed to be a submodule.
And at the end of every bram, a "Loc" attribute should be added to
point out the location of the bram.
After the two modification, I update the bit file without any warnings.
And then I download the new bit file, and the changes in code take
effect, which proves that this method works.


Article: 102923
Subject: Re: xilinx pricing discrepancy
From: fpga_toys@yahoo.com
Date: 23 May 2006 06:19:04 -0700
Links: << >>  << T >>  << A >>

MikeShepherd564@btinternet.com wrote:
> >On the otherhand there are strong truth in advertising laws...
> >...you can issue a PO based on those terms and start designing...
>
> You have a touching notion of how widely these laws extend (if they
> exist at all).  The general rule is "caveat emptor" and, in general,
> no contract is made until a clear offer has been both made and
> accepted.

By the way Mike ... being from the UK you might not understand that
Xilinx is located in California, the state with the strict "Truth in
advertising" law referenced ... just google calfifornia truth in
advertising ... the law does exist, and is well tested. Even corporate
giant Nike lost a few years back when their PR releases were challenged
... exactly the same issue in this thread. So, if the Xilinx price
claims are not true, in Calif they can run but not hide from the
liability.


Article: 102924
Subject: Re: CPLD (CoolRunner failures)
From: "dp" <dp@tgi-sci.com>
Date: 23 May 2006 06:22:46 -0700
Links: << >>  << T >>  << A >>
Nigel wrote:
> the supply is capable of approx 3A fault current. however, the limit
> was set to a little over 1A when the fault was first detected.

Was the chip hot after the failure? If not, latchup can be ruled out.
The 1 A  it may have had may or may not suffice to fry it if
latchup has occured (for whatever reason). Some large peak
current discharging the power filtering capacitors can have helped,
do you have an idea about that (how much capacitance there, that is)?

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search