Messages from 102775

Article: 102775
Subject: Re: xilinx V4 obufds_25 and 3.3 V
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 20 May 2006 09:47:00 +0200
Links: << >> << T >> << A >>


<leevv> schrieb im Newsbeitrag news:ee9b17b.-1@webx.sUN8CHnE...
> Hi All,
>
> Let say I have one bank in V4 device with all single ended outputs and one 
> differential output. I'd like to have VCCO =3.3V.
>
> This is not allowed in V4, because obufds_33 doesn't exist in V4 and PAR 
> ends with error.
>
> What going to happen if I'll declare all outputs in this bank as LVCMOS_25 
> and LVDS_25, but physically connect VCCO to 3.3V on board?
>
> Will it damage the device?
>
> Probably I'll get some out-of-spec voltage levels for LVDS output. But 
> it's fine for me.
>
> My situation is that diff output CLK signal was overlooked on the board 
> and placed in the 3.3V bank. Board can work with single ended CLK signal 
> but it's better to have differential.
>
> Thanks

should be ok, even if not spc

antti

Article: 102776
Subject: Re: ispLEVER Starter 6.0 FPGA Design Software Available
From: fpga_toys@yahoo.com
Date: 20 May 2006 01:33:22 -0700
Links: << >> << T >> << A >>


bart wrote:
> Lattice has released a new version of our downloadable ispLEVER Starter
> software, concurrent with version 6.0. Device support includes the 90nm
> LatticeECP2-50 and can be downloaded here:
> http://www.latticesemi.com/products/designsoftware/isplever/ispleverstarter.cfm

Native Fedora/Debian linux versions?

Article: 102777
Subject: Re: Spartan 3E
From: "Piotr Wyderski" <wyderski@mothers.against.spam-ii.uni.wroc.pl>
Date: Sat, 20 May 2006 11:45:07 +0200
Links: << >> << T >> << A >>

Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:

[cut -- thank you all for your answers!]

> ... but I wanted to amplify a bit further on your second question.
> 
>> 2. can I use a multiplier and its "neighbour" BRAM simultaneously,
>> i.e. is there enough routing?
> 
> For most applications, you can simultaneously use both the block RAM
> and its neighboring embedded mutliplier.  There is a limit, however, if
> and only if you use the block RAM in x36 mode (512 x 36).

I asked that question because the data sheet doesn't say anything
about the behaviour of the block RAMs configured as ROMs:

"Each multiplier is located adjacent to an 18 Kbit block RAM
and shares some interconnect resources. Configuring an
18 Kbit block RAM for 36-bit wide data (512 x 36 mode) prevents
use of the associated dedicated multiplier.

The upper 16 bits of the 'A' multiplicand input are shared
with the upper 16 bits of the block RAM's Port A Data input.
Similarly, the upper 16 bits of the 'B' multiplicand input are
shared with Port B's data input."

The ROM memories do not have data input ports and thus
there is nothing to share, except for the implementation-dependent
side effects.

    Best regards
    Piotr Wyderski

Article: 102778
Subject: Re: ispLEVER Starter 6.0 FPGA Design Software Available
From: "Piotr Wyderski" <wyderski@mothers.against.spam-ii.uni.wroc.pl>
Date: Sat, 20 May 2006 11:48:47 +0200
Links: << >> << T >> << A >>

bart wrote:

> Lattice has released a new version of our downloadable
> ispLEVER Starter software

Still without even the simplest free simulator?

    Best regards
    Piotr Wyderski

Article: 102779
Subject: Re: Suitable FPGA for my project
From: Franco Tiratore <nie@nie.nie>
Date: Sat, 20 May 2006 10:50:21 GMT
Links: << >> << T >> << A >>

On Fri, 19 May 2006 19:07:51 +0200, Falk Brunner <Falk.Brunner@gmx.de>
wrote:

>Yes. You need a good connection with appropiate termination from your 
>signal source to the FPGA. Coax cable or impedance matched PCB trace. 
>Ribbon may work too, if used properly (as always ;-). Also clocking 
>might bite you. Whats the source? Is there a clock signal availabe to 
>the datastream?

There are some RF and EM experts in our group, what we are missing is
FPGA/digital design/VHDL expertise...
At the beginning we will work with a randomly-generated bit stream...
Or at least we can use a waveform generator...
Can you suggest me... how can we generate such a clock? (Considering
for example the Spartan3 board).

And another point... Can you address me to some board vendor who can
ship to Europe that "evaluation board"? Some link? Considering the low
cost of the Spartan 3 evaluation board, I think I can risk to buy it
for my personal use, at least I will use it for educational purposes
even if it will not fit the final project... But what are the
differences between the evaluation board and the standard one?

>Regards
>Falk

Gruesse,
Franco

Article: 102780
Subject: Re: Suitable FPGA for my project
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Sat, 20 May 2006 13:13:59 +0200
Links: << >> << T >> << A >>

Franco Tiratore schrieb:

> There are some RF and EM experts in our group, what we are missing is
> FPGA/digital design/VHDL expertise...
> At the beginning we will work with a randomly-generated bit stream...
> Or at least we can use a waveform generator...
> Can you suggest me... how can we generate such a clock? (Considering
> for example the Spartan3 board).

Use a crystal clock (30...100 MHz) to feed the FPGA, use a DCM to 
multiply the clock to the appropriate frequency/2, lets say 160 MHz.

Use a second DCM to phase shift this clock by 90 degree.
Wiht the normal (not phase shifted clock) generate your bit pattern and 
push is out of the FPGA using DDR flipflops.
The phase shifted clock is used to generate the clock signal for the 
datastream with centered transitions relative to the data.

Read alot of Xilinx datasheets and application notes. The provide tons 
of very valueable informations.

> And another point... Can you address me to some board vendor who can
> ship to Europe that "evaluation board"? Some link? Considering the low
> cost of the Spartan 3 evaluation board, I think I can risk to buy it
> for my personal use, at least I will use it for educational purposes
> even if it will not fit the final project... But what are the
> differences between the evaluation board and the standard one?

What do you mean by standard one? A evaluation board contains the FPGA 
and some peripherials like RAM, RS232, LED, LCD, FLASH, Ethernet 
(depending on the board) and connectors. Its read to use. Just download 
the right bitfile and you are done.

http://www.altium.com/Products/NanoBoardNB1/
http://www.aufzu.de/FPGA/boards.html

Regards
Falk

Article: 102781
Subject: Re: Why do the electronics manufacturers have to spam me?
From: ziggy <ziggy@fakedaddress.com>
Date: Sat, 20 May 2006 09:44:59 -0400
Links: << >> << T >> << A >>

In article <1148085652.895237.264580@j55g2000cwa.googlegroups.com>,
 "rickman" <spamgoeshere4@yahoo.com> wrote:

> I give my email address in order to get support and Xilinx feels the
> need to send me spam.  I know it is through the support channels
> because I create a different address every time I use support.  Every
> time I end up getting spam.
> 
> It's not just Xilinx, I once contacted Altera because I was getting
> spam from a third party at an address I only gave to Altera.
> 
> I don't recall using this address, tektronix.drawing@arius.com, but I
> don't know why I would be receiving spam from Analog Devices using it.
> 
> 
> The list goes on and on.  Don't these companies realize the ill will it
> creates?

Beacuse that is how marketing works these days?

Article: 102782
Subject: Re: Why do the electronics manufacturers have to spam me?
From: "radarman" <jshamlet@gmail.com>
Date: 20 May 2006 07:26:52 -0700
Links: << >> << T >> << A >>

Sometimes it's spam, sometimes it's not. For example, I might not have
known about an errata from Altera regarding Cyclone II parts and their
M4K blocks if they hadn't sent me an unsolicited warning and link to
the errata sheet. As it happens, I had an affected die - and needed to
use the workaround. That email saved me a lot of pointless debugging.

On the other hand, sometimes I get emails that are clearly "marketroid"
output. However, at least they aren't hawking herbal v1@gr@ or
anything. As an engineer, particularly one working with FPGA's and
CPLD's, I would think that "spam" from a programmable logic vendor
would at least be a little interesting.

Maybe I've been fortunate, but so far the only spam I've gotten as a
result of registering with Xilinx and Altera is a few emails from other
component companies.

Article: 102783
Subject: initial block processing in XST 8.1
From: "Jeff Brower" <jbrower@signalogic.com>
Date: 20 May 2006 08:56:22 -0700
Links: << >> << T >> << A >>

All-

I recently opened a case with Xilinx about initializing arrays of
registers (search for thread "initializing array of registers in XST"
in this group
(http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/1ceb1069103cd272/744fcbc2b99c7c9a?lnk=st&q=initializing+array+of+registers&rnum=2&hl=en#744fcbc2b99c7c9a).

The answer is coming back that XST 8.1 processes initial block
constructs for registers, FSMs, and memories for synthesis, not just
simulation.

Is that correct?  Can anyone confirm that XST 8.1 actually changes the
config bitstream based on initial block content, not just for
simulation output files?

-Jeff

Article: 102784
Subject: Re: Why do the electronics manufacturers have to spam me?
From: MikeShepherd564@btinternet.com
Date: Sat, 20 May 2006 17:47:04 +0100
Links: << >> << T >> << A >>

Partly, they believe they're dispensing something useful.  (Yes,
really).

It's like the confidence of missionaries and evangelists who spread
like cancer through the world, sure that they have the one true
message and that they're doing "good" to the "less fortunate", even
when they can't deal adequately with their own lives.  (I'll leave
contemporary examples in the Middle East to your imagination).  I
always find it cheering to read of missionaries hacked to death by the
people they're so keen to "improve"!

Anyone who subscribes to the Microchip technical newsletter
"microSolutions" was treated this month to the CEO's 2-page article on
"Personality-Driven Culture versus Consciously Designed Culture" and
an advert for his book.  None of us signed up for this
self-congratulating sewage.  We just wanted to learn techniques for
using the company's products.  How many of us concerned with technical
matters are even in a position to exploit this guy's "pearls of
wisdom"?

But they send it anyway.  As you say, it generates ill-will.  I'd like
to read Microchip's technical information, but I won't do that if it's
used as a vehicle for irrelevant stuff.  I'll give them another
chance, but it will take only 30s to add them to our spam list.

Article: 102785
Subject: Re: xilinx V4 obufds_25 and 3.3 V
From: leevv <>
Date: Sat, 20 May 2006 11:37:40 -0700
Links: << >> << T >> << A >>

Thanks Antti, It's interesting why xilinx doesn't show this as a solution. If it doesn't hurt, I'd prefer that tools allow me to use obufds_33, even it is slightly out of spec. I suppose even input LVCMOS_25 under 3.3 V will work fine in most applications.

Article: 102786
Subject: Re: xilinx V4 obufds_25 and 3.3 V
From: "Antti" <Antti.Lukats@xilant.com>
Date: 20 May 2006 12:03:42 -0700
Links: << >> << T >> << A >>

well Xilinx cant put into datasheet what is out of spec.

Antti

Article: 102787
Subject: Signal 2 clocks long but only one clock possible
From: "Dennis" <dennis.binder@gmx.de>
Date: 20 May 2006 13:06:02 -0700
Links: << >> << T >> << A >>

hello,

in a design with virtex4 lx25-10 I have a problem which is caused by an
effect I do not
understand.
I create chipselect signals one by one for a predefined time to write
data off the chip.
Normally these chipselect signals are 3 us long to get the necessary
data through.
Sometime one of these chipselect signals is only 1 us long. But this is
not possible with the
implemented vhdl. So my question is, what effect can cause such a
behavior ?
In this design I process data, which is coming from a gigabit phy
(marvell 881111).
The clock for this IC is running at 125 MHz and is an Input to my FPGA.
The received
data ist synchronized with the other 100MHz in a fifo.
The timing contraints for the design are 2ns OFFSET IN for 125MHz and a
PERIOD of 125MHz and for the second clock a 100MHZ PERIOD.
All Contraints are met by the implematation.
I use ISE 7.1 Webpack.
All Clocks at the FPGA are at Global-Clock-Pins. 125MHZ-Clock drives a
DLL to reach the OFFSET IN requirement.

Any hints would be very welcome !

Dennis

Article: 102788
Subject: Re: Signal 2 clocks long but only one clock possible
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 20 May 2006 14:51:26 -0700
Links: << >> << T >> << A >>

So you receive data at 125 MHz, and you transfer it then at 100 MHz (if
I understand you right)
How do you control the FIFO to prevent it from overflowing? What do you
do with the flags?
Peter Alfke, Xilinx (from home)

Article: 102789
Subject: Re: Why do the electronics manufacturers have to spam me?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sun, 21 May 2006 10:05:09 +1200
Links: << >> << T >> << A >>

MikeShepherd564@btinternet.com wrote:
> Partly, they believe they're dispensing something useful.  (Yes,
> really).

I got 4 reminders about Xilinx's coolrunner seminar, but I thought
that was because they valued my comments so much ;)

<snip>
> 
> Anyone who subscribes to the Microchip technical newsletter
> "microSolutions" was treated this month to the CEO's 2-page article on
> "Personality-Driven Culture versus Consciously Designed Culture" and
> an advert for his book.  None of us signed up for this
> self-congratulating sewage.  We just wanted to learn techniques for
> using the company's products.  How many of us concerned with technical
> matters are even in a position to exploit this guy's "pearls of
> wisdom"?
> 
> But they send it anyway.  As you say, it generates ill-will.  I'd like
> to read Microchip's technical information, but I won't do that if it's
> used as a vehicle for irrelevant stuff.  I'll give them another
> chance, but it will take only 30s to add them to our spam list.

  You should have a look at the "Microchip sues Zilog" patent nonsense,
( and also poor, tiny startup, Luminary Micro )
- More sign of how Steve S. has simply lost the plot. Too much listening 
to those fawning around him, I guess.

  I voted by moving Microchip off our supplier list, so if enough 
designers do the same, perhaps Microchip will return their focus to
engineering...

-jg

Article: 102790
Subject: Re: Signal 2 clocks long but only one clock possible
From: "johnp" <johnp3+nospam@probo.com>
Date: 20 May 2006 15:13:46 -0700
Links: << >> << T >> << A >>

You might try changing your timing constraints to be a bit more
pesimistic to see if that helps.  Try 130MHz and 105Mhz.  I've
had cases (using 6.1) where things would be erratic.  I then tightened
the constraint and poof!  the problem went away.

Good luck.

John Providenza

Article: 102791
Subject: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sun, 21 May 2006 11:26:51 +1200
Links: << >> << T >> << A >>

Antti wrote:
<snip>
> PS hope you guy fixup the mockup with MAX2, I mean machXO beats MAX2
> hands down, not that MAX2 is bad, it's pretty nice, but.. no RAM is a
> real issue

  I see today QuickLogic are ramping their PolarPro devices :
Claim appx $2.95 (in the mythical 'high volume' ) for the 640 register 
device.

  These devices DO have RAM and also FIFO controllers

  So they go up against the MAX II and Mach XO,
(but are, of course, OTP - what you gain is low static Icc)

  Still you could develop using MachXO and then consider a move to 
PolarPro, if the Lattice devices are too hungry, or too expensive... ?

-jg

Article: 102792
Subject: Re: initial block processing in XST 8.1
From: John_H <johnhandwork@mail.com>
Date: Sun, 21 May 2006 00:25:49 GMT
Links: << >> << T >> << A >>

Jeff Brower wrote:
> All-
> 
> I recently opened a case with Xilinx about initializing arrays of
> registers (search for thread "initializing array of registers in XST"
> in this group
> (http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/1ceb1069103cd272/744fcbc2b99c7c9a?lnk=st&q=initializing+array+of+registers&rnum=2&hl=en#744fcbc2b99c7c9a).
> 
> The answer is coming back that XST 8.1 processes initial block
> constructs for registers, FSMs, and memories for synthesis, not just
> simulation.
> 
> Is that correct?  Can anyone confirm that XST 8.1 actually changes the
> config bitstream based on initial block content, not just for
> simulation output files?
> 
> -Jeff

I can confirm that I saw this behavior producing accurate results though 
the syntheis constructs ended up non-ideal.  More than 6 months ago I 
was using the reg declaration to initialize SRLs with non-zero data 
(reg [15:] MySRL = 16'h0802;) and found the INITs made it to the chip. 
Problem was, everywhere there was a one, the shift register split into 
pieces with the ones implemented as registers and the zeros implemented 
in SRLs as appropriate even though one SRL could have made the whole 
thing work.

I can't confirm that *everything* happens in 8.1.03i but it does more 
than Synplify's been doing with respect to initials.

- John_H

Article: 102793
Subject: JTAG chaining of two different Xilinx Spartan 3E boards
From: kishore2k4@gmail.com
Date: 20 May 2006 17:57:40 -0700
Links: << >> << T >> << A >>

Hi,

    I've two development boards with me.
1) Spartan 3E Sample Pack(XC3S100E) with a standard 6-pin JTAG
connector
2) Spartan 3E Starter Kit(XC3S500E) with a standard 6-pin JTAG
interface and on-board digilent USB-JTAG interface.

   My question is that if I connect the two 6-pin JTAG connectors
together like TDO<->TDI, TDI<->TDO,TCK<->TCK, TMS<->TMS and GND<->GND
the VCCs are not connected. If this is done will the two boards show up
together in the scan chain?

   The reason I want to do this is to debug the smaller board at usb
speeds.

Thanks,
kishore.

Article: 102794
Subject: Re: CPLD (CoolRunner failures)
From: "Nigel" <neilchamberlain@hotmail.com>
Date: 20 May 2006 18:03:47 -0700
Links: << >> << T >> << A >>

the failure has manifested on the removed device. we have delidded the
device and verified the short on the die. however, we have not ruled
out that contamination external to the package may have caused the
failure in the first place.

the vendor claims shorting can happen in devices near capacity. i have
heard of no other examples of this. other modules that have the same
CPLD with the same program have not failed.

bottom line: we suspect ESD damage due to mishandling.

thanks for the responses.
N.

Article: 102795
Subject: Re: CPLD (CoolRunner failures)
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 20 May 2006 18:59:40 -0700
Links: << >> << T >> << A >>

Nigel wrote:
> >
> the vendor claims shorting can happen in devices near capacity.

"Vendor" would have to be Xilinx, but I cannot believe that statement.
Filling a low-power CPLD to capacity does not create a Vcc-to-GND short
circuit.
That is not even an urban legend, it's just silly.
Peter Alfke, Xilinx Applications

Article: 102796
Subject: Re: JTAG chaining of two different Xilinx Spartan 3E boards
From: "Bob" <nimby1_NEEDSPAM@earthlink.net>
Date: Sun, 21 May 2006 02:25:06 GMT
Links: << >> << T >> << A >>


<kishore2k4@gmail.com> wrote in message 
news:1148173060.751952.10160@j73g2000cwa.googlegroups.com...
> Hi,
>
>    I've two development boards with me.
> 1) Spartan 3E Sample Pack(XC3S100E) with a standard 6-pin JTAG
> connector
> 2) Spartan 3E Starter Kit(XC3S500E) with a standard 6-pin JTAG
> interface and on-board digilent USB-JTAG interface.
>
>   My question is that if I connect the two 6-pin JTAG connectors
> together like TDO<->TDI, TDI<->TDO,TCK<->TCK, TMS<->TMS and GND<->GND
> the VCCs are not connected. If this is done will the two boards show up
> together in the scan chain?
>
>   The reason I want to do this is to debug the smaller board at usb
> speeds.
>
> Thanks,
> kishore.
>

I'm not sure if it will functionally work, but I would advise you to 
distribute and terminate TCK like any other fast rise/falltime clock. If you 
merely parallel (star or daisy-chain) TCK, without proper termination, 
you're asking for trouble. It's easiest just to use a clock buffer and 
source terminate each TCK separately.

Bob

Article: 102797
Subject: Re: CPLD (CoolRunner failures)
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sun, 21 May 2006 15:51:43 +1200
Links: << >> << T >> << A >>

Nigel wrote:

> the failure has manifested on the removed device. we have delidded the
> device and verified the short on the die. however, we have not ruled
> out that contamination external to the package may have caused the
> failure in the first place.
> 
> the vendor claims shorting can happen in devices near capacity. i have
> heard of no other examples of this. other modules that have the same
> CPLD with the same program have not failed.
> 
> bottom line: we suspect ESD damage due to mishandling.

Who is the 'vendor' you refer to ?
-jg

Article: 102798
Subject: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
From: "bjzhangwn" <bjzhangwn@126.com>
Date: 20 May 2006 22:25:19 -0700
Links: << >> << T >> << A >>

I want to to get the hardware(pcb or shematic) or some other files,and
also I want to know if I want to do this what should i prepare!

Article: 102799
Subject: Re: CPLD (CoolRunner failures)
From: MikeShepherd564@btinternet.com
Date: Sun, 21 May 2006 06:33:18 +0100
Links: << >> << T >> << A >>

>> the vendor claims shorting can happen in devices near capacity.
>
>"Vendor" would have to be Xilinx...

So, all your users buy from you directly?

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