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On Oct 23, 1:24=A0pm, "Symon" <symon_bre...@hotmail.com> wrote: > "Jeff Brower" <jbro...@signalogic.com> wrote in message > > news:9cf3f6ae-59d7-4dc3-aaa5-5924f79ed3c0@64g2000hsu.googlegroups.com... > > > > > Do you think it could be pins that are not used; i.e. not LOC'd or > > referred to at all? =A0There are several of those. > > > -Jeff > > Are there seven of them? > Cheers, Syms. Do you by chance have "use unbonded IOB" checked?Article: 135951
Brian, Thanks for getting back with me. > > It's built in, (to both full ISE 10.1 and Webpack) but it took me most > of a day to find too... > > In ISE, the "sources" window has a little drop down box at the top, > labelled "Sources for:" - select "Behavioural Simulation" here and the > simulator appears in the "Processes" window instead of the synth/PAR > tools. Yes, I see it and it does show ModelSim as the simulator. It must be a default as I do not have ModelSim installed on that PC. > > I seem to remember I had to set an option somewhere to choose between > ISIM and Modelsim, but can't remember where. > Yes, there is a setup screen in the project preferences pulldown but I can't select ISIM, or it's not called ISIM. It's like it's just not there. I tried to download the webpack but the only thing it lets me download is a TAR file. I decompressed this and get some other sort of compressed UNIX format. Can't find a selection for the Windows version of ISE. Can't use their client (machine is not on network and doubt it would work with our ISA and firewall. > ISIM is still a bit ropey compared with Modelsim, but when it doesn't > crash it seems to give accurate simulation results. The "Lite" version > handles moderately large designs but isn't up to post-route simulations > or EDK projects (it slows down to about a nanosecond per second) > > - Brian Would sure like to try it just to see for myself how good/bad it really is. Simple question, too bad they won't talk with me. I did contact Avnet and received the following responce: "You are correct.You must go through your ISE and make a web case.Since they have moved to this process I have heard they are very responsive. I will be in Thiursday AM and I will check in with you if you want to discuss. Thanks," Great responce. Started this simple eval on last week....Article: 135952
Alex (and Brian and Symon and Gabor): On Oct 21, 7:31 pm, LittleAlex <alex.lo...@email.com> wrote: > On Oct 21, 4:54 pm, Jeff Brower <jbro...@signalogic.com> wrote: > > > All- > > > In an existing XC3S-FG676 design, which has worked fine for a couple > > of years, we have recently enabled some previously unused pins. > > Whenever we build the updated logic, we get this message: > > > ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in > > your design > > cannot be automatically placed. > > > Each Group of a specific Standard is listed. > > Standard LVCMOS33 (Vref=NR Vcco=3.30 Terminate=none) 336 IOs, 336 > > locked. > > (59-Inputs, 170-Outputs, 107-Bidirectional) > > Standard LVCMOS25 (Vref=NR Vcco=2.50 Terminate=none) 7 IOs, 0 > > locked. > > (0-Inputs, 7-Outputs, 0-Bidirectional) > > > When we look at the Pad Report, we can't see any pins other than 3.3V > > (with exception of pre-defined VCCINT, VCCO_X, and VCCAUX pins). > > There are no LVCMOS25 pins listed. In the .ucf file, we did not > > define any LVCMOS25 pins and included IOSTANDARD = LVCMOS33 for all > > used pins. > > > What can cause this error? How do we know exactly which bank and/or > > pins to which XST is referring? How can we debug this? > > > We're using ISE v7.1.04i. I can send post the full XST report if > > needed. > > > -Jeff > > IIRC, the pad report contains only the properly placed pads. You'll > need to go back to the UCF to figure it out. > > Have you tried the GUI to nail down all pins? Sometimes it prevents > you from making "mistakes", and the error message from it mey be > enlightening. Exactly -- that's it. The GUI constraints editor found some duplicated pin names (array indexing issue) -- which in turn caused 7 pins to be unlocated, so they ended up with LVCMOS25. Argh. Normally I don't use the GUI constraints editor -- always found it slow and hard to deal with -- but it's error checking is clearly a valuable addition to the XST reports. Thanks Alex. -JeffArticle: 135953
Hi List, I'm using Cyclone II device. How do I find out the clock to output pin delay in the timing report? I have given the timing constraints, but the report displays delays in this fashion From -- some internal register To -- My desired output pin From clock --- the clock When I ask for tco, I expect only "From clock" to "My desired pin". Why does the report have internal register in between? Also, is the timing delay provided by the timing report up to the output pin or is it only the signal up to the input of the I/O cell? Thanks in advance NagarajArticle: 135954
Hello, Have Lattice MACH221 fuse table. Need logic schemetic or at a minimum a boolean equation. Can anyone provide this service? Regards, RJ SilvaArticle: 135955
lecroy7200 wrote: > > Yes, there is a setup screen in the project preferences > pulldown but I can't select ISIM, or it's not called ISIM. > It's like it's just not there. > I don't have 10.1i installed here where I'm typing; but in 9.2i, if you get into the Project Properties window by right clicking the chip icon next to the part number in the sources project view, you select the ISE simulator with something like : Project Properties->Simulator->ISE Simulator Or, the same choice is available in the File->New Project wizard. > > I tried to download the webpack but the only thing it lets > me download is a TAR file. I decompressed this and get > some other sort of compressed UNIX format. Can't find > a selection for the Windows version of ISE. Can't use > their client (machine is not on network and doubt it would > work with our ISA and firewall. > If your unzipper of choice doesn't handle it, first having something like this installed: http://unxutils.sourceforge.net/ Then the following, or something like it, should work on the SingleFileDownload tar file from Xilinx: \usr\local\wbin\tar -x <webpack_SFD.tar ( It's been a few months since I installed this; if it's a tar inside a gzip inside a tar, then do a "gzip -d webpack_SFD.gz" followed by another "tar -x <webpack_SFD.tar" ) Giving you, after a suitable hard disc access interlude, a webpack subdirectory with the setup executable inside. > > Would sure like to try it just to see for myself how good/bad it > really is. Simple question, too bad they won't talk with me. > Slow as molasses when I last tried it, but as another Brian said, it sorta works when it isn't crashing. BrianArticle: 135956
> But it has to be stable.Then if I feed a square wave of say > 10ns period. Do you allways have periodic signals? That is a completely different story than random signal. If you want to phase shift a periodic signal you can use delay locked loops or phase locked loops. I get the effective delay between the original and the > delayed signal as 0 ps. If I increase the input period to 10.001ps, I > get the delay to be 1ps and similarly for an input period of 9.999ns I > get a delay of -1ps. So all I require here is a fixed constant delay > like that of a passive element. Any signal inside an FPGA will have more than 100ps jitter. All you can hope for is an average delay resolution in that order. Even with specialized discrete analog hardware it is hard to get into the range of 1ps jitter even for clock signals let alone for logic. Kolja Sulimma www.cronologic.deArticle: 135957
Finally photos of new baby PC104/PC104+ board Hollybush2 are now available on our website http://www.enterpoint.co.uk/oem_industrial/hollybush2.html. Whilst it's very compact I am expecting this board to offer a highly compedative solution for mid to high level microprocessor and DSP applications. It's based around a Xilinx Spartan-3A DSP FPGA (XC3SD3400A) with a high performance DDR3 DRAM in support. It also has the normal facilities of any processor board including Ethernet, USB, SATA, RS232 and RTC to name a few features. The board has also been design so it can also be used as a standalone bench board. It will be available with either with no PC104 connectors or the short tail(base board) version connector in addition to the standard long tail connectors. It is capabile of running from a single 5V input and we have a jack on board to facilitate the use of power bricks. The board is capabile of generating 6 amps of 3.3V and hence can support add on of standard PC104 or PCI104 boards subject to that limit and the the DC jack's input limit. We will also be offering a wide range dc power supply companion board so this board can be used plane, train and automobile environments. Initial release of this board wil be as a FPGA development board but there will be turnkey soulution based on MicroBlaze for software developers that just want a ready to go target. Further down the line we will also be doing one or more starter kits for DSP and general processing. These kits with have the Hollybush2 as the main target but will also be supplied with supporting companion boards. I would be pleased to have any comments on the Hollybush2 and what you think of the features that we have and maybe ones we didn't have. I would also be interested in what you guys out there would like as companion boards. We are designing these companion boards soon so it's your chance to influence what we bring to the marketplace. John Adair Enterpoint Ltd. - Home of industrial FPGA solutions.Article: 135958
Beautiful! Hans www.ht-lab.com "John Adair" <g1@enterpoint.co.uk> wrote in message news:24006021-64dd-482a-b32d-73a69f53451b@x41g2000hsb.googlegroups.com... > Finally photos of new baby PC104/PC104+ board Hollybush2 are now > available on our website > http://www.enterpoint.co.uk/oem_industrial/hollybush2.html. > Whilst it's very compact I am expecting this board to offer a highly > compedative solution for mid to high level microprocessor and DSP > applications. It's based around a Xilinx Spartan-3A DSP FPGA > (XC3SD3400A) with a high performance DDR3 DRAM in support. It also has > the normal facilities of any processor board including Ethernet, USB, > SATA, RS232 and RTC to name a few features. > > The board has also been design so it can also be used as a standalone > bench board. It will be available with either with no PC104 connectors > or the short tail(base board) version connector in addition to the > standard long tail connectors. It is capabile of running from a single > 5V input and we have a jack on board to facilitate the use of power > bricks. The board is capabile of generating 6 amps of 3.3V and hence > can support add on of standard PC104 or PCI104 boards subject to that > limit and the the DC jack's input limit. We will also be offering a > wide range dc power supply companion board so this board can be used > plane, train and automobile environments. > > Initial release of this board wil be as a FPGA development board but > there will be turnkey soulution based on MicroBlaze for software > developers that just want a ready to go target. Further down the line > we will also be doing one or more starter kits for DSP and general > processing. These kits with have the Hollybush2 as the main target but > will also be supplied with supporting companion boards. > > I would be pleased to have any comments on the Hollybush2 and what you > think of the features that we have and maybe ones we didn't have. I > would also be interested in what you guys out there would like as > companion boards. We are designing these companion boards soon so it's > your chance to influence what we bring to the marketplace. > > John Adair > Enterpoint Ltd. - Home of industrial FPGA solutions.Article: 135959
In message <6004390c7d3a8cb01deeb8e6292@news.acm.uiuc.edu>, Matthew
Hicks <mdhicks2@uiuc.edu> wrote
>The problem with quality is largely related to the analog front-end
>used to capture the digital signal. The algorithms used to refine the
>digital signal would be hard to surpass with a one man team.
If US digital is anything like UK digital TV the limiting factor may be
the broadcaster. Cost and not quality is driving force behind digital
TV. Some (all?) broadcasters will try and squeeze as many channels into
the available bandwidth until the transmitted bit rate for some channels
is barely adequate to provide a picture and sound. If the broadcaster is
not providing enough information for quality video and audio there is
nothing that can be done at the back end to substantially improve the
end result.
--
Alan
news2006 {at} amac {dot} f2s {dot} com
Article: 135960On 2008-10-16, Andreas Ehliar <ehliar-nospam@isy.liu.se> wrote: > Personally I have an almost finished solution based on the XC95 series. > However, I will not tell you how many I need or the exact model number(s) > that I'm using right now. I do have a rather nice architecture which I > believe will be hard to improve on. I'll let you ponder this for a week > or so before I post my idea for a solution. I'm almost finished with my Tetris implementation though it has been put on hold for lack of time at the moment. I believe it should be doable using only one XC95108. This is a pretty bold claim as a normal playing field in Tetris consists of 10 columns and 20 rows and there are only 108 macroblocks in the XC95108. However, there are actually many more flip-flops available in the XC95108 if you only know where to look. In my solution I'm connecting a couple of pins on the CPLD to the JTAG port which allows me to access the 324 flip-flops in the boundary scan chain. By putting the JTAG FSM into SAMPLE mode it is possible to access the boundary scan chain like a shift register with 324 flip-flops. This means that I have to read the playing field in a bit serial fashion, but as we have discussed earlier, bit serial processing is usually resource efficient in a CPLD. I also have a short shift register inside the CPLD so that I can fit one row of the playing field so that I can duplicate it a couple of times when showing it on a TV. I have a couple of other tricks I had to use to make this fit into the device, but nothing very interesting. By using KEEP attributes on a couple of signals I could get the synthesizer to do a better job. Initially I used a separate FSM to put the JTAG FSM into boundary scan mode, but I ended up driving that from the X position counter to save some macroblocks. The inputs are just plain pushbuttons and debounced using an SR based debouncer inside the FPGA. The video output is created by mixing a video signal output and a sync signal output from the CPLD using a transistor and some resistors. My current implementation has this resource utilization: ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 86 /108 ( 80%) 494 /540 ( 91%) 215/216 ( 99%) 81 /108 ( 75%) 14 /69 ( 20%) This version has been tested on real hardware and it is actually working. It was a little weird to hookup the JTAG connection to the CPLD itself though. Initially I also sent the EXTEST command to the CPLD by mistake, which basically meant that the CPLD tristated all outputs. Not a good idea when you are trying to drive the JTAG machine from inside the CPLD :) However, a few features are missing: Currently rows are not being removed once they fill up. It shouldn't be that hard to fix it I hope, but I haven't had time to do it. (I'm hoping here that this could be added without adding more than one function block input...) If I remember correctly I am also missing one tetris block. While I don't believe that many people would like to use this trick in production, I hope that you at least enjoyed reading about it :) > Challenge 2 - A digital watch with as few CPLDs as possible > ----------------------------------------------------------- > > Personally, I have a relatively small solution to this, but there are still > a few tricks I haven't used. In my solution I'm using a 7 segment LED driver > circuit with built in NBCD decoder (the 9368), so if you want to compare > your solution to mine you might want to output NBCD coded numbers out of your > CPLD. My design for this is fairly straight forward. I'm storing the current time, current timer and current alarm in a long shift register in NBCD coded format. I'm using bit serial arithmetic to increase the time to minimize the cost of the arithmetic unit. A special comparator is used to generate the carry to handle rollovers like 9 -> 0 and 5 -> 0. Since a shift register is wasting a lot of combinational logic in a CPLD I am also trying to distribute some of the logic into different parts of the shift register. For example, the rollover from 23 -> 00 is not done directly adjacent to the CPU but further down the shift register. The arithmetic unit would actually increase the time to 24:00:00:0 which will be corrected a little bit later in the shift register. Since I am using a long shift register for all values I don't have to have any sort of mux to get any output to the 9368 LED drivers, I just have to activate the latch enable input to these drivers at the appropriate time. As for the interface I am using one button to adjust the minutes and one button to adjust the hours. (When holding down the button, the minutes and hours will increase.) Two other buttons are used to select wether to view the timer mode or alarm mode. (And likewise modify these modes.) A final button is used to start/stop the timer. All in all, this fits into one XC9572. Unfortunately there is not enough room for a prescaler which means that I will have to drive this circuit using a 540 Hz input signal. This is not very impressive unfortunately. If a XC95108 is used instead there is plenty of space left for a prescaler so that almost any input frequency could be used. This would also allow us to eliminate the 9368 drivers and move the NBCD -> 7 segment decoding to the CPLD. However, if someone is feeling like he or she has too much spare time available I challenge you to use my JTAG boundary scan trick and fit all of this into a XC9536 instead :) /AndreasArticle: 135961
On Thu, 23 Oct 2008 19:54:25 -0700 (PDT), Brian Davis <brimdavis@aol.com> wrote: >lecroy7200 wrote: >> >> Yes, there is a setup screen in the project preferences >> pulldown but I can't select ISIM, or it's not called ISIM. >> It's like it's just not there. >> > I don't have 10.1i installed here where I'm typing; >but in 9.2i, if you get into the Project Properties >window by right clicking the chip icon next to the >part number in the sources project view, you select >the ISE simulator with something like : > Project Properties->Simulator->ISE Simulator Yes: right click on the chip icon is the step I'd forgotten; it's the same in ISE10. And the name is ISE Simulator in the drop-down list, not ISIM. ISE10 and Webpack work in the same way in this respect, so unless the ISE10 installation is corrupt, the Webpack install won't solve it. Incidentally the same downloaded archive does install on both Linux and Windows (32-bit only for Webpack) just as you say. >> Would sure like to try it just to see for myself how good/bad it >> really is. Simple question, too bad they won't talk with me. >> > Slow as molasses when I last tried it, but as another Brian said, >it sorta works when it isn't crashing. In ISE10 it doesn't seem painfully slow to me, unless you have exceeded the project size limitation, though I haven't raced it against Modelsim. - BrianArticle: 135962
On Thu, 23 Oct 2008 14:06:08 -0700 (PDT), Jeff Brower <jbrower@signalogic.com> wrote: >Alex (and Brian and Symon and Gabor): > >On Oct 21, 7:31 pm, LittleAlex <alex.lo...@email.com> wrote: >> On Oct 21, 4:54 pm, Jeff Brower <jbro...@signalogic.com> wrote: >> >> Have you tried the GUI to nail down all pins? Sometimes it prevents >> you from making "mistakes", and the error message from it mey be >> enlightening. > >Normally I don't use the GUI constraints editor -- always found it >slow and hard to deal with -- but it's error checking is clearly a >valuable addition to the XST reports. Thanks Alex. > Okay, that wouldn't have been available in the map.mrp report. But I'd expect the "Translate" stage to leave appropriate complaints in the .bld report. Maybe worth checking, if you want to avoid the GUI constraints editor (which I agree is painful to use) - BrianArticle: 135963
I have generated the PCI express endpoint block for Virtex-5 sx95t. I would like to know if PIO.v is the top level file in the example design folder. Also, I do not see the PIO_64.v file generated. Where can i find this? Your comments would be appreciated.Article: 135964
Tobias, Virtex 5 has AES256, and Virtex 4 does also. These are strictly speaking, encryption, not authentication, but can be used to prevent cloning. V2P and V2 both had triple DES. All have battery backed up key memory. V4 is approved by the NSA (the only FPGA to have passed their requirements). http://edageek.com/2007/02/21/xilinx-virtex-4-fpga-nsa-crypto/ Spartan 3A, 3AN, 3AD, all have "Device DNA" a unique 57 bit code which may be integrated with a user design to prevent cloning. This feature is not perfectly secure, as the means to prevent the cloning must be kept a secret by the customer. Reverse engineering of the bitstream could defeat the feature, but that might cost more than the design is worth, so the feature is attractive to many. You don't protect a $300 bicycle with a $10,000 lock (low cost part, low cost solution). Anti-fuse is considered impossible to reverse engineer. SRAM-based bitstreams in the clear (un-encrypted) can be reverse engineered to find specific items fairly easily (like DCM M and D values). As of today, there is no known method to reduce a bitstream back to the HDL that created it, however. That doesn't mean that someone can't just copy the bitstream and clone boards (if unencrypted). CPLD's have long had bits that when programmed, prevent readback, and cloning. A good place to start is the data sheets describing these features. In future expect to see a broader range of security solutions, across all product families from all vendors (as cloning is a serious problem). Search for papers by Saar Drimer (he is finishing his studies at Cambridge) who has done some good work in this area. http://www.cl.cam.ac.uk/~sd410/ AustinArticle: 135965
I am fairly new to CPL development, and I need to create an emulation of a number of old bipolar Proms (256x4) being used in a very old system by using a CPLD and WInCUPL. My approach was to use the example "Lookup.pld" as a basis for my LUT, with the exception that I am trying to use 8 bits of address to produce a 4 bit output for each of the possible 256 inputs. Using an AT22V10, I am able to (sometimes) create a table of 256 elements in length. -which I have verified to function in a circuit BTW- However, I have noticed that there are certain sequences of values (most, in fact) that will give me errors: "too many Product terms" for each bit of the 4 bit output. So my approach is apparently not the "general solution" that I need. (I have the data for the parts that I need to emulate, and they appear to be "random" values) There does not appear to be any optimization selection that helps either. I have also tried using the AT750x series, hoping that the additional gates would help. -Same issue. Atmel technical support tried to help, however, I was unable to communicate my problem well enough. I was provided a modified example of "Lookup.pld". The issue I have with the example they sent is that there are still only 6 bits of input used, and even though I tried my best to expand the provided solution, I almost always (eventually) ended up with the same issue -not enough product terms. I am wondering if its possible to use some of the address bits (lets say 2 for example), that would be used to "select" which table to use. IOW, the 2 bits would select one of 4 tables, each of six bits in length to address the proper element in the table. Would doing this save product terms? I cannot get the above approach to work either. This was the approach I pitched to Atmel tech support, and was told that it should work, although like I said earlier, the example provided, was not sufficient. perhaps I am missing something(???) What bothers me the most about the issue is that I am trying to re- create something that was created back in the late '70s to early '80s, the chips obviously function, so I am wondering how it was done. I am using a 21st century development tool with optimizers, etc.... I was up until 2:30 last night struggling with this. (and I'm not counting the countless hours already spent over the past few weeks) Please Help if you have any ideas!. I do not want to resort to using High-density CPLDs or FPGAs (size & cost are the main isssues with that) Sorry if this email was long-winded, but I wanted to explain my problem with enough fidelity to hopefully get some real help. Thank you for reading all of this!Article: 135966
Hi Guys,
I am currently looking for a small board with FPGA and USB/Ethernet
module on it. Some time ago we used to use OpalKelly 3010 boards, and
they were just fine, and now they are on of the main candidates. But
since some time has passed, I thought maybe there are some others
interesting products that would satisfy my basic requirements:
1. Plenty of free user I/Os.
2. Fast communication interface (USB1 wouldn't do)
3. Relatively small form factor
4. Developed firmware, so that not much hacking would need to be
involved.
I would be very grateful if somebody could share his experience (known
bugs, etc) with
the following boards (or if you used different ones and can
compare - even better!!)
1. OpalKelly
2. TQM HS3/HV5 from tq-components
http://tq-components.de/produktdatenbank+M5d637b1e38d.html
interesting boards, but haven't heard anything from people using
them
3. TE0300 modules from Trenz-electronic
http://www.trenz-electronic.de/products/fpga-boards/trenz-electronic/industrial-modules.html
same story as in 2.
4. SUZAKU series from www.atmark-techno.com/
There are some others such as Easyfpga and FTDI Fpga boards, but they
offer slow data-rate and very limited in terms of user I/O pins.
Although all listed here products are based on XIlinx chips, this
certainly doesn't have to be case.
Alex
Article: 135967It's possible that a development board we have scheduled for release later in this quarter will meet your requirements. It's not the one I will probably announce next week, or even the release after that, so don't think they are the ones to look at. We also do have the possiblity of doing a small solution based on our Drigmorn1 board, http://www.enterpoint.co.uk/component_replacements/drigmor= n1.html, and an add-on module. For add-on modules we have an ethernet phy module and also a usb2 module based on CY7C68014. The later isn't as fast as it could be but I hope we will improve that shorly. John Adair Enterpoint Ltd. - Making FPGA Technology Work. On 24 Oct, 17:31, Alex <al.lop...@gmail.com> wrote: > Hi Guys, > > I am currently looking for a small board with FPGA and USB/Ethernet > module on it. Some time ago we used to use OpalKelly 3010 boards, and > they were just fine, and now they are on of the main candidates. But > since some time has passed, I thought maybe there are some others > interesting products that would satisfy my basic requirements: > 1. Plenty of free user I/Os. > 2. Fast communication interface (USB1 wouldn't do) > 3. Relatively small form factor > 4. Developed firmware, so that not much hacking would need to be > involved. > > I would be very grateful if somebody could share his experience (known > bugs, etc) with > =A0 the following boards (or if you used different ones and can > compare - even better!!) > 1. OpalKelly > 2. TQM HS3/HV5 =A0from tq-components =A0http://tq-components.de/produktda= tenbank+M5d637b1e38d.html > =A0 =A0 interesting boards, but haven't heard anything from people using > =A0 =A0 them > 3. TE0300 modules from =A0Trenz-electronic =A0 =A0http://www.trenz-electr= onic.de/products/fpga-boards/trenz-electronic/... > =A0 =A0 same story as in 2. > 4. SUZAKU series fromwww.atmark-techno.com/ > > There are some others such as Easyfpga and FTDI Fpga boards, but they > offer slow data-rate and very limited in terms of user I/O pins. > > Although all listed here products are based on XIlinx chips, this > certainly doesn't have to be case. > > AlexArticle: 135968
Today I searched some time for a bug in my software, but it was in Quartus: If I use a statemachine with some states, something like this: type stateType is (idle, readByte, writeByte); and then I initialize it not with the first state: signal state:stateType:=readByte; looks like nevertheless it starts up with the first state. I've tried different settings like "safe statemachine=on" etc., but all the time the same bug. But it works in the simulator. Now I'm using a workaround: I use a counter in the main entity (looks like normal unsigned-variables are initialized correctly on start) and issue a reset from this for the sub-entity, where the buggy statemachine is and where I catch the reset and reset the statemachine to the right state on reset. There is not much more in the Cyclone, no external signals, all inputs are on static levels. A similar bug was in Quartus v7, but fixed with a hot-fix from Altera, after several unsuccessful service packs. Unfortunately I think I can't use Quartus 7, because the support for Cyclone III is preliminary in this version and I need this chip. I wonder how many other bugs are in the software, or if it is only related to things like power up initializing. At least designs compiled with v7 works in customer products, so I'm unsure if I should use v8, with maybe more suprises. I'll at home now, but I just want to know, if someone has similar problems with Quartus 8 and which version is stable. There is V7.5, which looks like has better support for Cyclone III. On monday I'll contact my local Altera FAE and then maybe send the source code to the Altera support, if there is no better solution than my workaround. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 135969
Frank Buss wrote:
> Today I searched some time for a bug in my software, but it was in Quartus:
> If I use a statemachine with some states, something like this:
>
> type stateType is (idle, readByte, writeByte);
>
> and then I initialize it not with the first state:
>
> signal state:stateType:=readByte;
Signal initializations are often ignored for synthesis.
Standard practice is to use a reset input.
-- Mike Treseler
Article: 135970Mike Treseler wrote: > Signal initializations are often ignored for synthesis. > Standard practice is to use a reset input. This feels like a déjà vu, I think I have discussed this before. Quartus has the setting "Power-Up Don't Care". Help text for this option: | Causes registers that do not have a Power-Up Level logic option setting to | power up with a don't care logic level (X). A don't care setting allows the | Compiler to change the power-up level of a register to minimize the area of | the design. This option is not related to my problem, because I have a power-up initializtation, but then my assumption is, that it doesn't ignore power-up intialization (BTW: it was programming a SOF with an USB blaster, not from a config flash, but I assume it is the same). At least a warning would be nice, like "I see your initalization in line xy, but I'll ignore it", but there was no warning. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 135971
On Oct 24, 2:43=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Mike Treseler wrote: > > Signal initializations are often ignored for synthesis. > > Standard practice is to use a reset input. > > This feels like a d=E9j=E0 vu, I think I have discussed this before. Quar= tus > has the setting "Power-Up Don't Care". Help text for this option: > > | Causes registers that do not have a Power-Up Level logic option =A0sett= ing to > | power up with a don't care logic level (X). A don't care setting allows= the =A0 > | Compiler to change the power-up level of a register to minimize the are= a of > | the design. > > This option is not related to my problem, because I have a power-up > initializtation, but then my assumption is, that it doesn't ignore power-= up > intialization (BTW: it was programming a SOF with an USB blaster, not fro= m > a config flash, but I assume it is the same). At least a warning would be > nice, like "I see your initalization in line xy, but I'll ignore it", but > there was no warning. > The documentation for Quartus says it does support initial value declarations (refer to Quartus II Help Version 8.0 "Controlling the Power-Up State of VHDL Designs") so you should probably open a web case with Altera. A post-route simulation that matches what you're seeing would also tend to point to Quartus and give you more ammo for the web case. Maybe add a debug output that decodes the particular state that should exist at t=3D0. dbg <=3D '1' when (state=3DreadByte) else '0'; If this on actual hardware, here are a couple questions to ponder on first that would point to a timing problem - Is the clock running as you're coming out of configuration? - If the clock is running as configuration ends, how do you control the setup time of anything on that very first clock? As a closing comment, you should be using an explicit reset signal to get your state machine into the proper state at power up not a signal initializer anyway. Kevin JenningsArticle: 135972
On Oct 23, 1:27=A0pm, Jon Beniston <j...@beniston.com> wrote: > On 23 Oct, 10:50, adventurer <hry...@gmail.com> wrote: > > > Hello newsgroup! > > > I=92m going to implement my FPGA based =A0SoC with embedded processor. = Now > > I=92m trying to choose soft processor. The main feature for me it=92s a > > good CAD performance =A0and ease to use. I start to work with Xilinx > > EDK, and the questions is : Can I integrate my EDK processor system in > > some top-level schematic, like a component, such as I can do this in > > Quartus. There are many threads about =A0 problem of choose a software > > processor: =A0 Nios vs MicroBlaze and others, but it=92s interesting to > > hear opinions the people who work with both of them, or who study this > > problem more thoroughly. What are the advantages and disadvantages =A0o= f > > every cores? > > Would you really choose either Xilinx or Altera FPGAs based on Nios vs > MicroBlaze? If not, then why compare the two? > > Mico32 for me anyway ;-) > > Jon Maybe the Mico32 is a good processor. Yes LatticeMico32 is licensed under an open core license. The wishbone bus make possible to use many cores from opencores.org. What about CADs? The first impression was not very good. And Lattice chips are not so widely distributed like Xilinx or Altera. Open cores nature of processor allow to implement system on any vendors chip, but what the tools needed to build such system?Article: 135973
Frank Buss wrote:
> This option is not related to my problem, because I have a power-up
> initializtation, but then my assumption is, that it doesn't ignore power-up
> intialization (BTW: it was programming a SOF with an USB blaster, not from
> a config flash, but I assume it is the same). At least a warning would be
> nice, like "I see your initalization in line xy, but I'll ignore it", but
> there was no warning.
For portable code that always sims like it works on the bench,
I must have a physical reset *input*, and an initialization
strategy that does not depend on register values
prior to any input events.
-- Mike Treseler
Article: 135974On Oct 23, 9:27=A0pm, Test <bsilv...@testing-equipment.com> wrote: > Hello, > > Have Lattice MACH221 fuse table. > Need logic schemetic or at a minimum a boolean equation. > Can anyone provide this service? > > Regards, RJ Silva The old MachXL software did this if you have the JEDEC file. If in fact you have the file created by MachXL it would have meaningful names for the signals. The output would be the equations as implemented in the CPLD itself (reduced sum of products) rather than the original code, so you may still need some work to decipher what it does.
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