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Klaus wrote: <snip> > So basically I could say that the logic between two registers is the > same but the routing complexity is so high that I have the long delays. > Is this right? What is confusing me is the timing summary output > > Minimum period: 17.040ns (Maximum Frequency: 58.687MHz) > Minimum input arrival time before clock: 1.681ns > Maximum output required time after clock: 6.731ns > Maximum combinational path delay: 2.318ns > > Here is says that the minimum period for design one is 17ns although the > timing analyzer shows me a critical path of length 19ns? > > Thanks > Klaus Here's a thought: Have you constrined your design for timing at all? If there are no timing constraints for the clock period, the place and route meets all timing constraints (none) on the first pass and doesn't bother trying to improve. The Logic to Route ratio should be able to hang around 50/50 for most properly constrained designs. The 18.9%logic, 81.1% route is telling. Also note the top of both path descriptions: the shorter clock period (still shy of 50/50 logic to route) has 13 levels of logic while the longer clock period is out at 17 levels of logic. Even the synthesizer can make decisions based on constraints to help improve the number of logic levels. Get constraints into your design flow and you'll find the tools will work a little harder. If they're not working hard enough, you can change the map and route effort levels in the GUI options for your design.Article: 136201
On 3 Lis, 15:18, jhal...@TheWorld.com (Joseph H Allen) wrote:
> In article <d7f10746-01b5-42bc-b472-7950aaa74...@b31g2000prf.googlegroups=
.com>,
>
>
>
>
>
>
>
> mikel =A0<mikel...@gmail.com> wrote:
> >Hi
> >Is there a way to increase performance of Altera functional simulation
> >models? Specifically, I am using FFT core in our project and this is
> >the bottleneck of simulation speed, which I am not surprised to see,
> >given that VHO model is hundred of thousand lines of technology mapped
> >code consisting of Altera library primitives. Using Verilog *.VO does
> >not give much improvement.
>
> >Moreover, FFT core simulation performance behaves in weird fashion -
> >until core is feed in with first block of samples sim speed is quite
> >good, then when FFT processing starts it slows down (as expected). But
> >then simulation speed does not improve in idle times between
> >processing of consecutive FFT symbols =3D> when FFT core is idle.
>
> >Regards
> >Michal
>
> Write a simple model to use in place of their model. =A0Use their model o=
nly
> for final cycle-accurate checkout. =A0I'm doing this for their altmemphy-=
based
> memory controllers.
>
> --
> /* =A0jhal...@world.std.com AB1GO */ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0/* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=3D80;q+p-80;p-=3D2*a[p])for(z=3D9;z--;)q=
=3D3&(r=3Dtime(0)
> +r*57)/7,q=3Dq?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?=
!a[p+q*2
> ]?a[p+=3Da[p+=3Dq]=3Dq]=3Dq:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," =
#"[!a[q-1]]);}
I think that for FFT it is not that easy to write simple equivalent
model as for DDR, because it makes transformation to input signal. An
idea could be to create Verilog wrapper calling FFT function as
windows executable generated through Matlab mex compiler (Altera
megacore generates matlab bit accurate model).
Best, requiring lowest effort and most accurate is to get Modelsim
precompiled core from Altera, but I am not sure if they do that.
Once I asked them to provide generation of simulation model for their
complex multiplier megawizard core and they told me that I can create
such model from non-complex multipliers on my own. Yes, I can, I even
can create complex multiplier core this way so why bother to provide
such core at all to customers.
Michal
Article: 136202If anyone's interested it looks as though Xmos (https:// store.xmos.com/) have prices and are now shipping pre-production 4- core devices. 4-core 512BGA $62.60 for two (available now) 4-core 144BGA $20.90 each (December) -- JamesArticle: 136203
On 5 Nov, 19:14, James Harris <james.harri...@googlemail.com> wrote: > If anyone's interested it looks as though Xmos (https:// > store.xmos.com/) have prices and are now shipping pre-production 4- > core devices. > > 4-core 512BGA $62.60 for two (available now) > 4-core 144BGA $20.90 each (December) Corrected spelling of silicon and if the above link wraps it is https://store.xmos.com/ -- JamesArticle: 136204
On 5 Nov, 19:18, James Harris <james.harri...@googlemail.com> wrote: > On 5 Nov, 19:14, James Harris <james.harri...@googlemail.com> wrote: > > > If anyone's interested it looks as though Xmos (https:// > > store.xmos.com/) have prices and are now shipping pre-production 4- > > core devices. > > > 4-core 512BGA $62.60 for two (available now) > > 4-core 144BGA $20.90 each (December) > > Corrected spelling of silicon and if the above link wraps it is > > =A0https://store.xmos.com/ > > -- > James I got a couple of free samples of the 512BGA devices, and they are sending me some of the 144BGA parts in a couple of weeks. LeonArticle: 136205
> but it costs 20 Dollars... So I am wondering if there are any other sites > out there where I can learn this kind of stuff? Try this one on San Jose State University: http://www.engr.sjsu.edu/crabill/ ... also try MIT's OpenCourseWare on FPGA: http://ocw.mit.edu/ans7870/6/6.111/s04/NEWKIT/index.htm -- StoneThrower www.dgmicrosys.comArticle: 136206
On Wed, 5 Nov 2008 05:25:00 -0800 (PST), "lecroy7200@chek.com" <lecroy7200@chek.com> wrote: >FATAL_ERROR:Simulator:Fuse.cpp:424:$Id: Fuse.cpp,v 1.35.4.7 2008/05/28 >00:03:05 > droth Exp $ - Failed to compile generated C code > isim/_tmp/simprim/a_3586507481_2973208550.c Process will >terminate. For > technical support on this issue, please open a WebCase with this >project > attached at http://www.xilinx.com/support. >FATAL_ERROR:Simulator:Fuse.cpp:424:$Id: Fuse.cpp,v 1.35.4.7 2008/05/28 >00:03:05 droth Exp $ - Failed to compile generated C code isim/_tmp/ >simprim/a_3586507481_2973208550.c Process will terminate. For >technical support on this issue, please open a WebCase with this >project attached at http://www.xilinx.com/support. >Do a search on the errors and all Xilinx has is it being a problem in >Linux. I was running it on plain jane XP Pro 32-bit. Look inside that C file and you should see a string (static const char * = "...") containing a source file name. You may be able to localise the problem to one construct within that file. Either there is one thing you have done there and nowhere else; comment it out and try again; or divide and conquer until you find it... There may be an alternative construct to achieve the same goal without crashing ISIM; or at the worst you have something concrete to report to Xilinx. Oh crap, if it's in the simprim folder it's one of Xilinx's own. As it says, it would be good to open a Webcase if you can spare the time. Is this a gate level simulation? If not, what is calling for simprims? can you instantiate a Unisim equivalent instead? - BrianArticle: 136207
Eric wrote: > What do "real" engineers do when they want to preserve the ability to > connect a JTAG pod to a device, but board layout/space concerns > prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG > header that's common on all the JTAG Products? > > I'm somewhat envisioning a tiny small-pin-count press-to-fit > connector, but I have no idea. Are there any > standards in this area? > > Thanks! > ...Eric In the past we've designed in a small footprint connector; and created an adapter harness to go between the programming pod and the new board connector. I don't believe there is a standard on the connector--choose what ever makes sense for you design. I just used a 1.5mm JST connector on a production board I'm designing. The FPGA mfg's have to choose something that is robust (can handle many insertions/extractions) as the pod could be used quite frequently. RobArticle: 136208
http://en.wikipedia.org/wiki/JTAG#JTAG_Adapter_HardwareArticle: 136209
hi http://nibz.googlecode.com quartus archive available nibz40.qar. tight fit 94% of EPM570ZM100C6 16 bit full 64Kcell 16 bit static memory interface 40 (16+16+8) general purpose IO pins bidirectional 512 cell ufm flash boot 1.5 to 2 MIPS on internal clock simple to memorize instruction set fixed many problems of older nibz versions. Ideal for ultra low power (using MAX IIZ) micro controller applications. cheers jackoArticle: 136210
> After debugging the problem further, I am sure I can open, read and > close files from the CF card now. Everything is good while I am > reading files with <= 12KBytes. The previously mentioned exception > occurs when I read the next byte of the open file. > Any ideas? > > Thanks- Hide quoted text - > Try increasing your stack size.Article: 136211
I am working on ML505 board presently. I've some questions to ask. 1) I want to store my user data in SPI Flash? I converted my (program).elf files to (Program).mem file and added with my ARCprocessor.mcs file. It gives final mcs file which contain both program.mem and processor.mcs in .mcs format.Now i want to execute my program using ARCprocessor. When FPGA is configured from SPI it's only loading Processor mcs file not the UserData (Program). How can i debug my program? I'm using Xilinx ISE impact 10.1. plz suggest me. 2) I tried to load my .mcs file to LinearFlash on ML505 board. I tried to use JtagFlasher.exe which is used to load my .mcs file to LinearFlash. But it is giving error libSTL.dll file missed. There is no option in impact also to write my LinearFlash. Can u Help me Plz? and suggest me any other tool to write on my LinearFlashArticle: 136212
"Rayees" <rayie17@gmail.com> wrote in message news:43fa36e2-d5f6-4118-97a6-426f5bac37db@c36g2000prc.googlegroups.com... >I have 3 questions to ask regarding ML505 configurations. > > 1) How to configure Linear Flash on ML505 board? I generated .bin > files and in XILINX impact there is no option to configure linear > flash. > please tell me how to configure linear flash and suggest me any > tools to configure linear flash. Thank You. > search xilinx.com for jtagflasher.exe it can be used to program the linear flash. > 2) and my 2nd questions is how to store bitstreams (data or programs ) > into Flashes of ML505 and how to execute them? > i already loaded them via JTAG cable and i debugged them but > i want them to store in flashes and debug them. Thank You. > http://www.xilinx.com/products/boards/ml505/ml505_10.1_3/standalone_apps.htm > 3) What is the need of 2 platform flashes on ML505 board? why they are > seperated? ????Article: 136213
Hello, I understand that a TC/IP frame has 20 bytes of header + optional field + data. While having a 3 way handshake before establishing a connection, 1) SYN sent 2) SYN received 3) Connection established What should be the format of the frame send. Should I be sending in just the 20 bytes of header as there is no data transfer during this process? The actual data transfer starts after the connection is established, so should I just send headers while establishing the connection. Your comments would be appreciatedArticle: 136214
In comp.arch.fpga, FP <FPGA.unknown@gmail.com> wrote: > Hello, > > I understand that a TC/IP frame has 20 bytes of header + optional > field + data. While having a 3 way handshake before establishing a > connection, > 1) SYN sent > 2) SYN received > 3) Connection established > > What should be the format of the frame send. Should I be sending in > just the 20 bytes of header as there is no data transfer during this > process? The actual data transfer starts after the connection is > established, so should I just send headers while establishing the > connection. > > Your comments would be appreciated The entire protocol is defined in RFC's that you can find here: http://www.ietf.org/rfc.html You can start with RFC 791 (IP) and RFC 793 (TCP), but you will need others along the way. No practical advise from me (I have only attempted UDP on a CPU until now, TCP on an FPGA sounds a 'little' more complex), maybe others can help out. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) No two persons ever read the same book. -- Edmund WilsonArticle: 136215
Having a copy of Ethereal will probably be a big help. http://thud.ethereal.com/ JonArticle: 136216
On 6 Nov, 15:44, FP <FPGA.unkn...@gmail.com> wrote:
> Hello,
>
> I understand that a TC/IP frame has 20 bytes of header + optional
> field + data. While having a 3 way handshake before establishing a
> connection,
> 1) SYN sent
> 2) SYN received
> 3) Connection established
From memory, IP has a 20-byte header. If options are used there are
more but you won't need these in most cases. TCP also has its own 20-
byte header.
As for the handshake the initiating end (the client) sends a SYN (and
a sequence number to which the SYN applies, of course). The server
sends an ACK of the client's sequence number and its own SYN. The
client receives the server's SYN and ACKs it. So the sequence is
Client -- SYN -->
<-- SYN ACK -- Server
Client -- ACK -->
After that communication can proceed. You really need to understand
TCP well to implement it. Check out books by Douglas Comer for sample
code and implemenation details.
>
> What should be the format of the frame send. Should I be sending in
> just the 20 bytes of header as there is no data transfer during this
> process? The actual data transfer starts after the connection is
> established, so should I just send headers while establishing the
> connection.
Yes. Although, IIRC, according to Comer data could be sent in the same
packets most stacks don't do this. When you send a packet over a data
link such as Ethernet you may need to pad small header-only frames to
make the minimum frame size.
To close the connection a 4-way handshake is often used as each end
initiates a FIN ... ACK sequence.
--
James
Article: 136217Hey, Why FPGA based face recognition? MATLAB is fine too right. Is it for the Power or Reconfigurability or .. ? CheersArticle: 136218
On Nov 5, 1:48 am, y.tachw...@gmail.com wrote: > > Thank you for your good advice... Sounds like I could reduce the > number of errors by fixing the naming in the ucf file and reimplement. > However, there is over 300+ name that need to be fixed and I am not > sure if all of them can be this way... > > My thinking is that I need to move the PCI core over to the new > ISE10.1 installation (only webpack with all web updates) from ISE7.1 > but I do not know how to do that! I have read in Xilinx documentation > that once you obtain the IP zip file, you need to expand it in C: > \Xilinx\10.1\ISE\coregen\ip\xilinx so I thought instead I can move the > PCI folder from the ISE 7.1 installation folder to C:\Xilinx\10.1\ISE > \coregen\ip\xilinx and run the coregen hoping to detect a new core but > it did not! > > Do you think that these error messages are because I have not install > the PCI core in the 10.1 installation although it was able to > synthesis? Thank you all for your great help I be surprised if a 7.1 core worked properly in 10.1 I would also be surprised if the web-pack supported the PCI core. AlexArticle: 136219
FP wrote: > I understand that a TC/IP frame has 20 bytes of header + optional > field + data. While having a 3 way handshake before establishing a > connection, > 1) SYN sent > 2) SYN received > 3) Connection established Since you are posting to comp.arch.fpga, I might guess you want to generate IP data in the FPGA. UDP is much easier to generate and process than TCP. You should compare the two before deciding, but UDP is much easier to use, especially when done in hardware. (or a simple state machine.) As for your question, there is an IP header independent of the protocol, then a TCP or UDP header, or ICMP data. You might also need to generate/reply to ARP. -- glenArticle: 136220
LittleAlex wrote: > Just to pick a nit.... > RS-232 does have a protocol. RTS-CTS, DSR-DTR, etc. V.24 describes > the signal levels without mentioning the signal assertion/response. True, but much of it is rarely used. In the days of half duplex communication with line turn around (the hardware could physically only transmit one direction at a time) that protocol was needed. For connecting a terminal to a modem, or a computer to a printer, it isn't needed and isn't used. > So the OP is really saying "I want RS-232 protocol WITHOUT the > protocol". Still a miss-formed question. See above. -- glenArticle: 136221
1stderivat...@gmail.com wrote: > Hey, > Why FPGA based face recognition? MATLAB is fine too right. Is it for > the Power or Reconfigurability or .. ? > > Cheers For an application like Face Recognition, FPGAs would often be used because of the speed of parallelism afforded by the ability to tailor the logic to the task. The next faster step in speed but much faster in development is a DSP based approach, allowing the high algorithmic speed with the ease of higher level software languages. The slower option is to use a generic PC running software designed to accommodate a huge breadth of numerical processing such as MATLAB. But isn't MATLAB much slower and less effective than a human observer? Different applications call for different needs. A human observer can't recognize faces from an enormous database. An FPGA takes a long development time for such a high-level algorithm to get the speed into the system.Article: 136222
What are your views on http://scratchpad.wikia.com/wiki/TileraMulticore as a replacement for FPGA's ? http://www.tilera.com/solutions/digital_baseband.php The current architecture for base stations fall short of delivering the performance, the low latency and the flexibility customers need. To meet the requirements, wireless equipment providers design complex systems with FPGA, ASIC, DSP and processors with each component requiring special tools in a customized development environment. This leads to a long development cycle, sometimes years, before applications can be productized. Changes in standards also impact providers because such systems are inflexible-upgrades can be a slow and expensive process. What providers seek is an uncomplicated, well-designed, architecture that yields good performance. Tilera's processors provide a low latency single solution that integrates many functions seamlessly in a single processor and uses C/C++ to program their applications with industry standard tools. The familiar tools enable customers to preserve their software investments, replace a number of disparate programming methodologies with one standard programming environment, and gain the flexibility they need to support evolving protocols and ever-increasing demands for serviceArticle: 136223
Eric Acouple of approaches for you to consider depending on whether the connector cost is important and whether you have high volume etc.. For high volume it can be worth considering a set of pads, through hole, or flat surface on a regular grid like 2.54mm pitch. You then need a companion board or veroboard to hold a set of sprung pins that make contact and you adapt to the 2x7 connector. You also need mechanical arrangements to make this reliable. You could also adopt our 2x6 format on 1.27mm and buy one of our adaptors that converts the 2x6 to two standard 2x7 2mm connectors. You can see this connector on our Craignell DIP FPGA modules http://www.enterpoint.co.uk/component_replacements/craignell.html or the newly launched Hollybush2 http://www.enterpoint.co.uk/oem_industrial/ho= llybush2.html. You can see the adaptor in our Craignell manual http://www.enterpoint.co.uk/component_replacements/Craignell_User_Manual_Is= sue_1_01.pdf. The adaptors are available for GBP=A310 or US$17. The adaptor supports simultaneous independent SPI and JTAG if you have reason to do that. John Adair Enterpoint Ltd. On 4 Nov, 16:31, Eric <jo...@mit.edu> wrote: > What do "real" engineers do when they want to preserve the ability to > connect a JTAG pod to a device, but board layout/space concerns > prevent the use of the large 14-pin 2mm-pitch dual-row xilinx JTAG > header that's common on all the JTAG Products? > > I'm somewhat envisioning a tiny small-pin-count press-to-fit > connector, but I have no idea. Are there any > standards in this area? > > Thanks! > =A0 =A0...EricArticle: 136224
Hi I have a stupid question. I try to locate where my units of the floorplaner are then actually on the physical chip! So I am wondering there where the physical chip has its mark (a point) I assume that is Slice X0Y0 is that right? If that is the case then the Floorplaner would be quite confusing as it has X0Y79 in the upper left corner. Thanks for clarification ;) Silly Boy
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