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Austin, Thanks for the information. The ML561 board immediately caught my attention as it seem to support 2x72pin dimms in ddr2 at 333Mhz on a VLX50T -2, but the docs refer to xapp850, wich at the moment has a dead link and is nowhere else to find. Maybe you can direct me to that? This is a documented number I can relate to :) Also I would guess this design looses a bit of speed as it has some empty x16 simms disturbing many of the signals. I know all the external stuff needed to improve speed, but I have little detailed control of the internals. Some of the internals can be very hard to get to (like IO skew, delays (to ball), ripple and so on). Often we need to know this to tweak max performance. We need to handle the setup/hold times from the datasheet as a sum of all these unknown parameters, and they may not add up. Thanks again, MortenArticle: 130226
> Do you mean the lowest hardware overhead, the lowest software overhead, or > something else? The lowest software overhead - i.e. I want to maximise the time the processor has to do the number crunching, and minimise the amount of time the processor is moving data around. Given the above, I'm thinking that the FIFO would generate an interrupt when nearly full, the processor would set up the DMA transaction and the DMA would interrupt microblaze when completed. With FSL I'd need to execute a FSL instruction for each sample.Article: 130227
markmcmahon@hotmail.com writes: > Hello everyone, > > My project has several ADC channels with 16bit data up to 24kSPS. > > There is no need for each ADC sample to be sent ASAP to the > microblaze, as the data is processed in chunks of 200 samples. A > previous (non-xilinx) version of this project used a FIFO and a burst > read over a PCI bus to a pentium processor. > > Now, reading about FSL it seems that the microblaze has to execute an > instruction to get every sample of data? Yes. But so did the Pentium... > What I want is the lowest overhead - given that I can use a FIFO, > would the FIFO with DMA route be better suited to my needs than FSL? Where are you going to DMA to? Won't the processor need to execute an instruction to access every sample of data then as well? And wait the memory latency (if any). Personally, I would use a FIFO on the FSL. It seems a lot simpler than DMA! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 130228
Helmut, The customer is always right* (even when they are wrong), so they do not need to "convince us." But, it is true that a clear statement of the problem, along with archived design, etc. is a clear way to get further faster. Austin *Basic definition of "customer," something that we all must accept, and acknowledge (if we want to stay in business).Article: 130229
Abhi, Each manager has their own style for an interview. Mine is decidedly different than most. I ask about what you have done, and what you are doing (with FPGAs, software, or whatever is appropriate). I ask what gets you excited, what is it that you are passionate about in what you do. I have no interest in hiring anyone who doesn't clearly enjoy their work, and who isn't excited about working (here). Other managers will ask about your schooling, grades, courses, etc. I do not find that useful, as I know some of the best students become the worst employees, and some of the worst students become the best employees (education is required, but grades are not always a measure of what you learned, nor how you may perform). Xilinx is also about how you, the person, how you will fit and interact with others here at Xilinx: how do you deal with difficult situations? How do you argue a technical issue? How respectful are you of others, and their diversity (we have employees from around the world working at every site). How innovative are you? Are you able to "think out of the box?" Good luck, AustinArticle: 130230
On 18 mar, 01:36, Peter Alfke <al...@sbcglobal.net> wrote: > If for some (strange) reason you want to roll your own, [...] One reason would be to permit the use of generics. I often use fifos and I try to use generics whenever possible in the rest of my designs but unfortunately, coregen fifos are not compatible with generics. I therefore end up having to create _several_ fifo ngc cores and this is really a pain in the butt for a large design. We are seriously considering rolling our own to ease design reuse with generics (although we haven't yet because we understand that async fifos are tricky to design, as proven by the V4 bug). Can we hope to see generic coregen cores one day? PatrickArticle: 130231
On Mar 17, 10:36=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > > If for some (strange) reason you want to roll your own, > =A0you face three challenges around the FULL flag: > You must detect FULL fast enough, within a 3 ns period. > And you must release FULL in response to a read clock, without getting > into metastable problems. > And you must compare the two counters without decoding glitches. > All this is stuff the we core designers have solved already for you, > at much higher speed... > Peter Alfke, Xilinx Peter, Would it be valid to say that if the user doesn't need a(n almost) full flag on the read side or an (almost) empty flag on the write side that a FIFO design would be pretty relaxed? It's often preferred to have flags act as fast as possible in the "other" clock domain such that adding an extra clock cycle or more in the read domain after a write or vice-versa isn't an acceptable solution. I've been able to have my systems work well without this stressful need. Or is there more of a nuance that I haven't yet understood? I appreciate your guidance, - John_HArticle: 130232
> Where are you going to DMA to? =A0Won't the processor need to execute an > instruction to access every sample of data then as well? =A0And wait the > memory latency (if any). > > Personally, I would use a FIFO on the FSL. =A0It seems a lot simpler > than DMA! > How would I add a FIFO to the FSL? I have read that FSL is FIFO based, but can I parameterize it? (Do you mean add another FIFO or use the one in the FSL?) http://www.xilinx.com/support/documentation/application_notes/xapp529.pdf page 7. I am using the "Create or import peripheral" wizard but I haven't looked at any FSL VHDL yet. As to the overhead, I'm assuming I would get one interrupt per 200 samples from the FIFO instead of servicing 200 interrupts from the FSL. Thanks for your help.Article: 130233
Kolja, I agree. I have also spoken to those responsible for setting the policies and procedures. Do you have a case number you could email me privately? It will help identify where some re-training might be appropriate to improve our service? AustinArticle: 130234
On Mar 18, 8:38=A0am, John_H <newsgr...@johnhandwork.com> wrote: > On Mar 17, 10:36=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > > > > > If for some (strange) reason you want to roll your own, > > =A0you face three challenges around the FULL flag: > > You must detect FULL fast enough, within a 3 ns period. > > And you must release FULL in response to a read clock, without getting > > into metastable problems. > > And you must compare the two counters without decoding glitches. > > All this is stuff the we core designers have solved already for you, > > at much higher speed... > > Peter Alfke, Xilinx > > Peter, > > Would it be valid to say that if the user doesn't need a(n almost) > full flag on the read side or an (almost) empty flag on the write side > that a FIFO design would be pretty relaxed? > > It's often preferred to have flags act as fast as possible in the > "other" clock domain such that adding an extra clock cycle or more in > the read domain after a write or vice-versa isn't an acceptable > solution. =A0I've been able to have my systems work well without this > stressful need. > > Or is there more of a nuance that I haven't yet understood? > > I appreciate your guidance, > - John_H Hi John,the problem we faced when designing a generic core (in my case a "hard" FIFO), is that it has to be universal: run at 550 MHz, stop on FULL and EMPTY, have fully programmable ALMOST flags. That requires both binary and Gray counters, and very fast decoders, plus some metastable protection. A more limited design is obviously simpler. No programmable ALMOST flags =3D no need for binary counters. "Only 320 MHz" =3D ever so slightly relaxed timing. But with no ALMOST flags, the write or read must be stopped in one clock cycle ! Most users (have to and will) accept an extra delay in the release of FULL or EMPTY, as a protection against metastability confusion. The depth of a FIFO is irrelevant, as long as it is deep enough. Dual-ported RAMs are a great help for the designer. You can imagine that (after the Virtex-4 FIFO experience) we tested the hell out of the Virtex-5 hard FIFO. We ran it for weeks with two asynchronous clocks of several hundred MHz, just dancing around EMPTY. No error in E14 "going empty" operations... It's a solid design. Peter Alfke, XilinxArticle: 130235
Hi, The FSL bus has parameters which allows you to specify the size and what kind of FIFO you want. This is from the FSL_v2_11_a datasheet C_FSL_DEPTH Specifies the depth of the FIFO implemented by the FSL bus. The depth can be as low as 1 or as high as 8192. The depth that can be specified is dependent on the implementation scheme of the FIFO. When the parameter C_ASYNC_CLKS is set to 0, the depth allowed is between 1 and 8192. When the parameter C_ASYNC_CLKS is set to 1 and C_IMPL_STYLE is set to 0 (LUT RAM), the depth allowed is between 16 and 128. When the parameter C_ASYNC_CLKS is set to 1 and C_IMPL_STYLE is set to 1 (BRAM), the depth allowed is between 512 and 8192. C_USE_CONTROL Specifies whether or not the control bit is propagated along with the data bit. When set to 1, the control bit is transmitted from master to slave interface. When set to 0, the control bit transmitted to the slave is 0. Setting this bit to 0 when propagation of control bit is not required; enables reduction in the area of the FSL bus. C_ASYNC_CLKS Specifies whether the FIFO in the FSL bus is implemented as a synchronous FIFO or asynchronous FIFO. When set to 1, the FSL implements an asynchronous FIFO. In this case, the clock ports FSL_M_Clk and FSL_S_Clk are used as the master and slave clocks. If set to 0, the FSL is implemented as a synchronous FIFO. In this case, the clock port FSL_Clk is used for both the master and slave interfaces. C_IMPL_STYLE Specifies the style of implementation of the FIFO of the FSL. If set to 1, the FIFO is implemented using BRAMs. If set to 0, the FIFO is implemented using LUT RAMs. This parameter affects timing: When C_IMPL_STYLE=1, there is a one-cycle fall-through latency from a write to an empty FIFO before FSL_S_Exists Göran <markmcmahon@hotmail.com> wrote in message news:64f56d76-50a2-433c-992a-3b230987bca3@i12g2000prf.googlegroups.com... > Where are you going to DMA to? Won't the processor need to execute an > instruction to access every sample of data then as well? And wait the > memory latency (if any). > > Personally, I would use a FIFO on the FSL. It seems a lot simpler > than DMA! > How would I add a FIFO to the FSL? I have read that FSL is FIFO based, but can I parameterize it? (Do you mean add another FIFO or use the one in the FSL?) http://www.xilinx.com/support/documentation/application_notes/xapp529.pdf page 7. I am using the "Create or import peripheral" wizard but I haven't looked at any FSL VHDL yet. As to the overhead, I'm assuming I would get one interrupt per 200 samples from the FIFO instead of servicing 200 interrupts from the FSL. Thanks for your help.Article: 130236
On Mar 18, 11:26=A0am, Patrick Dubois <prdub...@gmail.com> wrote: > On 18 mar, 01:36, Peter Alfke <al...@sbcglobal.net> wrote: > > > If for some (strange) reason you want to roll your own, [...] > > One reason would be to permit the use of generics. I often use fifos > and I try to use generics whenever possible in the rest of my designs > but unfortunately, coregen fifos are not compatible with generics. Google for lpm_fifo_dc and then ask Xilinx why they don't support EIA standard LPM 220 components. KJArticle: 130237
Hello, When can i see vhdl variable with gtkwave. Currently i use three command inside cygwin: ghdl -a --ieee=synopsys -fexplicit --std=93 bench.vhd ghdl -c --ieee=synopsys -fexplicit --std=93 -r bench --stop- time=7000ns --wave=bench.ghw gtkwave bench.ghw a.sav I can't see all vhdl variable. Thank for you helpArticle: 130238
Yes, I have a clock on that pin too. Why do you ask? This IP interacts with many components: rocketIO, SDRAM, ZBTRam, PCI bus and DACs; and that is why, I think, it uses so many clocks. I thougth I was runing out of clocks resources so that using IBUFG I was saving some. The problem is that as the logic grows, even using IBUFG, P&R is unable to route the hole design and I get the ERROR:Place:249. Because my part of the logic on the FPGA generates the signals to enable DACs which move with an external clock, I generated them with system clock and put 3 synchronizers runing at external clock to sync them with it. I mean, reduce as much as possible the part that should use the external clock. So, I'll see how it works. Thanks!, Daniel. On Mar 17, 6:58 pm, Duane Clark <junkm...@junkmail.com> wrote: > Daniel wrote: > > I'm using a virtex2p VP40 (xc2vp40-5ff1152). The pin is AH17, > > according to the datasheet, it's in bank =EF=BB=BF4 and the inputs are > > IO_L74N_4/GCLK3S. > > What I want, is to know the right way to use the DCM. According to the > > users guide, both ways (IBUFG and BUFG) are OK. I want to know which > > one should I use. > > If I use IBUFG I should look for the corresponding DCM and LOC it?. > > > I guess using BUFG and DCM I run out of BUFG's but using IBUFG I > > don't. > > There are not actual different devices on the chip for ibufg and bufg, > so whether you specify ibufgs or bufgs, you will run out at the same > time. I don't ever LOC DCMs in the virtex2p devices I use, and I have > not specified ibufgs; I always just use bufgs, and specify only the > clock pin location. So I don't really know what the problem is in your > case, and why specifying an ibufg fixes it. > > You say that you have a lot of clocks (something you might want to > rethink ;). Are all the other clocks locked to pins, and is one locked > to AJ17?Article: 130239
picnanard@yahoo.fr wrote: > I can't see all vhdl variable. try --disp-tree=procArticle: 130240
Once you have clock buffer assignments that work, be sure to LOC them all in your ucf. I have a Virtex 2 Pro design where I had to figure out the clock placement manually. ISE could not figure it out, and if I didn't LOC every clock buffer, I'd always get an automatic placement error. --- Joe Samson Pixel VelocityArticle: 130241
On 18 mar, 19:13, Mike Treseler <mike_trese...@comcast.net> wrote: > picnan...@yahoo.fr wrote: > > I can't see all vhdl variable. > > try > > =A0 --disp-tree=3Dproc Thank for you help but where does I set this option? inside ghdl -a line or ghdl -c lineArticle: 130242
John_H wrote: (snip) > Would it be valid to say that if the user doesn't need a(n almost) > full flag on the read side or an (almost) empty flag on the write side > that a FIFO design would be pretty relaxed? I would think that if you had almost full and almost empty delayed by a cycle or two that would work well. With full and empty you tend to want them without delay. -- glenArticle: 130243
hi can anybody help me out with my problem please: i have a custom type: type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address, Generate_Strobe, Write_Data); signal state : STATE_TYPE; for debugging purposes i want to route the signal state out of the fpga. for that i have a signal dbg_state std_logic_vector(2 downto 0) in my portmap. but of course the statement dbg_state <= state; does not work. i have to do some type of typeconversion. i just cant find out how to do that... any ideas please ? thanksArticle: 130244
On Mar 18, 2:11=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > John_H wrote: > > (snip) > > > Would it be valid to say that if the user doesn't need a(n almost) > > full flag on the read side or an (almost) empty flag on the write side > > that a FIFO design would be pretty relaxed? > > I would think that if you had almost full and almost empty > delayed by a cycle or two that would work well. =A0With > full and empty you tend to want them without delay. > > -- glen More precisely: FULL and EMPTY must go active "without delay", but the process of going inactive crosses between the clock domains, and usually involves an extra clock delay to protect against metastable confusion. Peter AlfkeArticle: 130245
On Mar 19, 7:32 am, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote: > hi > > can anybody help me out with my problem please: > i have a custom type: > > type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address, > Generate_Strobe, Write_Data); > signal state : STATE_TYPE; > > for debugging purposes i want to route the signal state out of the > fpga. for that i have a > signal dbg_state std_logic_vector(2 downto 0) in my portmap. > but of course the statement dbg_state <= state; does not work. i have > to do some type of typeconversion. i just cant find out how to do > that... > any ideas please ? > > thanks Try: case state is when Idle => dbg_state <= "000"; when Read_Config => dbg_state <= "001"; when Read_Data => dbg_state <= "010"; when Generate_Address => dbg_state <= "011"; when Generate_Strobe => dbg_state <= "100"; when Write_Data => dbg_state <= "101"; when others => NULL; end case;Article: 130246
On Tue, 18 Mar 2008 14:32:08 -0700 (PDT),
u_stadler@yahoo.de wrote:
>i have a custom type:
>
>type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address,
>Generate_Strobe, Write_Data);
>signal state : STATE_TYPE;
>
>for debugging purposes i want to route the signal state out of the
>fpga. for that i have a
>signal dbg_state std_logic_vector(2 downto 0) in my portmap.
>but of course the statement dbg_state <= state; does not work. i have
>to do some type of typeconversion. i just cant find out how to do
>that...
>any ideas please ?
(1) Try comp.lang.vhdl instead.
(2) Write a function to do the type conversion - it makes
life far easier in the long run - and use a case statement
inside that function:
subtype slv3 is std_logic_vector(2 downto 0);
function to_slv3(s: state_type) return slv3 is
begin
case s is
when idle => return "000";
when read_config => return "001";
....etc....
end case;
end;
And then you can simply drive the output...
dbg_state <= to_slv3(state);
(3) Alternatively, make a lookup table.
type state_dbg_lookup is array(state_type) of slv3;
constant state_slv: state_dbg_lookup := (
idle => "000",
read_config => "001",
...
);
And then you can use that lookup table like a conversion function:
dbg_state <= state_slv(state);
Conversion functions are nice because you can use them in
a port map - give the state machine a debug output port of
type "state_type", and wire a slv3 signal to that port...
entity FSM_design is
port (
...
state_visibility: out state_type;
...
);
end;
architecture A of thing_that_uses_FSM_design is
...
signal state_dbg: slv3;
...
begin
...
FSM_instance: FSM_design port map (
...
to_slv3(state_visibility) => state_dbg,
...
);
Constant lookup tables are extremely efficient, and the code
for them is extremely easy to write and maintain, but you can't
use them in a port map as you can a conversion function.
HTH
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 130247
u_stadler@yahoo.de wrote:
> type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address,
> Generate_Strobe, Write_Data);
> signal dbg_state std_logic_vector(2 downto 0) in my portmap.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
function mode2vec (arg : STATE_TYPE)
return std_logic_vector is
begin
return std_logic_vector(
to_unsigned(STATE_TYPE'pos(arg),3)
);
end function mode2vec;
...
dbg_state <= mode2vec(state);
-- Mike Treseler
Article: 130248<u_stadler@yahoo.de> wrote in message news:ca15b973-cf5a-4fba-bf44-a3161eee9238@e10g2000prf.googlegroups.com... > hi > > can anybody help me out with my problem please: > i have a custom type: > > type STATE_TYPE is (Idle, Read_Config, Read_Data, Generate_Address, > Generate_Strobe, Write_Data); > signal state : STATE_TYPE; > > for debugging purposes i want to route the signal state out of the > fpga. for that i have a > signal dbg_state std_logic_vector(2 downto 0) in my portmap. > but of course the statement dbg_state <= state; does not work. i have > to do some type of typeconversion. i just cant find out how to do > that... dbg_state <= std_logic_vector(to_unsigned(STATE_TYPE'pos(state), 3)); The 'pos attribute returns the 'position' within the enumerated type. So STATE_TYPE'pos(Idle) = 0, STATE_TYPE'pos(Read_Config) = 1, etc. This 'position' is of type natural, which then gets converted to an unsigned and finally to a std_logic_vector. As a side note, there is also a 'val attribute which converts an integer into the enumerated type (i.e. STATE_TYPE'val(2) = 'Read_Data'. 'val and 'pos are inverse functions Kevin JenningsArticle: 130249
On Tue, 18 Mar 2008 23:08:18 GMT, "KJ" wrote: >dbg_state <= std_logic_vector(to_unsigned(STATE_TYPE'pos(state), 3)); Very nice, but in the past we have had trouble with some synthesis tools not implementing 'pos and 'val. Does anyone know the current state of play? I know of several tools that *do* support it, but haven't done a thorough check recently. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
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