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On Mar 18, 6:44 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > Austin, > > Thanks for the information. > The ML561 board immediately caught my attention as it seem to support > 2x72pin dimms in ddr2 at 333Mhz on a VLX50T -2, but the docs refer to > xapp850, wich at the moment has a dead link and is nowhere else to find. > Maybe you can direct me to that? > > This is a documented number I can relate to :) Also I would guess this > design looses a bit of speed as it has some empty x16 simms disturbing many > of the signals. > > I know all the external stuff needed to improve speed, but I have little > detailed control of the internals. Some of the internals can be very hard to > get to (like IO skew, delays (to ball), ripple and so on). Often we need to > know this to tweak max performance. We need to handle the setup/hold times > from the datasheet as a sum of all these unknown parameters, and they may > not add up. > > Thanks again, > Morten Check out the Altera StratixIII for DDR3 speeds. There is a video demo on the front page that shows it up to 1.067Gbps. Not sure if Xilinx can touch that? http://www.altera.com/b/stratixiii-ddr3-video.htmlArticle: 130426
Jonathan Bromley wrote: > I have no desire to be a stooge of any of the tool vendors, but > it is also very important to me and to my employer that we treat > them all fairly. We cannot avoid discussing specific tools as > part of our training courses, and we must scrupulously avoid bias. > By contrast, a customer of one single vendor has (almost) no such > obligation of impartiality and, give or take a few legalistic > constraints, can say whatever they want about the tool they > have purchased. Fair enough. Please do keep posting the clever hdl ideas. We'll dish the reviews. I would suggest that designers maintain a non-proprietary module/entity that covers all of the hdl features considered important. Doing this makes it much easier for me to evaluate new tools or new revisions of old tools. It is also makes quick work of writing a bug report when I can freely attach the code and error message. -- Mike TreselerArticle: 130427
On Sun, 23 Mar 2008 06:41:39 -0700 (PDT), Dave Pollum wrote: >> I uninstalled the video card and then re-installed the video card >> software. When I ran Modelsim (stand alone), the fonts were correct. >> But the second time I ran Modelsim, the fonts were huge again. As >> before, the character fonts had large pixels. >> -Dave Pollum > >I've tried ISE WebPack 9.2x with ModelSim XE II starter 5.8c and that >combo works. It still puzzles me that a newer version of ModelSim >acts so oddly. The fact that you have blocky pixels strongly suggests that it is NOT really a font choice issue, but instead something arcane to do with video drivers - as you obviously suspected. *Where* are the huge fonts appearing? Everywhere? Just in the transcript? Does the rest of the display scale to match the fonts? I've never seen anything like this. You can easily configure ModelSim's font sizes, as I guess you're already aware. But if you do so, and choose a huge font, it won't have big blocky pixels - it will be rendered nice and smooth. Can you get to the window preferences menu and try to discover what fonts ModelSim thinks it's using? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 130428
referringto@googlemail.com wrote: > On Mar 19, 7:28 am, Antti <Antti.Luk...@googlemail.com> wrote: >>I have been think and part time working towards a goal to make useable >>and useful serialized processor. The idea is that it should be (snip) > I wonder what the optimization target is? Size? > I am pretty sure that at some point the overhead of handling > a serial datapath exceeds the benefits. eg I would assume > that a 2 or 4 bit datapath does actually use fewer > resources than a 1 bit datapath. I suppose so for FPGA or other modern systems. Years ago I heard about the PDP8/S, a bit serial PDP-8, though the S was also mentioned as meaning slow. In the days of individual transistors it might have made more of a difference. Still, once you have the overhead of bit counting (or whatever unit) it probably doesn't matter much. -- glenArticle: 130429
On 23 Mart, 13:32, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 23 Mrz., 09:12, anilcelebi <anilcel...@gmail.com> wrote: > > > As i understand from the user guides and datasheets i am not allowed > > to split the data smaller than 8 bits. So the maximum rate to serially > > send an 8 bits data is 2.5Gbit/s. If i am wrong please correct my > > mistake and refer some data sheets related to the solution. > > I am not sure that I understand the question. > The V4 MGTs allow user side data busses of 8 bits to 64 bits. > For any of these user side widths a wide range of serial data rates > are > possible up to 6.5gbps (for higher speedgrades). > > The user bus frequency is determined (using 8b10b encoding) by > (serial link rate/10)/number of bytes on user bus > > The interpretation of the data on the user bus is up to the user. You > can > treat it as a stream of nibbles, a stream fo 16-bit words, whatever. > The only restriction is that comma words will alwas take up 8 bits and > will be byte aligned. (But hey, that could be a two-nibble-comma) > > So you can very well send a stream of nibble through a V4 MGT. > And you can run a single link at the 5gbps necessary for your > application > if you choose a higher speedgrade. > > Kolja Sulimma Thanks i will consider that...Article: 130430
"Jon Elson" <elson@pico-systems.com> wrote in message news:hfqdnVk6trG-d3vanZ2dnUVZ_ournZ2d@giganews.com... >I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese > seller, and am having problems with random failures at first power up. > Sometimes it is a stuck I/O pin, sometimes a failure to configure. I > first thought maybe we had an ESD problem, but I'm now thinking these may > be counterfeit. They have white ink printed labels on the front, whereas > other Xilinx chips have laser-etched labels. Also, these Spartan chips > don't have the Spartan logo just below the Xilinx logo, like my other > Xilinx chips. Anyone have any comments on this? > > Jon Surely you've sent one in to Xilinx for their appraisal. What did they say? BobArticle: 130431
I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese seller, and am having problems with random failures at first power up. Sometimes it is a stuck I/O pin, sometimes a failure to configure. I first thought maybe we had an ESD problem, but I'm now thinking these may be counterfeit. They have white ink printed labels on the front, whereas other Xilinx chips have laser-etched labels. Also, these Spartan chips don't have the Spartan logo just below the Xilinx logo, like my other Xilinx chips. Anyone have any comments on this? JonArticle: 130432
Hi Kolja, > If you spent the same human ressources on optimizing the serial > algorithms, don't you think a 15% speedup on a single processor would have been > possible? All parallel results (the 15-20% Adrian quotes) are *in addition* to normal improvements we make to Quartus compile times. In fact, a lot of our effort continues to go into serial algorithm speed (and memory footprint), since these gains usually stack with parallelism gains. We get serial improvements by replacing algorithms with better ones, tuning various parameters/trade-offs, early exiting various algorithms when they reach the design targets. We also play with new compilers, compiler optimization flags, look at memory layout / locality, etc. We leave no stone unturned, and no programmer unflogged :-) > I guess a theoretical computer scientist would call that "not > parallelizable". If you look at a breakdown of Quartus compile time, it is spread across a large number of algorithms/code fragments, few of which contribute more than a few percent each. If there was a big run-time peak, we would have squashed it by now -- hence the relatively even breakdown of run time. So i isn't that the problem isn't parallelizable -- it's that it takes a lot of time & effort to rewrite a large code base to take advantage of multiple processors. Many of the algorithms we parallelize achieve >1.5X speedup (on two CPUs), which is pretty good for a memory-intensive algorithm. With each release of Quartus since Quartus II v6.1 we've introduced more and more parallelism across the flow. > 20% on four processors is hardly impressive and should be possible be > rewriting the makefile alone. Which makefile are your referring to? > Also 15% speedup ist the same as pruchasing the CPU three months > later. But if we speed things up by 15% at our end, and you get a 15% faster CPU, then you've got yourself a 32% speed-up. If we didn't give you that 15%, you'd only have your 15% speed-up. Regards, Paul Leventis Altera Corp.Article: 130433
Jon Elson wrote: > I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese > seller, and am having problems with random failures at first > power up. Sometimes it is a stuck I/O pin, sometimes a failure > to configure. I first thought maybe we had an ESD problem, but > I'm now thinking these may be counterfeit. They have white ink > printed labels on the front, whereas other Xilinx chips have > laser-etched labels. Also, these Spartan chips don't have the > Spartan logo just below the Xilinx logo, like my other Xilinx > chips. Anyone have any comments on this? > > Jon Unlikely to be "counterfeit" in the true sense, but I understand Asia has long had a problem with 'grey market' devices. Stories of truckloads on Intel Pentiums going into one alley in Hong Kong, and truckloads of higher spec'd devices coming out an adjacent alley abound :) With Silicon, there are also the post-package rejects to consider. What happens to them ? (XIlinx actually sell some as Easy Path- could these be Easy path devices, re-labeled ?) -jgArticle: 130434
Jon Elson <elson@pico-systems.com> wrote: >I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese >seller, and am having problems with random failures at first >power up. Sometimes it is a stuck I/O pin, sometimes a failure >to configure. I first thought maybe we had an ESD problem, but >I'm now thinking these may be counterfeit. They have white ink >printed labels on the front, whereas other Xilinx chips have >laser-etched labels. Also, these Spartan chips don't have the >Spartan logo just below the Xilinx logo, like my other Xilinx >chips. Anyone have any comments on this? Photo.. ?Article: 130435
On Mar 23, 10:36 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > referrin...@googlemail.com wrote: > > On Mar 19, 7:28 am, Antti <Antti.Luk...@googlemail.com> wrote: > >>I have been think and part time working towards a goal to make useable > >>and useful serialized processor. The idea is that it should be > > (snip) > > > I wonder what the optimization target is? Size? > > I am pretty sure that at some point the overhead of handling > > > a serial datapath exceeds the benefits. eg I would assume> that a 2 or 4 bit datapath does actually use fewer > > > resources than a 1 bit datapath. > > I suppose so for FPGA or other modern systems. I would even go as far as saying that a 1 bit datapath does not even represent the clock speed optimum. The clock speed optimum is probably around 4-8 bits.Article: 130436
On Mar 23, 4:33=A0pm, bish <bishes...@gmail.com> wrote: > On Mar 20, 1:09 am, "David Binnie" <td.bin...@blueyonder.co.uk> wrote: > > > The Virtex2Pro board is not recognised by the latest version of EDK (9.2= i) > > > If you want larger memory the V2P DDR memory interface requires speciali= st > > support. > > Digilent nor Xilinx =A0will not give you a working example. > > > Strongly suggest Spartan 3A board instead. > > hmm, there are basically two reasons we want to use FPGA board in our > robotics club of our college: > > i) We want to make SOC designs used for image processing, path > planning, motion control for our robots which need both processor and > dedicated hardware. Since this type of design has not been used so far > here, we are actually trying to introduce it and hence finding it > difficult to select the best way. > Once started it will continue with newer students every year. > > ii) We want to complete a project with a working robot that could > track some colored object or some specific shaped object. Finding such > object in a room. > > Your suggestions for the board have been helpful and I hope I'll get > more insight with a bit more discussion. Thank you. Looking at the Spartan-3A board it seems it could be better. I'm still not clear about if we can use some softcore processor in this board's FPGA. What about extra cost for the license (if required) to use, say, microblaze. Putting it in simpler way, we want to have an embedded platform where we could use FPGA for designing hardwares like pwm generators, quadrature phase decoders, display controllers, parallel algorithms for image processing, and then we could use the processor present in it to do planning, some AI and high level tasks. Now the cost of the board is given in the xilinx sites, but would that be enough to use the board as with our requirement stated above?? I'm student and have to convince our professor so that the college would buy the boards but still have some limited budget. Initially I thought virtex II pro board would be best but now I think I've to know bit more before I can be clear. Hope to get some help soon!!!Article: 130437
hi groups !
what is the best route in order to use an edk generated mpmc ddr2
controller with a custom processor (not microblaze, but gaisler leon3
or even picoblaze ; this is for edu. purpose...) ?
I have a copy the ddr2_sdram_wrapper.ngc and
clock_generator_0_wrapper.ngc files (these are good, tested with a
microblaze design).
I read xilinx mpmc.pdf but I am lost ... I think I need interface my
cpu with opbv46 port 0, that is :
SPLB0_Clk : in std_logic;
SPLB0_Rst : in std_logic;
SPLB0_PLB_ABus : in std_logic_vector(0 to 31);
SPLB0_PLB_PAValid : in std_logic;
SPLB0_PLB_SAValid : in std_logic;
SPLB0_PLB_masterID : in std_logic_vector(0 to 0);
SPLB0_PLB_RNW : in std_logic;
SPLB0_PLB_BE : ...
is there a reference design somewhere...?
I know I should use mig, but this seems not be an easy task too...
best regards,
raph
Article: 130438On 24 Mrz., 04:17, Paul Leventis <paul.leven...@gmail.com> wrote: > If you look at a breakdown of Quartus compile time, it is spread > across a large number of algorithms/code fragments, Of course. I spent years in EDA algorithm research. > > 20% on four processors is hardly impressive and should be possible be > > rewriting the makefile alone. > > Which makefile are your referring to? Whatever script it is that controls the tool flow. I am not familiar with Quartus, but generally for an EDA flow it is possible to start synthesis on multiple source files in parallel without changing the algorithms. You can also run bitstream generation in parallel with post layout timing analysis. The cleanup/report phase of any step could be overlapped with the previous step, and so on. > > > Also 15% speedup ist the same as pruchasing the CPU three months > > later. > > But if we speed things up by 15% at our end, and you get a 15% faster > CPU, then you've got yourself a 32% speed-up. If we didn't give you > that 15%, you'd only have your 15% speed-up. Yes. But all these are minor cleanups when you consider the class of algorithms involved. Runtime between different placers for the same quality of results vary orders of magnitude. Try to run you 1999 placer on a design from today. KoljaArticle: 130439
"Peter Alfke" <peter@xilinx.com> wrote in message news:8ce02f2f-1e15-4ae9-8eb0-caacc2f09b48@e6g2000prf.googlegroups.com... > >> When using the series resistor technique there are also a couple of other >> considerations. Firstly, you need to make sure that the input FET gate >> can >> actually withstand 5V without breaking down - in other words, it is the >> maximum current and not maximum voltage that makes the pin non-5V >> tolerant >> to start with. Secondly, you need to make sure that the power supply >> powering the I/Os (or more particularly the clamp diodes) can sink >> current. >> If it can't you need to add a resistor from power to ground. > I was not too keen to jump onto this unpleasant subject, but I must > correct David: > The basic issue is to avoid excessive voltage on the input, and the > external resistor, together with the internal clamp diode (together > with a power supply that can absorb current) does just that > beautifully!. So the chip input never sees a voltage higher than Vcc + > 0.7 V diode drop. You can easily measure this. > The secondary issue is the amount of current, if the resistor value is > too small, or the excessive delay if the resistor value is too high. > And all of this only works if there is a clamp diode to Vc (and the > supply can absorb the current, especially from many pins). > We just hope that 5-V soon becomes a relic of the past, same as 12 V > became obsolete long ago... > Peter Alfke, Xilinx Sorry Peter - I was confusing the subject by going beyond the OP's Spartan 3 discussion. What I was trying to say (not very well!) is that if you are going to try and limit voltage with a series resistor then you need first to ensure that there is a high-side clamp diode. Obviously if there isn't, the gate will see the full voltage and the input transistor may be compromised.Article: 130440
On Mar 24, 9:18 am, "rpons...@gmail.com" <rpons...@gmail.com> wrote: > hi groups ! > > what is the best route in order to use an edk generated mpmc ddr2 > controller with a custom processor (not microblaze, but gaisler leon3 > or even picoblaze ; this is for edu. purpose...) ? > > I have a copy the ddr2_sdram_wrapper.ngc and > clock_generator_0_wrapper.ngc files (these are good, tested with a > microblaze design). > > I read xilinx mpmc.pdf but I am lost ... I think I need interface my > cpu with opbv46 port 0, that is : > SPLB0_Clk : in std_logic; > SPLB0_Rst : in std_logic; > SPLB0_PLB_ABus : in std_logic_vector(0 to 31); > SPLB0_PLB_PAValid : in std_logic; > SPLB0_PLB_SAValid : in std_logic; > SPLB0_PLB_masterID : in std_logic_vector(0 to 0); > SPLB0_PLB_RNW : in std_logic; > SPLB0_PLB_BE : ... > > is there a reference design somewhere...? > > I know I should use mig, but this seems not be an easy task too... > > best regards, > raph If you want to interface the MPMC (any version from 2.x up to the 3.x found in EDK 9.2), you're best bet is to look at the NPI (Native Port Interface). That's what every port on the MPMC interfaces to. The MPMC uses it as the base interface, and then when you instantiate a OPB, PLB, XCL, etc port it has a wrapper that sits on top of the NPI. The NPI provides a simple direct-to-the-FIFO interface of the MPMC. Be careful following the documented standard, though. It is very picky and sometimes some of the 'protocol' is not 100% documented and is inferred. This will allow you to create your own wrapper to connect to any other bus.Article: 130441
sky465nm@trline4.org wrote: > Jon Elson <elson@pico-systems.com> wrote: > >>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese >>seller, and am having problems with random failures at first >>power up. Sometimes it is a stuck I/O pin, sometimes a failure >>to configure. I first thought maybe we had an ESD problem, but >>I'm now thinking these may be counterfeit. They have white ink >>printed labels on the front, whereas other Xilinx chips have >>laser-etched labels. Also, these Spartan chips don't have the >>Spartan logo just below the Xilinx logo, like my other Xilinx >>chips. Anyone have any comments on this? > > > Photo.. ? > OK, where should I put the photos? JonArticle: 130442
"Jon Elson" <elson@wustl.edu> wrote in message news:47E7F9C4.7060001@wustl.edu... > > > sky465nm@trline4.org wrote: >> Jon Elson <elson@pico-systems.com> wrote: >> >>>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese >>>seller, and am having problems with random failures at first power up. >>>Sometimes it is a stuck I/O pin, sometimes a failure to configure. I >>>first thought maybe we had an ESD problem, but I'm now thinking these may >>>be counterfeit. They have white ink printed labels on the front, whereas >>>other Xilinx chips have laser-etched labels. Also, these Spartan chips >>>don't have the Spartan logo just below the Xilinx logo, like my other >>>Xilinx chips. Anyone have any comments on this? >> >> >> Photo.. ? >> > OK, where should I put the photos? > > Jon I'm not touching that one... Bob >Article: 130443
Alex Freed wrote: > > It may be a bit off-topic, but could someone explain how exactly a few > extra volts can damage the GATE of a MOS transistor in the absence of > protection diodes? Most designs have protection diodes for each signal to ground and VDD. This limits the maximum voltage applied to the pad from -0.6V to VDD+0.6V. If the current is sufficient the voltage may go a little bit over VDD+0.6V. FPGA may not be protected like that check the datasheet. > I ASSume FPGAs use MOS technology. And the gates are insulated by the > oxide layer. And it takes a lot more than a few volts to cause a breakdown. With respect to VDD_CORE. As an approximation the breakdown voltage is 10*gate length (in um). Hence 130nm will operate at 1.3V. Be clever design and process you may get a little bit more possibly 1.5V. Beyond the design/process limit the device will fry itself. You may have a margin of 10%. The maxcimum safe voltage is usually in the datasheet as abcolute maximum voltage. Even this may cause damage if spplied for any length of time. So the datasheet gives a min and a max stick to it. Pad ring VDD may be higher. Possibly 3V or higher. They generally use a thicker gate oxide which will tolerate higher voltages. The datasheet will quote a min and max for this supply as well. Stick to it. > > -Alex. >Article: 130444
David Spencer wrote: > What I was trying to say (not very well!) is that if you are > going to try and limit voltage with a series resistor then you need first to > ensure that there is a high-side clamp diode. Obviously if there isn't, the > gate will see the full voltage and the input transistor may be compromised. > It may be a bit off-topic, but could someone explain how exactly a few extra volts can damage the GATE of a MOS transistor in the absence of protection diodes? I ASSume FPGAs use MOS technology. And the gates are insulated by the oxide layer. And it takes a lot more than a few volts to cause a breakdown. -Alex.Article: 130445
I wanted to perform a byte shifting of a 24bit vector . the resultant
vector is a 48 bit vector . the following is the functinality needed
signal BV : std_logic_vector(23 downto 0);
signal BYTE_SEL : std_logic_Vector(1 downto 0);
signal BVOUT : std_logic_Vector(47 downto 0);
method 1
BVOUT <= x"000000" & BV when BYTE_SEL = "00" else
x"0000" & BV & x"00" when BYTE_SEL ="01" else
x"00" & BV & x"0000" when BYTE_SEL ="10" else
BV & x"000000";
-------------------------------------------------------------------------------------
signal MUL : std_logic_vector(23 downto 0);
method 2
rom port map( addr => BYTE_SEL, qout => MUL)
BV_d1 <= BV after 1 clock cycle
MULTIPLY PORT MAP ( M1 => MUL, M2 => BV_d1 , clock => clock, BVOUT);
I would like to know if the above method 1 of the behavioural
statement is a good way of programming when I am implementing on the
FPGa or should I implement it using a ROM where I store a multiplier
constant and use the byte_sel as an address to select it and then
multiply with the pipelined BV to generate the output.
Or is there any other better way to implement it other than the above
two methods.
Thanks,
D
Article: 130446On Mar 24, 11:58=A0am, Jon Elson <el...@wustl.edu> wrote: > sky46...@trline4.org wrote: > > Jon Elson <el...@pico-systems.com> wrote: > > >>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese > >>seller, and am having problems with random failures at first > >>power up. =A0Sometimes it is a stuck I/O pin, sometimes a failure > >>to configure. =A0I first thought maybe we had an ESD problem, but > >>I'm now thinking these may be counterfeit. =A0They have white ink > >>printed labels on the front, whereas other Xilinx chips have > >>laser-etched labels. =A0Also, these Spartan chips don't have the > >>Spartan logo just below the Xilinx logo, like my other Xilinx > >>chips. =A0Anyone have any comments on this? > > > Photo.. ? > > OK, where should I put the photos? > > Jon You can send it to me,and I will pass it on. peter@xilinx.comArticle: 130447
On Mar 23, 1:39 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sun, 23 Mar 2008 06:41:39 -0700 (PDT), Dave Pollum wrote: > >> I uninstalled the video card and then re-installed the video card > >> software. When I ran Modelsim (stand alone), the fonts were correct. > >> But the second time I ran Modelsim, the fonts were huge again. As > >> before, the character fonts had large pixels. > >> -Dave Pollum > > >I've tried ISE WebPack 9.2x with ModelSim XE II starter 5.8c and that > >combo works. It still puzzles me that a newer version of ModelSim > >acts so oddly. > > The fact that you have blocky pixels strongly suggests that > it is NOT really a font choice issue, but instead something > arcane to do with video drivers - as you obviously suspected. > *Where* are the huge fonts appearing? Everywhere? Just in > the transcript? Does the rest of the display scale to match > the fonts? > > I've never seen anything like this. You can easily configure > ModelSim's font sizes, as I guess you're already aware. But > if you do so, and choose a huge font, it won't have big blocky > pixels - it will be rendered nice and smooth. > > Can you get to the window preferences menu and try to discover > what fonts ModelSim thinks it's using? > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I found that I had an older video card, but before I installed it I want to try uninstalling my ATI card again. This time I clicked on the box to show hidden items. An what do you know, there were some hidden ATI entries, so I got rid of those. Then I re-installed the ATI video card software, and everything works OK now, including ModelSim. Strange, huh? -Dave PollumArticle: 130448
On Mar 24, 2:15=A0pm, Alex Freed <al...@mirrow.com> wrote: > Andy Botterill wrote: > > Alex Freed wrote: > > >> It may be a bit off-topic, but could someone explain how exactly a few > >> extra volts can damage the GATE of a MOS transistor in the absence of > >> protection diodes? > > > Most designs have protection diodes for each signal to ground and VDD. > > This limits the maximum voltage applied to the pad from -0.6V to > > VDD+0.6V. If the current is sufficient the voltage may go a little bit > > over VDD+0.6V. > > I understand perfectly what happens WITH the protection diodes. That's > why my question includes "in the absence of the protection diodes" clause.= > > >> I ASSume FPGAs use MOS technology. And the gates are insulated by the > >> oxide layer. And it takes a lot more than a few volts to cause a > >> breakdown. > > With respect to VDD_CORE. As an approximation the breakdown voltage is > > 10*gate length (in um). Hence 130nm will operate at 1.3V. > > Could you be confusing the GATE BREAKDOWN voltage with some other > parameter? The GATE BREAKDOWN voltage should be a function of the SiO2 > layer thickness rather than the gate length. > > > Be clever > > design and process you may get a little bit more possibly 1.5V. Beyond > > the design/process limit the device will fry itself. You may have a > > margin of 10%. The maxcimum safe voltage is usually in the datasheet as > > abcolute maximum voltage. Even this may cause damage if spplied for any > > length of time. So the datasheet gives a min and a max stick to it. > > I do respect the data sheets, especially the "absolute maximum rating" > part :) So I fried my semiconductors by other methods... > > I'm just trying to understand the physics of the issue. > > -Alex. Alexx, the breakdown voltage is of course determined only by the gate oxide thickness, but for practical circuits, the thickness goes together with the gate length (not logically, but practically) When really thin oxide is 15 Angstroms =3D 1.5 nm "thick", then 3 V across it is equivalent to 2 billion volts per meter, or 2 million volts per mm. Would you want to touch a flimsy 1 mm glass plane when somebody puts 2 MV on the opposite side? I would hesitate... Peter AlfkeArticle: 130449
Andy Botterill wrote: > Alex Freed wrote: > >> >> It may be a bit off-topic, but could someone explain how exactly a few >> extra volts can damage the GATE of a MOS transistor in the absence of >> protection diodes? > > Most designs have protection diodes for each signal to ground and VDD. > This limits the maximum voltage applied to the pad from -0.6V to > VDD+0.6V. If the current is sufficient the voltage may go a little bit > over VDD+0.6V. I understand perfectly what happens WITH the protection diodes. That's why my question includes "in the absence of the protection diodes" clause. >> I ASSume FPGAs use MOS technology. And the gates are insulated by the >> oxide layer. And it takes a lot more than a few volts to cause a >> breakdown. > With respect to VDD_CORE. As an approximation the breakdown voltage is > 10*gate length (in um). Hence 130nm will operate at 1.3V. Could you be confusing the GATE BREAKDOWN voltage with some other parameter? The GATE BREAKDOWN voltage should be a function of the SiO2 layer thickness rather than the gate length. > Be clever > design and process you may get a little bit more possibly 1.5V. Beyond > the design/process limit the device will fry itself. You may have a > margin of 10%. The maxcimum safe voltage is usually in the datasheet as > abcolute maximum voltage. Even this may cause damage if spplied for any > length of time. So the datasheet gives a min and a max stick to it. I do respect the data sheets, especially the "absolute maximum rating" part :) So I fried my semiconductors by other methods... I'm just trying to understand the physics of the issue. -Alex.
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