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sky465nm@trline4.org wrote: > Well one option is to go FreeBSD/Linux. If I were the only one using that machine, that would be OK. But there's other people doing stuff on there, and they need Windoze for some reason. All I need to do on that particular machine is load an FPGA from time to time. Just load it... no synthesis, no nothing, just loading... > Or setup a jtag server on another machine. Another machine is always a solution, but not really an acceptable one. I don't want the lab clogged up with dozens of machines so everyone can load his/her board. That's how this is going to end sooner or later. I was thinking about trying out some Actel devices as well, and Altera is out there, too... :) > This seems like a problem that won't go away unless you create > something of your own. Or fake the system for the drivers (ie virtualisation). Virtualisation is probably what I'll end up doing. It's just so... stupid. Can't they all get along? :) > Ping Xilinx ..?, how are you going to make this work?, I don't find this an > acceptable situation. I heard from another user that Intel-cpu-jtag + > xilinx-jtag also fails on the same issues. Well, why should THEY care? Thou shalt not have any JTAG beside me. ;) > I don't know the status of libusb on win32. But my tip would be > to check: http://libusb-win32.sourceforge.net/ Hmm, didn't know that one... But doesn't look like anything that will be up and running faster than a virtual machine... > Btw,... google :p I've been googling and finding only more problems and no real solutions. So, obviously, the answer to my original question is an emphatic "No"... cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 130751
On Mar 30, 10:41 am, Alain <no_spa2...@yahoo.fr> wrote:
> At present, I'm just worry about LUT and FF increase after map : More
> Lut and FF (??? I've to investigate...) but more LUT used as Shift
> registers and less slices occupied.
You know, I hadn't noticed that, but I am seeing a fairly large
'inflation' of the design as well.
Here is the final utilization report from XST
9.2.04
------
Device utilization summary:
---------------------------
Selected Device : 2vp100ff1704-5
Number of Slices: 34416 out of 44096 78%
Number of Slice Flip Flops: 48682 out of 88192 55%
Number of 4 input LUTs: 55604 out of 88192 63%
Number used as logic: 29643
Number used as Shift registers: 25229
Number used as RAMs: 732
Number of IOs: 61
Number of bonded IOBs: 61 out of 1040 5%
IOB Flip Flops: 36
Number of BRAMs: 39 out of 444 8%
Number of MULT18X18s: 324 out of 444 72%
Number of GCLKs: 1 out of 16 6%
Number of DCMs: 1 out of 12 8%
10.1.0
------
Device utilization summary:
---------------------------
Selected Device : 2vp100ff1704-5
Number of Slices: 34881 out of 44096 79%
Number of Slice Flip Flops: 53619 out of 88192 60%
Number of 4 input LUTs: 54316 out of 88192 61%
Number used as logic: 29631
Number used as Shift registers: 23953
Number used as RAMs: 732
Number of IOs: 61
Number of bonded IOBs: 61 out of 1040 5%
IOB Flip Flops: 36
Number of BRAMs: 39 out of 444 8%
Number of MULT18X18s: 324 out of 444 72%
Number of GCLKs: 1 out of 16 6%
Number of DCMs: 1 out of 12 8%
Not much difference - 10.1 is a little larger, but not much.
Here are the usage summaries from the top of the PAR file
9.2.04
------
Number of MULT18X18s 324 out of 444 72%
Number of RAMB16s 44 out of 444 9%
Number of SLICEs 37241 out of 44096 84%
10.1.0
------
Number of MULT18X18s 324 out of 444 72%
Number of RAMB16s 44 out of 444 9%
Number of SLICEs 40732 out of 44096 92%
Wow - looks like MAP really flubbed it - almost 8% growth from 9.2.04
to 10.1.0.
And here are the final lines of the place & route status:
9.2.04
------
Phase 6: 45317 unrouted; (0) REAL time: 1 hrs 19 mins 41 secs
Intermediate status: 37260 unrouted; REAL time: 1 hrs 52 mins
45 secs
Phase 7: 0 unrouted; (0) REAL time: 2 hrs 1 mins 33 secs
Phase 8: 0 unrouted; (0) REAL time: 2 hrs 3 mins 42 secs
10.1.0
------
Phase 6: 57617 unrouted; (693) REAL time: 6 hrs 16 mins 47 secs
Intermediate status: 45825 unrouted; REAL time: 6 hrs 55 mins
31 secs
Phase 7: 0 unrouted; (1443123) REAL time: 7 hrs 16 mins 57 secs
Phase 8: 0 unrouted; (1443123) REAL time: 7 hrs 18 mins 53 secs
Phase 9: 0 unrouted; (1433735) REAL time: 7 hrs 19 mins 10 secs
PAR was _not_ happy. Took amost 4x longer to run. This is with the
exact same source & control files.
A little something for the developers to chew on.
Eric
Article: 130752On Mar 31, 2:04 pm, Sunn <sun...@gmail.com> wrote: > Hi, please forgive me for any ignorance in this question, but I am > really lost. > > I have tried to get Xilinx ISE Webpack 9.2i to work with modelsim. But > it just doesn't seem to work. > > Now I am not very familiar with these programs, I am using them > because I am doing a school course that uses FPGA and they use Xilinx > and Modelsim... I have used them in the labs, but here I am just > having trouble to install them. > > I am able to installed Xilinx ISE Webpack 9.2i, but I cannot find > Modelsim in it, so I googled for Modelsim, installed it, but it > doesn't do anything. > > I just don't know what's going on or where should I look at... I just > want to install the programs!! > > Does anyone have any guides on how to get it install and running on > Linux? (Kernel 2.6) > > Thanks. Hi, I did not see you write that you had "purchased a license for ModelSim". I would not expect ModelSim to do anything until it can find a valid license. Whoever you buy the license from should be able to help you get things going. May I recommend that you purchase the Xilinx version (ModelsimXE), as it comes pre-configured to run inside ISE. G.Article: 130753
Sean Durkin <news_mar08@tuxroot.de> wrote: >sky465nm@trline4.org wrote: >> Well one option is to go FreeBSD/Linux. >If I were the only one using that machine, that would be OK. But there's >other people doing stuff on there, and they need Windoze for some >reason. All I need to do on that particular machine is load an FPGA from >time to time. Just load it... no synthesis, no nothing, just loading... But things ain't working so either you (a) have a machine #2 that runs another ms-win that can do jtag (b) have a machine #2 that runs BSD/Linux and can load any jtag. >> Or setup a jtag server on another machine. >Another machine is always a solution, but not really an acceptable one. >I don't want the lab clogged up with dozens of machines so everyone can >load his/her board. That's how this is going to end sooner or later. I >was thinking about trying out some Actel devices as well, and Altera is >out there, too... :) You can dedicate a 30 USD laptop to control jtag devices. Small and neat.. On ms-win you need to re-install and have a new machine. On unix you need another process.. add the bonus of smooth remote control. >> This seems like a problem that won't go away unless you create >> something of your own. Or fake the system for the drivers (ie virtualisation). >Virtualisation is probably what I'll end up doing. It's just so... stupid. >Can't they all get along? :) The larger organisation, the higher, and especielly the more money. The more sandbox turf stuff you will see :) >> Ping Xilinx ..?, how are you going to make this work?, I don't find this an >> acceptable situation. I heard from another user that Intel-cpu-jtag + >> xilinx-jtag also fails on the same issues. >Well, why should THEY care? Thou shalt not have any JTAG beside me. ;) Large corporation callsign? :-) >> I don't know the status of libusb on win32. But my tip would be >> to check: http://libusb-win32.sourceforge.net/ >Hmm, didn't know that one... But doesn't look like anything that will >be up and running faster than a virtual machine... Give it a try?, you need ofcourse the source for a loader. Anyway maybe you can make something with a plain C compiler?Article: 130754
Sean Durkin wrote:
> Another machine is always a solution, but not really an acceptable one.
> I don't want the lab clogged up with dozens of machines so everyone can
> load his/her board. That's how this is going to end sooner or later.
Languishing in my yet-to-be-started home projects pile is the
following scheme for a small, low budget, networked FPGA downloader :
- reflash a Linksys NSLU2 [1] ( ~$85 USD ) to run Linux [2]
- add a cheap USB cable
- re-compile x3sprog|xilprg|???? for the ARM target
- plunk one down next to the target HW, telnet in to download
Brian
[1] Linksys NSLU2
http://en.wikipedia.org/wiki/NSLU2
[2] NSLU2 Linux & NetBSD ports
http://www.nslu2-linux.org
http://www.netbsd.org/ports/evbarm/faq.html
Article: 130755On Mar 28, 6:47 am, Rube Bumpkin <Some...@somewhere.world> wrote: > water9...@yahoo.com wrote: > > On Mar 27, 6:23 am, Rube Bumpkin <Some...@somewhere.world> wrote: > >> water9...@yahoo.com wrote: > >>> On Mar 25, 1:17 pm, John_H <newsgr...@johnhandwork.com> wrote: > >>>> water9...@yahoo.com wrote: > >>>>> no reply? > >>>>> water9...@yahoo.com wrote: > >>>>>> The Linux lspci -xxx command can show my PCIE device header > >>>>>> space(0x00~0xFF). However,simultaneity,the Correctable Error and > >>>>>> Unsupported Request error from PCIE Capabilities device status > >>>>>> register are set. > >>>>>> I run the PCI Express Configuration Testing program from PCISIG to > >>>>>> test configure space.The system is halt after click run all test.Reset > >>>>>> PC and report NMI error. > >>>>>> why? > >>>>>> My configuration: PCIEx1, 16bit customize GTP wrapper same as Endpoint > >>>>>> x1 IP. > >>>> Do you see anything unusual from your PCI Express protocol analyzer? > >>> No,i didn't use any protocol analyzer. Only PCISIG Configuration > >>> Testing program > >> If this is your first PCI Express design, you need to think about > >> getting some tools. PCI-SIG recommends a scope with at least 6GHz of > >> bandwidth. There are a couple of different companies that have PCIE > >> analyzer solutions. You need to buy, rent, or borrow one. > > >> I've run compliance testing in the Gold suite at PCI-SIG workshops. It > >> takes me just a couple of minutes to identify the folks that designed > >> and built a device without having the right tools. There's a real > >> surprised look on their face when they see the waveforms. Sometimes we > >> spend the entire scheduled testing period just debugging their design, > >> electrically. > > >> If your device is failing the Config Test program, you may need to write > >> some low-level code to generate some simple cycles. You'll want to start > >> with a single Cfg Read, Type 0 of Register 0, and look at the results. > >> Follow that up with more reads and writes, stepping through the > >> enumeration process. If you don't want to do that, the same companies > >> that make analyzers make exercisers that can generate the necessary > >> cycles and show you the result of the completions. > > >> Good luck... > > >> RB > > > but,i use a simple tool of windows ,eg:Pcitree. it can read out my > > PCIE device header content. > > > why ompliance testing prgrame not? > > Yes, but PCITree can't tell you why the values that you are reading are > wrong. Is it an electrical problem, or a protocol problem? > > RB but,the all values read out by Pcitree sw are correct. why PCI Express Configuration Testing program is halt?Article: 130756
ghelbig@lycos.com wrote: > > May I recommend that you purchase the Xilinx version (ModelsimXE), as > it comes pre-configured to run inside ISE. Note that there is also modelsimXSE which is free and might be good enough for small designs. -JeffArticle: 130757
On Mar 31, 2:08 pm, "pillar2...@gmail.com" <pillar2...@gmail.com> wrote: > > When you say "start up webpack", do you mean the ISE gui? > > Yes > > > I've not > > used it, but I did note that the settings.sh is now settings32.sh and > > is located under the ISE/ directory. > > I am already aware of those files. These files do not invoke the > gui. In version 9.2i there was an executable called ise which would > invoke the program/gui. I still have not figured out where this file > (I have even looked for anything that would be renamed etc) is. > > Newell For me it's /opt/xilinx10.1/ISE/bin/lin/ise, which is placed on my path (so you can invoke it with "ise") when you source the above files. Does it not exist in your install?Article: 130758
On 1 Apr., 00:14, emeb <ebromba...@gmail.com> wrote: > > 9.2.04 > ------ > Number of MULT18X18s 324 out of 444 72% > Number of RAMB16s 44 out of 444 9% > Number of SLICEs 37241 out of 44096 84% > > 10.1.0 > ------ > Number of MULT18X18s 324 out of 444 72% > Number of RAMB16s 44 out of 444 9% > Number of SLICEs 40732 out of 44096 92% > > Wow - looks like MAP really flubbed it - almost 8% growth from 9.2.04 > to 10.1.0. To the contrary. Look again at the same report: 9.2.4 Number of 4 input LUTs: 55604 out of 88192 63% 10.1.0 Number of 4 input LUTs: 54316 out of 88192 61% Actually there is a 2.3% reduction in area. The number of slices is meaningless, it only tells you the LUTs are distributed. You might as well say you had 100% utilization because all four quadrants of the chips are used. Any Slice with less than the maximum number of LUTs used still has space for more logic that can and will be used by the tools. Always report LUT and DFF numbers and ignore the Slices. Kolja SulimmaArticle: 130759
Hi *, I am driving a bunch of DACs each having its own SPI bus with a Virtex4 FPGA. The test design is up and running fine (generating a sine output via an DDC generator implemented on the fabric). Now I want to make sure it still works fine after the FPGA is stuffed with more control logic. The DACs have both setup and hold time requirements for the serial data input (SDI) vs. the serial clock (SCK). My .ucf file should tell par the following constraint: For i in 1 .. 15: sdi<i> must be valid 5 ns before the rising edge on sck<i> and stay valid for 15 ns I tried the following constraint: NET "dac8811_sdi<1>" OFFSET = OUT 5 ns VALID 15 ns BEFORE "dac8811_clk<1>" HIGH; ISE report these errors: Checking timing specifications ... ERROR:XdmHelpers:865 - For OFFSET specification "OFFSET=OUT 5000 pS VALID 15000 pS BEFORE dac8811_clk<1> HIGH" on net "dac8811_sdi<1>", the given clock net "dac8811_clk<1>" is a device output. The OFFSET must reference a clock input net. Great - but how do I work with clocks generated inside the FPGA? The sck signal is generated from an 100 MHz quartz using a digital clock manager (DCM_ADV) of the Virtex. ERROR:XdmHelpers:874 - OFFSET specification "OFFSET=OUT 5000 pS VALID 15000 pS BEFORE dac8811_clk<1> HIGH" on net "dac8811_sdi<1>" has a VALID duration. The VALID clause is not supported on OUT-type OFFSET specifications. So I can't model a hold time requirement of an external component? Any hints appreciated. Unfortunately, the documentation of ISE is not that helpful how something like this is modeled correctly. I am thinking about using the OFFSET AFTER constraint (the data is written on the falling edge anyway) but I had hoped that the timing analyzer will protect against the wrong frequency on the output clock as well. Greetings, TorstenArticle: 130760
On Mar 31, 3:21=A0pm, kislo <kisl...@student.sdu.dk> wrote: > On 31 Mar., 14:55, morphiend <morphi...@gmail.com> wrote: > > > On Mar 31, 8:23 am, kislo <kisl...@student.sdu.dk> wrote: > > > > hi, is it possible to increase the available memory for a microblaze > > > after it has been created ? .. i have created a microblaze with 16kb > > > blockram using the base system builder, but now i want to use 32kb .. > > > can this be changed? > > > Yes, you can either edit the MHS file and change the HIGHADDR of the > > memory controller, or you can edit it from the Address view in XPS. > > will this also make xps initialize more bram? if i for instance build > a system with 16kb block ram it automaticaly assigns 32K for > dlmb_cntlr, but that dosent mean it has 32K of blockram .. if i use > more that 16K for application code the compiler complains.. That is exactly what it will do. When you change the HIGHADDR (or memory size in XPS address view) you will get 32K of BRAM for program storage. Of course this needs additional 8 BRAMs. Cheers GuruArticle: 130761
On Apr 1, 10:36 am, Torsten Landschoff <t.landsch...@gmx.de> wrote: > Hi *, > > I am driving a bunch of DACs each having its own SPI bus with a > Virtex4 FPGA. The test design is up and running fine (generating a > sine output via an DDC generator implemented on the fabric). > > Now I want to make sure it still works fine after the FPGA is stuffed > with more control logic. The DACs have both setup and hold time > requirements for the serial data input (SDI) vs. the serial clock > (SCK). > > My .ucf file should tell par the following constraint: > > For i in 1 .. 15: sdi<i> must be valid 5 ns before the rising edge on > sck<i> and stay valid for 15 ns > > I tried the following constraint: > > NET "dac8811_sdi<1>" OFFSET = OUT 5 ns VALID 15 ns BEFORE > "dac8811_clk<1>" HIGH; > > ISE report these errors: > > Checking timing specifications ... > ERROR:XdmHelpers:865 - For OFFSET specification "OFFSET=OUT 5000 pS > VALID 15000 > pS BEFORE dac8811_clk<1> HIGH" on net "dac8811_sdi<1>", the given > clock net > "dac8811_clk<1>" is a device output. The OFFSET must reference a > clock input > net. > > Great - but how do I work with clocks generated inside the FPGA? The > sck signal is generated from an 100 MHz quartz using a digital clock > manager (DCM_ADV) of the Virtex. > > ERROR:XdmHelpers:874 - OFFSET specification "OFFSET=OUT 5000 pS VALID > 15000 pS > BEFORE dac8811_clk<1> HIGH" on net "dac8811_sdi<1>" has a VALID > duration. The > VALID clause is not supported on OUT-type OFFSET specifications. > > So I can't model a hold time requirement of an external component? > > Any hints appreciated. Unfortunately, the documentation of ISE is not > that helpful how something like this is modeled correctly. I am > thinking about using the OFFSET AFTER constraint (the data is written > on the falling edge anyway) but I had hoped that the timing analyzer > will protect against the wrong frequency on the output clock as well. > > Greetings, Torsten The best you can do is to make sure to use the flip-flops in the IO Block (FFs in the PADs) for the last register used for each output. Why it is the best: Because you do not need to play with constraint file. FFs in PAD to PAD timing are fix and well specified by FPGA Vendor. Laurent http://www.amontec.comArticle: 130762
Kolja Sulimma wrote: > On 1 Apr., 00:14, emeb <ebromba...@gmail.com> wrote: > >>9.2.04 >>------ >> Number of MULT18X18s 324 out of 444 72% >> Number of RAMB16s 44 out of 444 9% >> Number of SLICEs 37241 out of 44096 84% >> >>10.1.0 >>------ >> Number of MULT18X18s 324 out of 444 72% >> Number of RAMB16s 44 out of 444 9% >> Number of SLICEs 40732 out of 44096 92% >> >>Wow - looks like MAP really flubbed it - almost 8% growth from 9.2.04 >>to 10.1.0. > > > To the contrary. Look again at the same report: > > 9.2.4 > Number of 4 input LUTs: 55604 out of 88192 63% > > 10.1.0 > Number of 4 input LUTs: 54316 out of 88192 61% > > Actually there is a 2.3% reduction in area. > The number of slices is meaningless, it only tells you the LUTs are > distributed. > You might as well say you had 100% utilization because all four > quadrants of the chips > are used. > > Any Slice with less than the maximum number of LUTs used still has > space for more logic > that can and will be used by the tools. > > Always report LUT and DFF numbers and ignore the Slices. On that subject, any idea why the FlipFlop count went UP 5%, when the LUT count went down 2% - and why the tools decided to do that with the same param settings ? A change that large is not good to see on a 'signed off' design.... 9.2.04 ------ Number of Slice Flip Flops: 48682 out of 88192 55% Number of 4 input LUTs: 55604 out of 88192 63% 10.1.0 ------ Number of Slice Flip Flops: 53619 out of 88192 60% Number of 4 input LUTs: 54316 out of 88192 61% -jgArticle: 130763
On 1 Apr., 11:08, j...@amontec.com wrote: > The best you can do is to make sure to use the flip-flops in the IO > Block (FFs in the PADs) for the last register used for each output. > > Why it is the best: Because you do not need to play with constraint > file. FFs in PAD to PAD timing are fix and well specified by FPGA > Vendor. True, but changing the device will change the implicit timing constraints that I set by putting the FFs there. I would like to define the requirements explicitly. Also, while the time from the FF to the pad is well defined, I can't be sure how the routing delay from the DCM-generated clock to the pad will be. Thanks, TorstenArticle: 130764
On 1 Apr., 11:50, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > On that subject, any idea why the FlipFlop count went UP 5%, > when the LUT count went down 2% > - and why the tools decided to do that with the same > param settings ? It is a new tool, so it uses different algorithms. Pretty much all problems solved in the tool chain (exept for retiming and mapping) are NP-complete, so approximation algorithms are used. There is no formal specification of the result returned by the tool, it just promises to search for a solution that is good relative to some cost function. I would expect the tool manufacturer to keep the cost function stable for unchanged settings, but not the algorithms. Beside changes in the search strategy the difference might as well be very early in the tool chain. For example at some point (Version 8.1?) ISE synthesis started to honor inital values in VHDL and use them as register reset values. Changed initial values can have a major impact on which retiming steps are legal. In extreme cases a single bit with changed reset value can have an arbitrarily large impact on the clock frequency achieved by retiming. And retiming is a problem where the optimum result is returned. No random search or similar. Therefore you should always expect different results from new version of the tools. You should expect better results on average, but not better results for every single design. That is impossible in EDA. Kolja SulimmaArticle: 130765
Antti wrote: > hm chain aint completly broken, weird > well i have seen wrong jtag id been returned, it was digged down to > have excessive 100mhz noise on VCCINT Looks like I've got a similar problem. After removing the oscillator module the JTAG identification works fine. Thanks for the pointer AndyArticle: 130766
>hm chain aint completly broken, weird >well i have seen wrong jtag id been returned, it was digged down to >have excessive 100mhz noise on VCCINT How did you resolve the 100mhz noise source problem..?Article: 130767
On 1 Apr., 13:17, sky46...@trline4.org wrote: > >hm chain aint completly broken, weird > >well i have seen wrong jtag id been returned, it was digged down to > >have excessive 100mhz noise on VCCINT > > How did you resolve the 100mhz noise source problem..? removing the 100mhz oscillator :) that PCB proto was SO BAD that no powersupply bypassing helped.. i tried and looked with the scope BTW it was weird, i was also using lab power supply, so while sweeping the VCC i could see the JTAG ID to change from virtex to spartan and then failing completly AnttiArticle: 130768
On Mon, 31 Mar 2008 23:33:02 -0400, Jeff Cunningham <jcc@sover.net> wrote: >ghelbig@lycos.com wrote: > >> >> May I recommend that you purchase the Xilinx version (ModelsimXE), as >> it comes pre-configured to run inside ISE. > >Note that there is also modelsimXSE which is free and might be good >enough for small designs. >-Jeff Neither of which works under Linux, as far as I know. The OP probably has to install Windows as a first step, or find the price of Modelsim SE (or possibly LE, which is crippled to only handle Verilog) - BrianArticle: 130769
I've read all the posts here but have lost track of how you're getting on. Can you post an update and describe what the problem turned out to be? Nial.Article: 130770
On 1 Apr., 10:36, Torsten Landschoff <t.landsch...@gmx.de> wrote:
> My .ucf file should tell par the following constraint:
>
> For i in 1 .. 15: sdi<i> must be valid 5 ns before the rising edge on
> sck<i> and stay valid for 15 ns
Okay, I am getting better. I now have this constraint for the SDI
(serial data in) of the DAC:
TIMESPEC TS_DAC8811_SDI = FROM "FFS" TO PADS("dac8811_sdi<*>") 5 ns;
This would do fine, as the serial clock is running with 50 MHz and I
drive the pad on the falling edge. Therefore, if the pad finishes the
transition after 0 ns to 5 ns in relation to the clock output, all is
fine: Even if the transition takes 5 ns, the setup time will be
reached, and if it is instantly, the hold time is still okay as it
allows changing the data together the the falling clock.
Now, this constraint is a bit too tight, as the clock output will also
take a bit to change. Any way to model that in ucf?
Thanks, Torsten
Article: 130771On Mar 28, 4:31 pm, "Ron N." <rhnlo...@yahoo.com> wrote: > On Mar 28, 10:20 am, moja...@mojaveg.IWVISP.com (Everett M. Greene) > wrote: > > > > > David Brown <da...@westcontrol.removethisbit.com> writes: > > > >> The key is, > > > >> "Can you write code to do +,~, |,>>,conditional branch on > > > >> z or carry" > > > > > You need XOR for add/subtract so it can be one of the > > > > operations at little extra cost. Some sort of CALL > > > > and RETURN is needed for the processor to be useful. > > > > AND is needed as well. > > > > (a & b) == ~(~a | ~b) > > > (a ^ b) == (a | b) & ~(a & b) > > > > Thus you don't need AND or XOR. Similarly, you subtraction. > > > But you haven't produced addition/subtraction yet. The first > > term of adders/subtractors is a ^ b. If you gate that output > > to rest of the world, you have XOR with no further fuss. > > NOT is available via a ^ 1s. > > You can produce any arithmetical or logical operation out > of just NAND gates (or just NOR gates as was actually done > in some ECL supercomputer implementations), and the same > can be done in software, if efficiency is of no importance. Actually, it is not that you *can* produce all logic from NAND gates, in effect that is how it *is* done. The basic logic element consists of transistors configured to be a NAND gate, an inverter (a degenerate form of a NAND gate), a NOR gate (a NAND gate with inverted logic) and transmission gates. So inside of a chip designed at the gate level, there really is no distinction between NAND and NOR gates and there are no OR and AND gates. Implementations like the Cray computer that used ECL NAND gates did so because of the limitations of ECL packaging at that time. The real difficulty in designing that super computer had to do with packaging and heat dissipation. So Cray attacked those problems first and fit the logic design into those constraints. A regular array of ECL DIPS on common sized circuit boards fit the thermal design well and the only variation needed was the circuit board routing.Article: 130772
On Mar 31, 4:04 pm, Sunn <sun...@gmail.com> wrote: > Hi, please forgive me for any ignorance in this question, but I am > really lost. > > I have tried to get Xilinx ISE Webpack 9.2i to work with modelsim. But > it just doesn't seem to work. > > Now I am not very familiar with these programs, I am using them > because I am doing a school course that uses FPGA and they use Xilinx > and Modelsim... I have used them in the labs, but here I am just > having trouble to install them. > > I am able to installed Xilinx ISE Webpack 9.2i, but I cannot find > Modelsim in it, so I googled for Modelsim, installed it, but it > doesn't do anything. > > I just don't know what's going on or where should I look at... I just > want to install the programs!! > > Does anyone have any guides on how to get it install and running on > Linux? (Kernel 2.6) > > Thanks. I know that Xilinx works with universities to supply boards, chips, and software at very low costs to students (speak up Austen). Perhaps Modeltech (Modelsim) has a similar program. Have you talked to your prof about this? And even for us non-students, there is a free, but limited, version of Modelsim that is available from the Xilinx website. HTH -Dave PollumArticle: 130773
Andrew Greensted wrote: > Looks like I've got a similar problem. After removing the oscillator > module the JTAG identification works fine. I've dropped in a lower frequency oscillator module, that seems to have improved things. It's not a massive problem, I'll just use a DCM to multiply things up. I'm guessing the oscillator was causing noise on VCCO. However, isn't the JTAG TAP and IO powered by VCCAUX? AndyArticle: 130774
Andrew I would be interested to know if now that JTAG works you hit the same "feature" that we did recently (otherwise we have a hidden design bug). If you power up and program any device using JTAG it completes programming, releases DONE but sees that DONE is still held by the other three FPGAs and decides that it has failed and IMPACT returns failed. We have to try to program all the devices which will all fail except the last one which releases DONE and sees it high and so passes. The other three then need programming again which will pass as done is high. Colin
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