Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On May 5, 2:48 pm, Martin Darwin <martin.darwin.nos...@alcatel- lucent.com> wrote: > > I have used XAPP058 to get a working setup. The only thing I struggled > with was getting the DONE pin to go high. Yes, this is exactly my problem! > I belive the code has two > options for the "RUNTEST" SVF instruction (or something like that): one > is a delay loop and the other puts out clocks. Make sure you pick the > code that puts out the clocks. The delay loop won't work. This was for a > Spartan3A FPGA. Okay, but I don't know how to do this. Where do I "pick the code" that you refer to? I've poked around all the options for the "Generate Programming File" process, but nothing seems to work, nor does anything seem to be what you're talking about. It certainly sounds like you have a great lead, but I don't even know how to follow it! Can you describe or point me to how exactly do I do this? I haven't run across it.. Thanks, Martin, -BobArticle: 131876
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:fvo2o9$p0m1@cnn.xsj.xilinx.com... > KJ wrote: >> On May 5, 12:13 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> >> wrote: >>>> You'll also find that changes (like switching the Nobl SRAM to DRAM as >>>> an >>>> example) can be accomodated without having to change *everything*. > ... >> Designing a request/acknowledge interface to some other process or >> entity (in this case the 'other' being a DRAM controller) results in a >> much easier to maintain design. >> >> Using the exact same interface signal functionality whether one is >> talking to internal FPGA memory, NoBL or SDRAM or SPI results in a >> design that can be reused, retargeted and improved upon if necessary. > ... >> Kevin Jennings > > This is a great example, because switching from one type of RAM to another > means you *do* have to change everything, if you want the controller to be > good. The methodology I use makes use of every clock cycle, DRAMs are running full tilt, transfers from fast FPGA through a PCI bus to some other processor, etc., the whole 9 yards. > You can certainly modularlize the code and make concurrent SMs with > handshaking and this is easy to maintain. And a lot of DRAM controllers > are designed this way. But here is the problem: while you are waiting > around for acknowledges, you have just wasted a bunch of memory bandwidth. Then you're waiting for the wrong acknowledgement. Taking the DRAM again as an example, every data transfer consists of two parts: address/command and data. During a memory write, all of this happens on the same clock cycle. When the controller 'fills up' it sets the wait request to hold off until it can accept more commands (reads or writes). During a read though, the address/command portion happens on one clock cycle, the actual delivery of the data back to the requestor occurs sometime later. The state machine that requests the read does not necessarily have to wait for the data to come back before starting up the next read. The acknowledge that comes back from a 'memory read' command is that the request to read has been accepted, another command (read or write) can now be started. There are also situations where one really does need to wait until the data is returned to continue on, but in many data processing applications, the data can lag significantly with no real impact on performance, the read requests can be queued up as fast as the controller can accept them. Although I've been using the DRAM as an example, nothing in the handshaking or methodology is 'DRAM specific', it is simply having to do with transmitting information (i.e. writing) and requesting information (i.e. reading) and having a protocol that separates the request for information from the delivery of that information (i.e. specifically allowing for latency and allowing multiple commands to be queued up). > If you want to make better use of your bandwidth, you can't use > handshaking. I disagree. > You have to start another burst while one is in the pipe. That's correct...but you can't start one if the pipe is full (which can happen when a memory refresh or a page hit occurs and the pipe fills up waiting while those things get serviced). The handshake tells you that the pipe is full and you absolutely need to have it. The 'pipe full' signal is a handshake, when it is full, it says 'wait', when it is not full, it says 'got it'. > You have to look ahead in the command FIFO to see if the next request is > going to be in the same row/bank to see if you need to close the row > during this burst and precharge or if you can continue in the same open > row in a different bank, etc. OK > If I do all that with handshaking, I'm frittering away cycles. Then you're not doing it properly. It's called pipelining, not frittering. > And to do this in a way that doesn't fritter away cycles with standard > methodology means everything is so tightly bound together that to change > from SDRAM to some other type of RAM means I have to tear up most of the > design. > Latency can matter in certain situations, in others it doesn't. If there is some situation where latency mattered, one would have to come up with a way where the requestor could start up the read cycle earlier...but if there is such a way to start it up earlier, then that change could be applied equally well to the lower latency situation as well which means that you could have a common design Kevin JenningsArticle: 131877
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:fvo47b$on52@cnn.xsj.xilinx.com... > KJ wrote: >> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message >> news:fvfm29$on81@cnn.xsj.xilinx.com... >>> KJ wrote: >>>> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message >>>> news:fv7i38$69n6@cnn.xsj.xilinx.com... >>>>> My question: what is the cleanest way to describe an FSM requiring >> >> Well, just the fact that you're time sharing the DSP48 means that you're >> not processing something new on every clock cycle which just screams out >> to me that you'd want to implement this with a request/acknowledge type >> of framework. ... >> >> Kevin Jennings > But I *do* have to process something on every cycle. You're not able to process a new set of 'a', 'b', 'c' and 'd' on every clock cycle since the DSP48 is time shared (by your choice) and that was my point. Time multiplexing the DSP48 to keep *it* busy on every clock cycle is not the same thing. > Consider that I have to process these two equations: > > y0 <= (a0*b0+c0)*d0; > y1 <= (a1*b1+c1); > > Now, if you look at the structure of the DSP48, you can see that I can't > even process these two sequentially. I can send off (a0*b0+c0)*d0 to the > black box thingy you speak of, but this can't be processed without dead > cycles: I have to get the result of (a0*b0+c0) before I multiply it with > d0, and if the DSP48 is fully pipelined, that means that the multiplier is > unused for three cycles. That's only true if the addition can't be done combinatorially. If it can then the calculation of 'y0' takes two clock cycles and the DSP48 is fully utilized. The answer pops out after two clock cycles of latency, the DSP48 hums along doing something useful on every tick. > It's similar to a superscalar process with dependencies. So I have to > reschedule: I put (a0*b0+c0) into the pipe, then put in (a1*b1+c1) (which > has no dependency on what is in the pipe), and then when the result of > (a0*b0+c0) pops out I can feed it back into the DSP48 and multiply it with > d0 to get y0. In the meantime y1 pops out. Without this intermixed > scheduling I end up with too many dead cycles and then I need to use too > many DSP48s. > And depending on just what the bottlenecks in the design are, one can do all kinds of things. But no matter what, you still need to interface *to* that thing, no matter what it does and no matter how wide of an input vector it takes (i.e. a0, b0, c0, d0, a1, b1, c1...if that's what it takes). In other words, a0, b0, c0, d0, a1, b1 and c1 all need to get in somehow; y0 and y1 both need to make it out and you need to flag when they are valid and that flagging is functionally the same thing as handshaking. Kevin JenningsArticle: 131878
Someone asked about state machines using encoding similar to one-hot but with "forking" where multiple states make be active simultaneously, and I wrote: > DEC used that style of design in the PDP-16 Register Transfer Modules. > Possibly also in the control units of some of their asynchronous > processors such as the PDP-6 and KA10. Kevin Neilson wrote: > That's interesting--I'm not even familiar with an "asynchronous > processor". What does that mean? -Kevin There's no central clock. At any given time, one particular "unit" in the computer is active. When it completes its work, it sends a pulse to the next unit that needs to do something, thus handing off control. In some situations, a unit might trigger two other units. Usually in such a case, a later unit implements a "join" between the two paths, by waiting for both to complete. The logic implementing such a control system looks just like a flowchart. There were quite a few asynchronous computers in the old days, but the world settled on synchronous designs for various reasons. In recent years there has been a resurgence of interest in asynchronous designs, partly due to the possibility of power savings. There are still no mainstream asynchronous processors, though.Article: 131879
I'm looking for an individual with FPGA/CPLD hardware and software skills to develop prototype of a consumer device. Chicago area preferred. cjt101 at yahoo.comArticle: 131880
On 3 Maj, 12:32, Mike Treseler <mike_trese...@comcast.net> wrote: > 0xdeadbeef wrote: > > Hi all. I'm brand new in fpga subject so please be patient :P > > My problem is about to use stimulatorin waveform. > > Well, exactly- there is no such thing as stimulator as it was in ahdl > > 7.1. > > How to add it then ? > > Choose a language, vhdl or verilog.Aldecis a simulator that can use either. > Write some synthesis code. > Write a testbench. > > -- Mike Treseler Mike, in waveform there is no "stimulator" label. I just wanted to know if there is possibility to add there stimulators ? Even if i wrote testbech, there is no such thing as "stimulator" labels, as it was in previous versions. GreetingsArticle: 131881
Hi,
Easiest way to find out what is happening is to disassemble the program.
Just do a "mb_objdump -S" on the .elf file.
Göran
<chrisdekoh@gmail.com> wrote in message
news:6a6c57ff-bc59-4477-83e3-c85ac0e6664d@a9g2000prl.googlegroups.com...
> Hi Goran,
> The FSL_Full Flag is not asserted. Also, the microblaze came out of
> reset. I know cos I probed the addr and data bus signals and there is
> information on the bus in the modelsim simulator, wrt to when the
> microblaze is not out of reset.
>
> anyway, i found something else. This was what I wrote in my
> firmware code running on microblaze:
>
> #include "float.h"
> #include "mb_interface.h"
>
>
> typdef unsigned long long uint_64; //64 bits wide
> typedef union {
> uint_64 long_t;
> double double_t;
> } Union_double_t;
>
>
>
> int main(){
> Union_double_t a;
> Xuint32 temp;
> a= 3.0;
>
> //extract the lower word to put into the peripheral
>
> temp = (Xuint32) a.long_t & 0xffffffff;
> microblaze_bwrite_fsl(temp,0);
> //extract the upper word to put into the peripheral
> temp = ((Xuint32) a.long_t >>32) | 0xffffffff;
> microblaze_bwrite_fsl(temp,0);
> return 1;
> }
>
> the code above does not work. In short, when i try to send a double
> precision word onto the FSL bus like the manner described above by
> breaking it into the lower word and the upper word, it fails to work.
>
> However, for a single precision word sent in exactly the same way, it
> works just fine.
>
> any idea? :)
> Chris
>
Article: 131882Hi, This is my first time install Xilinx ISE in CentOS, I thought it's the free clone of RHEL. But I cannot find the ISE in the application menu list. I don't mean I have to have it, but just don't know if it's the default like that. I don't know if it's showing in the RHEL or your CentOS. I am pleased to see how close the CentOS to RHEL. Thank you for your time and reply. SimonArticle: 131883
Hello, I am trying to design a 4-tap FIR filter using system generator for Spartan3 xc3s200-4ft256. But when I try to generate the netlist from Matlab, I get the following error: >> standard exception: XNetlistEngine: An exception was raised: com.xilinx.sysgen.netlist.NetlistInternal: ERROR:sim:160 - Could not find requested IP (Multiplier,9.0) for currently at C:/MATLAB2006a/toolbox/xilinx/sysgen/scripts/SgGenerateCores.pm line 611. >> I get this error only for one particular installation but works fine on other machines. Can anyone suggest where is the problem? (There is no design issues; it passes through all stages on other machines.) Thanks, ParthaArticle: 131884
---------- Forwarded message ---------- hello !! i have a problem with programming PROM , i must programing it in linux , in windows this programing file is with *.msc extesion , it contans bit file for FPGA, when my machine reboot FPGA load bit file from PROM . My question is if i can program this with xc3sprog , or same soft , without IMPACT . TnxArticle: 131885
zuzaila@gmail.com wrote: > hello !! > i have a problem with programming PROM , i must programing it in > linux , in windows this programing file is with *.msc extesion , it > contans bit file for FPGA, when my machine reboot FPGA load bit file > from PROM . > My question is if i can program this with xc3sprog , or same soft , > without IMPACT . I'm using iMPACT with Linux drivers from http://rmdir.de/~michael/xilinx/ and it works fine. Maybe that's an option ?Article: 131886
Hi , The bitstream takes heed of BRAM , so my questions are : * Is it true that all the zeros that we localise in the beginning of configurable part ( of bitstream) correspond to BRAM initialization ? * how could i initialize BRAM differently ? Thank you ! M.BArticle: 131887
On 2008-05-06, jraj.thakkar@gmail.com <jraj.thakkar@gmail.com> wrote: > Hi all, > > My background is in Software Engineering C,C++,Java and Unix. I am > getting started with VHDL and Verilog. What is the good way/books/ > websites/training to get started? I have B.S. and M.S. in Computer > Engineering. Also, what is the learning curve in VHDL and Verilog? Have you ever taken a course in digital hardware? If not you should probably read a little bit about that before doing anything else. Unfortunately I don't really know of good books in English in this area because we are mainly teaching these subjects in Swedish. Once you know a little bit about digital hardware you can draw a little schematic and translate it into VHDL or Verilog. The learning curve of VHDL and Verilog is actually quite low _if_ you know what hardware your are planning to design. May I ask why you are interested in learning about VHDL or Verilog? Do you have a particular project in mind? Hobby or professional interest? /AndreasArticle: 131888
M.B. http://www.xilinx.com/products/ipcenter/dr_dt_data2mem.htm (data2mem tool) Describes how you place the program binary into a BRAM so it may be executed by the soft or hardened processor in the FPGA. For initializing the BRAM contents using VHDL, or verilog: http://toolbox.xilinx.com/docsan/xilinx9/help/platform_studio/html/ps_c_sim_memory_init_files.htm If you do nothing, BRAM is automatically initialized to all 0's by default by the bitstream (if nothing else is specified, BRAMs will have 0's for their contents in the bitstream). Austin From webmaster@nillakaes.de Tue May 06 08:29:11 2008 Path: flpi142.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!news.linkpendium.com!news.linkpendium.com!newsfeed.straub-nv.de!news01.khis.de!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <48207923$0$22076$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: warning from ISE 9.2 Newsgroups: comp.arch.fpga Date: Tue, 06 May 2008 17:29:11 +0200 User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 36 Organization: CNNTP NNTP-Posting-Host: 223085d5.read.cnntp.org X-Trace: DXC=YJ<K[RV>=jcXMoNd=::YAkWoT\PAgXa?aEg3cBIa4b3jCWCf629N19dVfa3D?:k27k95F]UUg=1hb`Gm9Cog@YDc X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:144348 X-Received-Date: Tue, 06 May 2008 11:28:35 EDT (flpi142.ffdc.sbc.com) Hi, waht does that mean : Loading device for application Rf_Device from file '3s200.nph' in environment /home/thorsten/Xilinx92i. WARNING:Xst:2677 - Node <b_reg_0> of sequential type is unconnected in block <ps2_rx>. WARNING:Xst:2677 - Node <b_reg_1> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_2> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_3> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_4> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_5> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_6> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_7> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_8> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_9> of sequential type is unconnected in block <ps2rx>. WARNING:Xst:2677 - Node <b_reg_10> of sequential type is unconnected in block <ps2rx>. ========================================================================= Advanced HDL Synthesis Report ?? Regards TKArticle: 131889
"Bob" <rsg.uClinux@gmail.com> wrote in message news:736a625f-4421-4309-a98f-4e645f2b1d7f@t54g2000hsg.googlegroups.com... > > Okay, but I don't know how to do this. Where do I "pick the code" > that you refer to? Martin is talking about the source code for the microcontroller... /Mikhail From webmaster@nillakaes.de Tue May 06 08:59:06 2008 Path: flpi142.ffdc.sbc.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!news.albasani.net!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <48208026$0$22074$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: Re: warning from ISE 9.2 Newsgroups: comp.arch.fpga Date: Tue, 06 May 2008 17:59:06 +0200 References: <48207923$0$22076$6e1ede2f@read.cnntp.org> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 46 Organization: CNNTP NNTP-Posting-Host: 223085d5.read.cnntp.org X-Trace: DXC=5PCCIY_ec3_@[U>KjoD5EWWoT\PAgXa?QBmN`jHYN1lZCWCf629N19TVfa3D?:k27[95F]UUg=1hR_3ji9JYQe;\ X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:144350 X-Received-Date: Tue, 06 May 2008 11:58:31 EDT (flpi142.ffdc.sbc.com) Thorsten Kiefer wrote: > Hi, > waht does that mean : > > Loading device for application Rf_Device from file '3s200.nph' in > environment /home/thorsten/Xilinx92i. > WARNING:Xst:2677 - Node <b_reg_0> of sequential type is unconnected in > block <ps2_rx>. > WARNING:Xst:2677 - Node <b_reg_1> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_2> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_3> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_4> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_5> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_6> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_7> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_8> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_9> of sequential type is unconnected in > block <ps2rx>. > WARNING:Xst:2677 - Node <b_reg_10> of sequential type is unconnected in > block <ps2rx>. > > ========================================================================= > Advanced HDL Synthesis Report > > ?? > > Regards > TK The warning appears only of I prepend a '1' to b_reg : b_next <= '1' & b_reg(10 downto 1); If I write b_next <= '0' & b_reg(10 downto 1); no warning is generated.Article: 131890
On May 6, 11:59 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote: > Thorsten Kiefer wrote: > > Hi, > > waht does that mean : > > > Loading device for application Rf_Device from file '3s200.nph' in > > environment /home/thorsten/Xilinx92i. > > WARNING:Xst:2677 - Node <b_reg_0> of sequential type is unconnected in > > block <ps2_rx>. > > WARNING:Xst:2677 - Node <b_reg_1> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_2> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_3> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_4> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_5> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_6> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_7> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_8> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_9> of sequential type is unconnected in > > block <ps2rx>. > > WARNING:Xst:2677 - Node <b_reg_10> of sequential type is unconnected in > > block <ps2rx>. > > > ========================================================================= > > Advanced HDL Synthesis Report > > > ?? > > > Regards > > TK > > The warning appears only of I prepend a '1' to b_reg : > b_next <= '1' & b_reg(10 downto 1); > > If I write > b_next <= '0' & b_reg(10 downto 1); > no warning is generated. I would suspect that hard-coding that bit to a '1' is causing your code to ignore the value of the entire vector wherever it is used, so it may be getting optimized away. You would really have to look at the rest of your code, and the context of the statement you gave above. Bang your head against the wall for a while and think about it. Pore over your code. Staring at a problem you don't understand and researching it on your own can be great ways to become a better engineer. If you're still stuck after a couple days of that, come back with more code and anything new you've learned.Article: 131891
On May 6, 11:33 am, "MM" <mb...@yahoo.com> wrote:
> > Okay, but I don't know how to do this. Where do I "pick the code"
> > that you refer to?
>
> Martin is talking about the source code for the microcontroller...
Oh!!! Do you mean this user-supplied function?
void waitTime(long microsec);
Now we're talking! The version I got suggested three approaches, one
that pulses TCK, one that doesn't, and one that does for short
durations, and doesn't for long ones! Well, I chose the one that
simply delays, as the comments suggested that's okay for Spartan-3; on
the other hand, the default does pulse the TCK! Since this is in
agreement with Martin, I'll try that tonight, and report back...
Thanks, guys!
Bob
Article: 131892
On May 6, 11:33 am, "MM" <mb...@yahoo.com> wrote:
> > Okay, but I don't know how to do this. Where do I "pick the code"
> > that you refer to?
>
> Martin is talking about the source code for the microcontroller...
Oh!!! Do you mean this user-supplied function?
void waitTime(long microsec);
Now we're talking! The version I got suggested three approaches, one
that pulses TCK, one that doesn't, and one that does for short
durations, and doesn't for long ones! Well, I chose the one that
simply delays, as the comments suggested that's okay for Spartan-3; on
the other hand, the default does pulse the TCK! Since this is in
agreement with Martin, I'll try that tonight, and report back...
Thanks, guys!
Bob
Article: 131893Hi all, My background is in Software Engineering C,C++,Java and Unix. I am getting started with VHDL and Verilog. What is the good way/books/ websites/training to get started? I have B.S. and M.S. in Computer Engineering. Also, what is the learning curve in VHDL and Verilog? Please let me know. Thanks JayArticle: 131894
Jay, I received a free copy of: "FPGA prototyping By VHDL Examples" by Chu. There will be a verilog version soon, too. A easy to read book, designed around the Digilentinc.com Spartan pcb for learning (he is a professor in Ohio). There are a lot of books out there, so I would encourage others to comment on ones they have actually read (like I did). AustinArticle: 131895
Hi:
I found your queries every where about SystemAce so I decided to
seek your help. I am also stuck in SystemAce and want to simply read
and write files from it. The code was working on EDK 8.1 reference
design but when I make a separate project no file is created in
SystemAce. I also added XILFATFS library in .mss and there were no
errors. I will be thankful to any help in this regard.
Thanks again
Article: 131896Austin , Exactly what i need ! thank you ! M.BArticle: 131897
On 3 mai, 04:47, 0xdeadbeef <Przemyslaw.D...@gmail.com> wrote: > Hi all. I'm brand new in fpga subject so please be patient :P > My problem is about to use stimulatorin waveform. > Well, exactly- there is no such thing as stimulator as it was in ahdl > 7.1. > How to add it then ? > Please help me because w/o it I won't be able to do my project. > Thanks I believe that Active-HDL v7.3 now uses the "Accelerated Waveform Viewer" by default instead of the old waveform viewer. That accelerated viewer is faster but lacks some feature of the old viewer, such as stimulators. There is a way to use the old waveform viewer however: http://support.aldec.com/KnowledgeBase/Article.aspx?aid=000724 As Mike said, you can always create your own stimulus in VHDL, which is better in the long run. I see stimulators as a way to run a quick and dirty simulation but I don't think it should be used throughout the project as it's less portable. You just got a proof of that with the change to the accelerated waveform viewer. PatrickArticle: 131898
On May 6, 2:35=A0pm, austin <aus...@xilinx.com> wrote: > Jay, > > I received a free copy of: > > "FPGA prototyping By VHDL Examples" by Chu. > > There will be a verilog version soon, too. > > A easy to read book, designed around the Digilentinc.com Spartan pcb for > learning (he is a professor in Ohio). > > There are a lot of books out there, so I would encourage others to > comment on ones they have actually read (like I did). > > Austin Thanks for the response. I will try to get hold of some good books.Article: 131899
On May 6, 10:54=A0am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > On 2008-05-06, jraj.thak...@gmail.com <jraj.thak...@gmail.com> wrote: > > > Hi all, > > > My background is in Software Engineering C,C++,Java and Unix. I am > > getting started with VHDL and Verilog. What is the good way/books/ > > websites/training to get started? I have B.S. and M.S. in Computer > > Engineering. Also, what is the learning curve in VHDL and Verilog? > > Have you ever taken a course in digital hardware? If not you should > probably read a little bit about that before doing anything else. > Unfortunately I don't really know of good books in English in this > area because we are mainly teaching these subjects in Swedish. > > Once you know a little bit about digital hardware you can draw a > little schematic and translate it into VHDL or Verilog. The learning > curve of VHDL and Verilog is actually quite low _if_ you know what > hardware your are planning to design. > > May I ask why you are interested in learning about VHDL or Verilog? > Do you have a particular project in mind? Hobby or professional > interest? > > /Andreas It's just a professional interest/curiousity. Just wanted to get hang of hardware design.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z