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Thanks Alan, I had done that, but the ISE give other errors like follows: ERROR:NgdBuild:455 - logical net 'GND' has multiple drivers. The possible drivers causing this are pin G on block BG1_Ground with type GND, pin PAD on block B318_comp/GND with type PAD ERROR:NgdBuild:462 - input pad net 'GND' drives multiple buffers. Possible pins causing this are: pin I on block B415_OBUF with type OBUF, pin i on block B318_comp/s1_7_ibuf with type IBUF, pin i on block B318_comp/s1_6_ibuf with type IBUF, pin i on block B318_comp/s1_5_ibuf with type IBUF, pin i on block B318_comp/s1_4_ibuf with type IBUF, pin i on block B318_comp/s1_3_ibuf with type IBUF, pin i on block B318_comp/s1_2_ibuf with type IBUF, pin i on block I'm searching what's wrong now. Thanks for your time. If you know something I apreciate a lot your help. RegardsArticle: 53652
hi all What is the difference between he Typical gates and Maximum System gates specifications For Altera EPXA1 these ratings are 100K and 263K respectively what may be the available gates for programming regards geekoArticle: 53653
Dear Utku,
On Wed, 12 Mar 2003, Utku Ozcan wrote:
>
> I'm using M3.1i SP8 IPv4 on Solaris 2.8.
>
> I am trying to use MPPR using command line with -m option.
> When I run the tool, in stdout following message comes out:
>
> ------------------
> par -t 10 -ol 5 -w -m 0 -s 3 map.ncd m2.ncd m2.pcf
> Release v3.3.08i - Par D.27
> Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
>
I use another release of the par tool, however i think the command line options
should be the same. The "-m" switch allows you to use multiple nodes for your
par run.
Assuming that you try to set the P&R iterations to unlimited ("-n 0") the
following command line will help:
par -t 10 -ol 5 -w -n 0 -s 3 map.ncd mppr.dir m2.pcf
It'll run a multi pass place-and-route on map.ncd, starting at table entry 10
and saving the best 3 results to the subdirectory mppr.dir.
Kind regards,
Lars.
--
GnuPG public key:
http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.key
Article: 53654hi all Anybody familiar with Excalibur bus functional model where is it available is it free.Can it be used for functional simulation in 3rd party tools re geeArticle: 53655
Utku Ozcan <utku.ozcan@netas.com.tr.spamela> writes: > par -t 10 -ol 5 -w -m 0 -s 3 map.ncd m2.ncd m2.pcf The -m option takes a filename argument (or do you use a file called "0"?). The file will contain hostnames for the machines where you will distribute your PaR iterations. This is described in the documentation. If you have machines with multiple CPU's you can mix upper and lower case names to make them appear as different hosts: machineone MachineOne machinetwo MachineTwo Means two par processes on the two hosts named machineone and machinetwo. I hope that the -m option will be supported in the rumored native Linux version (i.e. not a Windows version using Wine). Or even better yet, a more fine grained parallel version of PaR for clusters where also a single iteration will be distributed. Petter -- ________________________________________________________________________ Petter Gustad Test drive my coldfire uCLinux based web server at: http://www.gustad.com/coldfireArticle: 53656
I create EDIF files usgin Leonardo Spectrum Version: v2001_1d.45. Using EDIF file as entry in NGDBUILD, it issued the following error: ERROR:NgdBuild:519 - The EQN value of "()", on the LUT1 symbol "cB/GND_LUT1_CB", is not a valid equation. ERROR:NgdBuild:520 - The above-referenced equation has the following error: Unexpected ')'. Leonardo write out an EDIF netlist that contains LUT1 with empty INIT and EQN. I don´t know where is locate the error. Could someone help me? Thanks for the help. EduardoArticle: 53657
Hi,
I've written some VHDL code that synchronises 2 clocks, one being the normal
"clk", that drives all logic, coming from GCK0, and one "spiclk", used in
only one process, coming from GCK1.
Synthesis is fine, but when mapping, I get a warning, and then an error
(using xilinx ISE5.2.01i):
WARNING:NgdBuild:477 - clock net 'clk_bufgp' has non-clock connections.
These
problematic connections include: pin i0 on block spi_slave_clkout1 with
type
LUT1
and then
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
component:
PAD symbol "spiclk" (Pad Signal = spiclk)
BUF symbol "spiclk_ibuf" (Output Signal = spiclk_ibuf)
Each of the following constraints specifies an illegal physical site for
a
component of type IOB:
Symbol "spiclk" (LOC=P77)
Please correct the constraints accordingly.
Problem encountered during the packing phase.
I'm assuming I should somewhere define that "spiclk" is a clock signal...
but how.. and where?
thank you for your help,
Maxx
Article: 53658Is there a quick way to assign a lot of pins to signals ? Especially changing the pin say from input to output or bidirectional is tedious for dozends of them. Eg is there a file to be edited ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 53659
4000 series does have async resets, it does not have dedicated synchrounous
resets however.
David Binnie wrote:
> 4000 series does not facilitate async reset
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 53660> Is there a quick way to assign a lot of pins to signals ? > Especially changing the pin say from input to output or > bidirectional is tedious for dozends of them. > Eg is there a file to be edited ? See: http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&oe=UTF-8&safe=off&frame=r ight&th=68981c6ca9b8d83e&seekm=a561d1%24h69%241%40pegasus.csx.cam.ac.uk#link 3 (link may wrap so copy and paste manually if required) JamesArticle: 53661
Take a look at the pico-blaze. It is a free simple 8 bit micro. On a different issue... What is the board. We are looking at redesigning a spartan2e board to use the cypress ez chip and the usb interface might be of interest. Thanks, Theron Hicks newdevkit wrote: > Hello, > I recently aqquired a spartan2e dev board with a usb programming > interface (uses cypress ez chip). I am very new to fpgas and curious > as to where I can find a fpga core that is a cpu such as risc or cisc. > Something just very simple so that I can attempt to send the cpu a > command such as add two values or decrementing/incrementing a value. > If anyone can help me with this I would be very grateful with any > suggestions. Thank you.Article: 53662
can u tell me from where i will get free downloadable softwares for VHDL/verilog simulation and synthesis , SPICE ,IC Station...... with free licences. waiting for ur helpArticle: 53663
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<wppca.229368$AV5.2637012@news.chello.at>... > I would like to thank all for their good ideas and help. > > I've tested some of the suggested ideas and wrote a little summary with some > osci plots. You can find them at: > http://www.jopdesign.com/cyclone/powerup.jsp > > Regards, > > Martin Schoeberl Does Altera officially recognize the Power On Surge problem ? I didn't find any references to this problem in Altera's datasheets or App. notes. Their datasheets don't specify start up current as well. One of our designs sometimes has strange power-up problems at the low temperature. We never attributed this problems to the FPGA. Actually I didn't hear about this problem before (thank you, Martin). Now I'm starting to suspect that the problem is related to FPGA. The design is based on ACEX 1K100 device. Where can I find Power On Current profile for this device ?Article: 53664
adarsh arora wrote: > can u tell me from where i will get free downloadable softwares for > VHDL/verilog simulation and synthesis , SPICE ,IC Station...... with > free licences. > waiting for ur help http://geda.seul.orgArticle: 53665
Wouldn't FLASH /RESET = FPGA /INIT FLASH /CE = FPGA DONE work without an inverter (and a /sysreset) or will the FLASH CE/ falling edge ignored while FLASH /RST is asserted ? Regards, Tobias "Peter C. Wallace" <pcw@freeby.mesanet.com> wrote in message news:pan.2003.03.17.13.09.48.115606.23961@freeby.mesanet.com... > I just tested sucessfully a very simple and inexpensive serial > Flash EEPROM configuration device for SpartanII and IIE 100K gate or > smaller. I was using a PIC with a serial EEPROM before but with this > specific chip all thats needed is one inverter from /SYSRESET to > SYSRESET needed to generate falling /CS edge for the flash. > > > Flash chip is SST 45LF010 1 Mbit serial flash in 8 pin SOIC ($.1.35!) > > Connections: > > FLASH DI = TIED HIGH > FLASH SCLK = FPGA CCLK > FLASH DO = FPGA D0 > FLASH /RESET = /SYSRESET = FPGA /PROGRAM > FLASH /CS = SYSRESET (note inversion) > FLASH /WP = /SYSRESET > > FPGA configuration set for master slave mode. This works because the > 45LF010 has a read command of FF (DI tied high) and supports sequential > bit readout.What happens is the first config clocks shift in a FF command > (read) and an 1FFFF address. Subsequent clocks read the data from > 1FFFF,0,1, etc etc > > PCWArticle: 53666
Falk, I have found that XCS30 (Spartan 5V family) does not have parametric speed files any more, supported by Xilinx in their tools. Therefore, it is impossible to observe behavior of these chips with respe= ct to TEMPERATURE. I have developed a small Perl script that iteratively updates a UCF file and runs NGDBUILD, MAP, PAR, TRCE with -u and accumulates frequency value= from TRCE log file *.TWR. Then I have visualized the frequency change wit= h Gnuplot (http://www.gnuplot.info). Yes, the less the temperature, the faster the circuit. I could observe th= is result at the graphics visualization representation of temperature variation, by= choosing a Spartan-II device (XC2S50-5-FG256C). This device is supported with a parametric speed file (I think speed information is extracted from device= physical information file *.nph). But the change is not linear, it is almost. I ha= ve not observed this chip in lab. MfGr=FCssen, Utku Falk Brunner wrote: > "Utku Ozcan" <utku.ozcan@netas.com.tr.spamela> schrieb im Newsbeitrag > news:3E6F7710.1F34FD5A@netas.com.tr.spamela... > > > > We have design targetted to a XCS30-4-PQ240C which fails during > > heat tests. Product is being tested at -20 degrees but our commercial= > > FPGA is heated with special equipment to +20 degrees on package > > surface. > > > > The point is that the design fails during this testcase, and we wonde= r > > whether it is of a good practice to emulate this test with TEMPERATUR= E > > constraint in UCF file. We would like to hear the experiences around.= > > Hmm. AFAIK the TEMPERATURE constraint only sets the "speed point" of th= e > static timing analysis. Means, a cold chip is faster than a hot chip. S= o if > you decrease the temperature, the design will get faster. If you are lu= cky, > the static timing analysis finds a hold time problem, but I wouldnt bet= on > this. I guess you must find the problem on your own. A hold time proble= m is > likely, but it can also be a unclean clock domain crossing, a clock ske= w > problem on non-clock nets etc. > Good luck. > > -- > MfG > FalkArticle: 53667
Yes, I am aware of MPPR, I have used it for a large design aggressively 3 years ago. The point is that PAR behaves different, to a mistyped command line argument. I was just curious, what that meaning was. Utku Petter Gustad <newsmailcomp4@gustad.com> wrote in message news:<m3adfry5nh.fsf@scimul.dolphinics.no>... > Utku Ozcan <utku.ozcan@netas.com.tr.spamela> writes: > > > par -t 10 -ol 5 -w -m 0 -s 3 map.ncd m2.ncd m2.pcf > > The -m option takes a filename argument (or do you use a file called > "0"?). The file will contain hostnames for the machines where you will > distribute your PaR iterations. This is described in the > documentation. If you have machines with multiple CPU's you can mix > upper and lower case names to make them appear as different hosts: > machineone > MachineOne > machinetwo > MachineTwo > > Means two par processes on the two hosts named machineone and > machinetwo. > > I hope that the -m option will be supported in the rumored native > Linux version (i.e. not a Windows version using Wine). Or even better > yet, a more fine grained parallel version of PaR for clusters where > also a single iteration will be distributed. > > PetterArticle: 53668
"geeko" <jibin@ushustech.com> wrote in message news:b59525$26k0i5$1@ID-159027.news.dfncis.de... > hi all > What is the difference between he Typical gates and Maximum System gates > specifications > For Altera EPXA1 these ratings are 100K and 263K respectively what may be > the available gates for programming > > Try sci.electronics.componentsArticle: 53669
"Maxx" <bla@bla.com> schrieb im Newsbeitrag news:3e78619d$0$1139$4d4ebb8e@read-nat.news.nl.uu.net... > Hi, > > I've written some VHDL code that synchronises 2 clocks, one being the normal > "clk", that drives all logic, coming from GCK0, and one "spiclk", used in > only one process, coming from GCK1. > > Synthesis is fine, but when mapping, I get a warning, and then an error > (using xilinx ISE5.2.01i): > > WARNING:NgdBuild:477 - clock net 'clk_bufgp' has non-clock connections. > These > problematic connections include: pin i0 on block spi_slave_clkout1 with > type > LUT1 This sounds like you dont use spiclk as a pure clock. I guess you do some kind of clock gating or so. This is not good in two ways. 1st (very important) you will run into ugly porblems with clock gating. 2nd the synthesizer realize that spiclk is NOT directly used as a clock signal, so it inserts just a normal input buffer (ibuf). But since you constraint this input to a GCK input, you MUST use a ibufg. You can do this by manually instanciating the ibufg, BUT I strongly recommend that you think about you synchronization in general. Gated clocks are no good in FPGAs. (Yes, there area always exceptintion to every rule ;-) > ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB > component: > PAD symbol "spiclk" (Pad Signal = spiclk) > BUF symbol "spiclk_ibuf" (Output Signal = spiclk_ibuf) -- MfG FalkArticle: 53670
Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: > Is there a quick way to assign a lot of pins to signals ? > Especially changing the pin say from input to output or > bidirectional is tedious for dozends of them. > Eg is there a file to be edited ? look for a file named *.csf Input or output is defined by the symbol you use (or the VHDL code), its not in the csf- file RomanArticle: 53671
Hello, I'am currently working on a project that will be implemented in a Xilinx Virtex-II device. I've previously used 'bit patching' on a Virtex component (patching an existing configuration file with a microcontroller so you can alter the the contents of ROMs and other components - see Xilinx Application note 151). I cannot find any information about bit patching Virtex-II configuration files. Has anybody attempted this before? Will Xilinx release such information as it did with the Virtex?Article: 53672
ozcan@ieee.org (Utku Ozcan) writes: > Yes, I am aware of MPPR, I have used it for a large design aggressively > 3 years ago. Good. So you would also vote for a Linux native (presumably with x86-64 support) par -m as well? > The point is that PAR behaves different, to a mistyped command > line argument. I was just curious, what that meaning was. OK. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 53673
I have used the altera ACEX 1K product line and after studing the new Cyclone products ... except for possibly the very lowest cost 1K products which still seem to be cheaper than the lowest cost Cyclone .. is there any reason to still consider the 1K products for new designs over the Cyclone ? thanks for any insight CBArticle: 53674
Hi, Im new to this field, and currently trying to configure an XC9500 CPLD using the Xilinx ISE Webpack software through a JTAG interface.. Im having trouble in that each time i try to download the data to my device the software crashes. I am able to connect to the device and perform a blank check on it, so im pretty sure that it is not a power problem. What i'm after is advice on the signals that must be present on the aforementioned pins. Eg. must i have a clock signal on the GCK pin to clock the internal logic and must the GTS pin be 'high' to enable the outputs. I cannot seem to find this very basic information in the datasheet, maybe because it is too basic, but it has escaped me. so any help would be appreciated. Thanks.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z