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Duth schrieb: > On Apr 18, 11:40 am, Thomas Heller <thel...@python.net> wrote: >> Finally I gotsimulationof logicores in webpack 9.1.03i to work with the ISE simulator. >> However, these messages appear in the transcript window: >> >> Running Fuse ... >> WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. >> Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector.vhd" in Library work. [...] >> Thanks for any help, >> Thomas > > Hi Thomas, > > Can you try to do a clean up project files and ensure that you have > both: > > - Latest Service Pack > - Latest IP Update > > The order in which you install should be the order in which it was > released. If you use webupdate, then this will take care of this for > you. Sounds like it is trying to look an older compiler version > somewhere and that is why you are getting the error. Ah, cool. Webupdate reported 'no updates to display', but 'Cleanup Project Files' made the warnings go away. Many thanks for the help, ThomasArticle: 118201
On Apr 18, 4:29 pm, a <a...@walla.com> wrote: > Ive got a problem like mentioned, > During "map" signals that are used in the design are being trimmed and > than I get errors that these signals are missing. > Anybody knows how to prevent ISE from trimming my signals? > (using the option in map properties doesn't change anything) > My ISE version is 9.1 webpack. > Looking forward for some help. You didn't say what ther errors were. Normally map only removes logic that will not affect the outputs of the design. Then if you have timing contraints for example on nets that have been trimmed you'll get errors during build. If you really want to keep parts of a design even when they aren't used, you can generate a function from the nets (like a big OR or AND gate) and run its output to an unused pin. If you're getting errors because map removed portions of the design that are actually used, this often happens because those parts were not sourced for some reason (missing clock connection could cause this). What errors are you actually seeing? Can you post a few lines of the report? HTH, GaborArticle: 118202
Gabor napisa?(a): > On Apr 18, 4:29 pm, a <a...@walla.com> wrote: >> Ive got a problem like mentioned, >> During "map" signals that are used in the design are being trimmed and >> than I get errors that these signals are missing. >> Anybody knows how to prevent ISE from trimming my signals? >> (using the option in map properties doesn't change anything) >> My ISE version is 9.1 webpack. >> Looking forward for some help. > > > You didn't say what ther errors were. Normally map only removes logic > that will not > affect the outputs of the design. Then if you have timing contraints > for example on > nets that have been trimmed you'll get errors during build. If you > really want to keep > parts of a design even when they aren't used, you can generate a > function from > the nets (like a big OR or AND gate) and run its output to an unused > pin. > > If you're getting errors because map removed portions of the design > that are > actually used, this often happens because those parts were not sourced > for some reason (missing clock connection could cause this). What > errors > are you actually seeing? Can you post a few lines of the report? > > HTH, > Gabor > thanks problem solved, it was because as you said problems with clock connections.Article: 118203
On 2007-04-19, Kunal <kunal.yadwadkar@gmail.com> wrote:
> Some suggestions were the spartan-3 starter kit, XSK40 and the XSK95.
> Being a poor student, I can't afford anything else (and being a
> beginner I guess I may not be able to _use_ anything else :) )
I've recently come across the Altera DE1 board which also seems like
a very good deal. Among its good nice features are:
512Kbyte SRAM memory - No need for a cumbersome SDRAM controller or DDR
controller
Audio input/output - Haven't found this on a low end Xilinx board yet
SD card interface - Nice for storing audio files for the above :)
Lots of leds
Downside: No Ethernet.
(I'd love to hear about a Xilinx board with Audio input/output in
the same price range. We are interested in such a board for a course
we are giving since it would be nice if students could afford the
board.)
Personally, I would also like to point out that getting DDR memory
to work is not straightforward. If DDR memory is your only external
memory (and you are building a design which needs more memory than
is available on the FPGA) you are going to be in trouble. (Unless
you buy the EDK which can automatically generate a design with
a DDR memory controller for you.) DDR is complicated by the fact
that you have to run it quite fast if you are going to follow
the standard.
In contrast, SRAM is very easy to interface to and SDRAM can be
done with a moderate effort.
/Andreas
Article: 118204
Lately I've seen a couple of posts that ask for a PCI based prototype boards
which has drivers available. Well actually, almost any post which asks about
PCI based prototype boards asks for drivers as well. I'm writing this post in
the hope that someone will find it useful.
Firstly, I'd like to point out that at least in Linux it isn't that hard to
write a driver since a lot of information is publicly available [1]. But it
isn't really necessary to write a kernel module since it is very easy to
communicate with a PCI card from Linux if you know what to do. The program
included below show how to map a PCI card into a programs address space and
write some values to it.
While this is probably not suitable for a final product it will do nicely for
experimentation during development. You can even do DMA in this kind of program
if you make sure to boot linux with a command line like mem=120M to fool Linux
into thinking you have less memory than you really have which allows you to
use the rest for DMA without fear of overwriting important data. I'm sorry
to say that you cannot do IRQ:s in this way though, for that you will need
a true driver.
[1] http://lwn.net/Kernel/LDD3/ - Recommended. Download it or buy it.
/Andreas
/* Simple test program which will map a PCI card into userspace and
* manipulate it. */
#include <stdio.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <math.h>
#include <sys/mman.h>
int main(int argc,char **argv)
{
int fd;
volatile long *foo;
long verify[2048];
int i;
int idx,val;
int count;
long long writecount;
int verifications;
/* This is where we first open the memory and then mmap
* a PCI card at address 0xfa240000 into the programs address
* space. A real program should probably scan /proc/bus/pci/devices
* to find out where the PCI card has been configured but I was lazy
* when I wrote this test program... */
fd = open("/dev/mem",O_RDWR);
foo = mmap(0,262144,PROT_READ|PROT_WRITE,MAP_SHARED,fd,0xfa240000);
printf("Opened PCI card\n");
printf("Resetting PHY\n");
foo[0x1002] = 0x00000000;
sleep(1);
printf("Removed reset\n");
foo[0x1002] = 0x80000000;
sleep(5);
printf("Writing packet\n");
foo[0] = 0xffffffff;
foo[1] = 0xffff0001;
foo[2] = 0x01234567;
foo[3] = 0x08004500;
foo[4] = 0x00200001;
foo[5] = 0x00000511;
foo[6] = 0x10000a00;
foo[7] = 0x00050a00;
foo[8] = 0x00010020;
foo[9] = 0x00ff0010;
foo[10] = 0x0000abcd;
foo[11] = 0xef001122;
foo[0x1000] = 0;
foo[0x1001] = 60;
printf("Sending packet\n");
foo[0x1002] = 0x80000001;
}
Article: 118205On Apr 19, 2:50 pm, cs_post...@hotmail.com wrote: > On Apr 19, 1:48 pm, cs_post...@hotmail.com wrote: > > > > > On Apr 19, 12:44 pm, Austin Lesea <aus...@xilinx.com> wrote: > > > > Kunal, > > > > The "Spartan 3E Starter Board" from digilentinc.com is used by quite a > > > number of schools and universities. > > > > As such, 'google' for this shows 131 hits, with complete courses with > > > labs from University of Arizona, etc. etc. > > > > $149. > > > >http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Pro... > > > > Austin > > > Unless someone really needs an S3E chip, I might stay away from that > > board, as part of its schematics (around the USB chip) are withheld, > > limiting your options for programming and communicating with it to > > what is officially supported or laboriously reverse engineered. > > In fairness, I should add the substantial memories and display to the > "unless one needs" consideration. > > All of these boards have tradeoffs of goodies vs. issues Hey guys, thanks for the advice. I do have a parallel port on my machine, but I'd rather also be able to program from my laptop. The S3E sounds really great, but it's probably got more goodies than I can pay for :). I'd probably go for the nexsys one, though not without another thorough look at both the S3E starter as well as nexsys. Thanks all the same! cheers, KunalArticle: 118206
An output pin voltage swing is determined by VCCO, so how else does specifying LVCMOS25 vs LVCMOS18 as the IOSTANDARD affect output signals? ThanksArticle: 118207
Hello, I have several DCMs in my design and they are phase synchronized. I generated them respectively in the DLL mode from the system clock. The simulation is fine. But when I put the design on board, it stops working somehow. My guess is that the DCMs aren't locked. When I tried a very simple EDK design with only one DCM and tie its reset port with ground, the design always works. If I tied the reset port to the switch on the board (high active), it always works after configuration. But if I push the switch on the board, sometimes it works, and sometimes it doesn't. Would you please give me any suggestion on the DCM reset signal? I noticed there is a proc_sys_reset core in the EDK kit, is that a good idea to use this core and generated reset signal? The proc_sys_reset has a DCM_locked input and says it should be connected to the DCM which achieved the lock last when there are several DCMs in the system. But my DCMs are not chained and I don't know which one will achieve lock last. Is there a way to and all the lock signals of DCMs in the EDK and tie it to the proc_sys_reset core? Thanks a lot, RebeccaArticle: 118208
Mike, Well, the blank sheet (3) is for the USB interface. Not sure why... http://www.xilinx.com/products/boards/files/s3e_starter_schematic.pdf Is the previous revision of the schematic, with page 3 shown. If it is proprietary (now, in this revision), then I suppose someone else owns the USB interface design, and they have rights to it we must protect. Still, I do find it odd. If someone really wants to look at a USB to FPGA interface, not only is there the previous revision of the board schematic, but thousands of them out there on the web. AustinArticle: 118209
Well, Specifying the IO standard pretty much identifies to the bitgen part of the program which bits to turn on (and off) to get that drive strength for that standard. Suppose you have 2.5 V Vcco, and you call for a 1.5 V 4 mA CMOS driver -- running at 2.5 volts it will be much stronger than the 4 mA as the bits will have enabled most of the driver "legs" to get 4 mA min at 1.5V Vcco. It would require far fewer "legs" enabled to get 2.5 V 4 mA. So, the IO will function at a different voltage, it just won't meet the data sheet specifications for that new voltage. Its behavior will be stronger if the Vcco is larger than it thought, or weaker if smaller than it was programmed for. Other specifications will also be affected: delay and input impedance if differentially terminated internally. AustinArticle: 118210
On Apr 18, 1:55 pm, FightingQuak...@gmail.com wrote: > Also, I guess you want to have signal tap in the first pass because of > the long re-compile times. With the Signal Tap GUI flow, you don't > have to go through a complete recompile. There is an option to add > Signal Tap nodes in post-fit. (i.e. no synthesis of your original > design, just an addition of the Signal Tap logic). You can do this > by turning on Incremental compile in the settings dialog box (it's > defaulted to on) and checking the "Incremental Compilation" in the > Signal Tap GUI. > Full Incremental Compilation is definitely turned on, but I haven't made any "LogicLock" assignments... is that actually necessary? Anyhow, I haven't been able to get around doing ... 1 Create EDIF project from Precision RTL (scripted) 2 Enable Signal Tap II in design (unable to add nodes) 3 Perform full compile (synth + p&r).. wait 30-40 minutes.. 4 Add post-fitted nodes 5 Perform full compile.. again.. 6 GOTO 4 Also, I have been unable to add BI-DIRECTIONAL pins to signal tap without it complaining during (re)-synthesis... Any ideas?, at this point I just want to get this to work! EdmondArticle: 118211
Somewhat of what you are looking for is our Broaddown2 board used in conjunction with with our Virtex-4 module Swinyard1. Some details here http://www.enterpoint.co.uk/moelbryn/swinyard1.html. We can probably provide the Spartan-3 on the Broaddown2 programmed to your needs with our PCI interface. John Adair Enterpoint Ltd. On 18 Apr, 05:17, "h...@hit.edu.cn" <h...@hit.edu.cn> wrote: > I want to buy a FPGA PCI development board supporting the following > features: > 1. Large FPGA device, Xilinx FPGA prefered, especially Virtex2p/ > Virtex4/Virtex5 series. > 2. PCI(33M/32bit,66M/64bit) bridge interface with license IP Core, or > third party ASIC implemented, or small FPGA(like spartan2 FPGA) > implemented. > 3. Detailed and complete reference design for PCI development in both > FPGA side and PC side. > > Thanks.Article: 118212
On Apr 19, 2:25 pm, Rebecca <pang.dudu.p...@hotmail.com> wrote: > Hello, > I have several DCMs in my design and they are phase synchronized. I > generated them respectively in the DLL mode from the system clock. The > simulation is fine. But when I put the design on board, it stops > working somehow. My guess is that the DCMs aren't locked. > When I tried a very simple EDK design with only one DCM and tie its > reset port with ground, the design always works. If I tied the reset > port to the switch on the board (high active), it always works after > configuration. But if I push the switch on the board, sometimes it > works, and sometimes it doesn't. Would you please give me any > suggestion on the DCM reset signal? > > I noticed there is a proc_sys_reset core in the EDK kit, is that a > good idea to use this core and generated reset signal? The > proc_sys_reset has a DCM_locked input and says it should be connected > to the DCM which achieved the lock last when there are several DCMs in > the system. But my DCMs are not chained and I don't know which one > will achieve lock last. Is there a way to and all the lock signals of > DCMs in the EDK and tie it to the proc_sys_reset core? > > Thanks a lot, > Rebecca You can and all of the signals together using the util_reduced_logic core in EDK. Look in the IP Catalog under Utility. Did you start your design with the Base System Builder? If so, it should have put a reset core in the design for you. If not, add one in. Regards, John McCaskill www.fastertechnology.comArticle: 118213
Rebecca, If you are using Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=14425&BV_SessionID=@@@@1770433415.1177021117@@@@&BV_EngineID=cccdaddkidmkgdlcefeceihdffhdfjf.0 For Spartan parts: http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf There are a number of small details that might cause the DCM to not lock, or lose lock: 1) clock feedback does not arrive in time after reset 2) clock frequency is changing as the DCM is trying to lock 3) clock has too much jitter 4) clock has missing pulses (bad signal integrity, noise, etc.) Depending on which part you are using, you need to review the above literature, as well as read the chapter in the respective user's guide. AustinArticle: 118214
On Apr 18, 9:11 pm, nezhate <mazouz.nezh...@gmail.com> wrote: > On Apr 18, 9:40 pm, Andy Peters <goo...@latke.net> wrote: > > > On Apr 18, 4:24 am, nezhate <mazouz.nezh...@gmail.com> wrote: > > > > Hi all, > > > I'm using Ise 9.1.03i. when I try to print a code written in Ise text > > > editor, I get this error: > > > "Print fails because the default printer has not been selected", and > > > when the design summary is opened I can see the window "steup printer" > > > and my default printer is automatically selected. > > > How to configure printer for ise text editor? > > > thanks. > > > Wow...somebody actually uses the ISE text editor? > > > I thought everyone just used emacs. > > > -a > > not everyone works under Linux. > At home I have Linux and use emacs but in univ. they have windows and > use Ise text editor .... what to do? I use emacs on Windows every day! -aArticle: 118215
Andreas, If I have my choice, I hope he chooses a Xilinx board. I do not mind one bit that he uses an Altera board to learn about FPGAs: it will be his first job that will determine who he will get to use, it will probably not be his choice! So, the more that know how to use FPGA's, the better. I only offer up the Digilent board because there have been tens of thousands sold to students. The resulting ecosystem has some benefits. AustinArticle: 118216
You shouldn't have to worry about LogicLock assigments. By default your top level project forms a "Design Partition" Check in the settings dialog box to make sure "Full Incremental Compilation" is turned on. After you do that, go to the Design Partitions window ( under the Assignments menu). Make sure that the top level partition is set to Netlist type "Post-Fit". In Signal Tap, you can then turn on incremental Compilation and add your nodes post- fit. That should get you started without having to recompile this thing every time. Also, I noticed that Quartus doesn't allow you to both instantiate signal tap into your RTL and use the GUI, so stick to either one or the other. btw, what version of Quartus are you running? On Apr 19, 3:08 pm, Edmond Cot=E9 <edmond.c...@gmail.com> wrote: > On Apr 18, 1:55 pm, FightingQuak...@gmail.com wrote: > > > Also, I guess you want to have signal tap in the first pass because of > > thelongre-compile times. With the Signal Tap GUI flow, you don't > > have to go through a complete recompile. There is an option to add > > Signal Tap nodes in post-fit. (i.e. nosynthesisof your original > >design, just an addition of the Signal Tap logic). You can do this > > by turning on Incremental compile in the settings dialog box (it's > > defaulted to on) and checking the "Incremental Compilation" in the > > Signal Tap GUI. > > Full Incremental Compilation is definitely turned on, but I haven't > made any "LogicLock" assignments... is that actually necessary? > > Anyhow, I haven't been able to get around doing ... > > 1 Create EDIF project from Precision RTL (scripted) > 2 Enable Signal Tap II indesign(unable to add nodes) > 3 Perform full compile (synth + p&r).. wait 30-40 minutes.. > 4 Add post-fitted nodes > 5 Perform full compile.. again.. > 6 GOTO 4 > > Also, I have been unable to add BI-DIRECTIONAL pins to signal tap > without it complaining during (re)-synthesis... > > Any ideas?, at this point I just want to get this to work! > > EdmondArticle: 118217
Andreas Ehliar wrote: > Lately I've seen a couple of posts that ask for a PCI based prototype > boards which has drivers available. Well actually, almost any post > which asks about PCI based prototype boards asks for drivers as well. > I'm writing this post in the hope that someone will find it useful. And if you want to experiment with it under Windows, try this: <http://www.entechtaiwan.com/tvicpci.htm> It's free and very easy to use. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 118218
On 4=D4=C220=C8=D5, =C9=CF=CE=E76=CA=B111=B7=D6, John Adair <g...@enterpoin= t=2Eco.uk> wrote: > Somewhat of what you are looking for is our Broaddown2 board used in > conjunction with with our Virtex-4 module Swinyard1. Some details herehtt= p://www.enterpoint.co.uk/moelbryn/swinyard1.html. We can probably > provide the Spartan-3 on the Broaddown2 programmed to your needs with > our PCI interface. > > John Adair > Enterpoint Ltd. > > On 18 Apr, 05:17, "h...@hit.edu.cn" <h...@hit.edu.cn> wrote: > > > > > I want to buy a FPGA PCI development board supporting the following > > features: > > 1. Large FPGA device, Xilinx FPGA prefered, especially Virtex2p/ > > Virtex4/Virtex5 series. > > 2. PCI(33M/32bit,66M/64bit) bridge interface with license IP Core, or > > third party ASIC implemented, or small FPGA(like spartan2 FPGA) > > implemented. > > 3. Detailed and complete reference design for PCI development in both > > FPGA side and PC side. > > > Thanks.- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - I have noticed your product these days. I am also interested in your development board. I am in post-graduate student in Shenzhen, China. Can you show me more details? I would like to know the price of Broaddown2 and Swinyard1 with the largest Virtex4 device. And also the way you can export it to China. Because I am lack of any experience with international import/export business. Thanks.Article: 118219
On Apr 19, 6:51 pm, Austin Lesea <aus...@xilinx.com> wrote: > Andreas, > > If I have my choice, I hope he chooses a Xilinx board. > > I do not mind one bit that he uses an Altera board to learn about FPGAs: > it will be his first job that will determine who he will get to use, it > will probably not be his choice! > > So, the more that know how to use FPGA's, the better. > > I only offer up the Digilent board because there have been tens of > thousands sold to students. The resulting ecosystem has some benefits. > > Austin Hey all, Thanks a lot for your help! Andreas, your Altera DE1 board seems really interesting especially with the audio out. But I guess Austin is right too. If xilinx is indeed a more popular choice for students, there'll probably be more accessible projects, docs etc. to help me out. Anyway, I'll try and find out how popular this altera kit is too, and then come up with a conclusion. That aside, the nexys one looks good to me, primarily because it has the usb port too, and also 'cos it's all i can afford right now :(. I'd love to have the S3E, but............... Thanks a million once again! cheers, KunalArticle: 118220
There are several ways to double a clock frequency.
Any Digital Clock Manager (DCM) orPLL will do it.
I published a very simple 1-flip-flop design on Xilinx TechXclusives
("six easy pieces"), that assumes a 50% duty-cycle clock input.
A dual-ported RAM solves the problem of unrelated read and write
clocks, but not the potential problem of contention, when you write
to, and read from, the same location more or less simultaneously in an
asynchronous way. That's still your job to guard against.
But the time-division-multiplexed design that I recommended avoids
this problem altogether.
Peter Alfke
On Apr 17, 4:08 am, vlsi_learner <baj...@gmail.com> wrote:
> Hi Peter,
>
> Another thing, what if I dont have the double clock available in the
> design?
>
> Thanks in advance for your help
>
> vlsi_learner wrote:
> > Hi peter,
>
> > If I understand correctly, you are saying that I should use double
> > clock rate & then time multiplex the ports i.e
> > write on even clock into a single port RAM & read on the odd clock
> > from the SPRAM.
> > But what about reads at varying freq ( 5 - 30 Mhz)
>
> > Peter Alfke wrote:
> > > In a dual-ported RAM, you have two independent access mechanism to the
> > > common data, so you can read while you are writing. (In a "true dual-
> > > ported RAM" you can also have two independent write, or two
> > > independent read opertions going on simultaneously) But you still have
> > > to avoid simultaneous read and write to the same location.
> > > (Contention)
> > > You avoid (almost) all these problem with Time-Division Multiplexing,
> > > as I mentioned in my previous post.
> > > Given your extremely slow speed, that's the way to go!
> > > Peter Alfke
>
> > > On Apr 16, 10:04 pm, vlsi_learner <baj...@gmail.com> wrote:
> > > > Hi Petter,
>
> > > > I was trying to do the same, using 2 SPRAM's & writing to both of them
> > > > simultaneouly using same address & data.
>
> > > > addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr; (port A is R/W port)
>
> > > > addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0); (port B
> > > > is read only port)
>
> > > > In this case , if there is a write from port A then we cannot read
> > > > from the other port.Is this dual port
> > > > functionality?
>
> > > > Petter Gustad wrote:
> > > > > "vlsi_learner" <baj...@gmail.com> writes:
>
> > > > > > My ASIC design requires dual port memories(one port R/W other port
> > > > > > only read) but there is a constraint on using it.
> > > > > > Instead I am planning to create this memory using single port RAM's.
>
> > > > > You an use two RAMs if you have enough RAM availabe in your
> > > > > ASIC. Simply write into both RAMs using the same address and data.
>
> > > > > Petter
> > > > > --
> > > > > A: Because it messes up the order in which people normally read text.
> > > > > Q: Why is top-posting such a bad thing?
> > > > > A: Top-posting.
> > > > > Q: What is the most annoying thing on usenet and in e-mail?
Article: 118221Hi All, After searching the web (and xilinx's own site) for any references to the "xilprofile" library or documentation and only finding XAPP545 which is for the ppc and edk 6.x. I was wondering if anyone could point me in the direction of this library for use with the microblaze and edk 8.2? Thanks, P.Article: 118222
This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware in FPGAs. http://lists.duskglow.com/open-graphics/2007-January/008663.html http://en.wikipedia.org/wiki/Richard_StallmanArticle: 118223
On Apr 20, 4:41 am, Paddy <PaddyDemps...@gmail.com> wrote: > Hi All, > > After searching the web (and xilinx's own site) for any references to > the "xilprofile" library or documentation and only finding XAPP545 > which is for the ppc and edk 6.x. I was wondering if anyone could > point me in the direction of this library for use with the microblaze > and edk 8.2? > > Thanks, > P. Hi again, Please disregard this message as about 5 minutes after I sent the message I found a workaround for the xilprofile problem, It appears that in, at least ISE/EDK 8.2.2sp3 in order to do profiling on software code you need to enable the enable_sw_intrusive_profiling and set the profile_timer to the timer in the system. http://toolbox.xilinx.com/docsan/xilinx8/help/platform_studio/platform_studio.htm#html/ps_c_pro_profiling_overview.htm Thanks, P.Article: 118224
On Apr 20, 3:09 am, Mark McDougall <m...@vl.com.au> wrote: > Andreas Ehliar wrote: > > Lately I've seen a couple of posts that ask for a PCI based prototype > > boards which has drivers available. Well actually, almost any post > > which asks about PCI based prototype boards asks for drivers as well. > > I'm writing this post in the hope that someone will find it useful. > > And if you want to experiment with it under Windows, try this: > <http://www.entechtaiwan.com/tvicpci.htm> Also, if you do not need DMA, this product is great: http://www.zealsoftstudio.com/memaccess/ It is next to free and extremely simple to use. Kolja Sulimma
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