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Hi Dear all, I need an implementation of a STATIC RAM with VHDL; I need this RAM to work with/without read buffer and with/without partitioning. Could you please help me? Thank you in advance.Article: 117451
Hi Dear all, I need an implementation of a STATIC RAM with VHDL; I need this RAM to work with/without read buffer and with/without partitioning. Could you please help me? Thank you in advance. ZiLakArticle: 117452
Matthew, Parallelism was also a factor in choosing PCA for implementation on FPGA, and Composite-PCA can even increase that parallelism. I think it's a very good point what you said about speed concerning a C implementation, which means we'll probably take your suggestion and do it entirely in VHDL. The part of the team working on the algorithm is already breaking it down into parallel parts; hopefully this would make the algorithm really "shine", as we definitely need it to. Also, for the sake of comparison, I'm thinking we can implement the same algorithm on a standard PC with threading and run it in real-time priority, and compare the results to see what was gained through the FPGA implementation. I'm sure the results would be interesting either way. And in response to Jim's question, this is more of a research project; so, naturally, we want it to support as large a database as possible. The plan is to keep testing it with databases of increasing size until we get it to reach the maximum size possible without breaking the real- time requirement. Thanks all for your responses... Best Regards, Islam Ossama On Mar 31, 9:23 am, Matthew Hicks <mdhic...@uiuc.edu> wrote: > We (Illiac 6 research group at the University of Illinois) are currenlty > working on porting one of the more popular face recognition programs for > an application that is going to run on our "Communications Supercomputer", > which involves a Virtex II-Pro FPGA. These is no benefit from implementing > a processor in the FPGA and then running the existing C code on it, becuase > there is no way it will come close to the performance of a processor in ASIC. > Your only option of utilizing the FPGA for speedup is going to the roots > of the algorithm(s), finding parallelism, and writing HDL code to exploit > that parallelism. That is the phase we are currently in. Remember that > an algorithm that may not be the best in a sequential environment may shine > in a highly parallel environment, so it's best to look at all algorithms > for possible parallel structure. > > ---Matthew HicksArticle: 117453
On Mar 30, 9:53 pm, "Islam Ossama" <islam.oss...@gmail.com> wrote: > Peter, > > First of all, thanks for replying :-). > > > I did check out the Xilinx University Program. The "Virtex-II Pro > Development System" seems like an extreme overkill in our case, since > the use of FPGA isn't standard curriculum in our faculty; we are > mainly doing this as a unique, single-case approach. It seems like an > excellent choice for an engineering faculty, though. Unfortunately, I > don't think our faculty (Computer Science) would be willing to make > such a purchase based on a single case requirement, especially taking > into account the relatively high currency exchange rate (1 USD ~= 5.7 > EGP). I think you should deliberately use a board that is an "overkill", so that you can stay away from any limited resources, and concentrate on the job at hand. Regarding cost: Universities can buy this board for less than $500, which is a fantastic bargain... Good luck with your project. Peter AlfkeArticle: 117454
Ok :-). I'll be sure to look into it. I was kinda set back by the retail number, which would be closer to 10 grand in local currency. I'll contact the university on Monday and see if I can work this out. Thanks! On Mar 31, 6:05 pm, "Peter Alfke" <a...@sbcglobal.net> wrote: > > I think you should deliberately use a board that is an "overkill", so > that you can stay away from any limited resources, and concentrate on > the job at hand. > Regarding cost: Universities can buy this board for less than $500, > which is a fantastic bargain... > Good luck with your project. > Peter AlfkeArticle: 117455
Hi all, at the moment, we are using AT17LV010 configuration devices for a spartan 2S100. I have to look for a different solution which is not so expensive. The Xilinx XC17V01 is OTP and more expensive than the AT17LV010. Does someone know a different prom (OTP, EEPROM, Flash)? I don't want to use a pld or microcontroller for active serial programming. Thanks a lot MarkusArticle: 117456
I am running Fedora 6, and I am having trouble installing ISE WebPack. When I run the setup program it tells me that I don't have the right version of libstdc++, so I installed the compat-libstdc++ package. Now when I run setup, the program just quits immediately, with no error message at all. Anybody have any ideas? Thanks, MattArticle: 117457
Hi, I am using XPS to program my application onto the Xilinx Virtex2 pro board. The size of the application is upto 1 MB and hence I need to reference instructions from the external DDR memory (2GB). I need to write a bootloader and program the Flash memory with the executable (.elf or .srec) file, such that, on booting, the bootloader would copy the executable to the external DDR at the address which will later be used by Microblaze to fetch instructions. I am facing many problems and am not sure if my approach is right. 1. flash is connected to the microblaze using OPB through the OPC-EMC controller. 2. generate libraries and BSP 3. select the desired executable (.elf) . program flash memory selecting the 'create flash bootloader option'. on 'program flash' and after the bootloader application is successfully created. the text window stops at the following error: XMD% ERROR: Flashwriter application reported an error: Unable to query target part layout! Processor started. Type "stop" to stop processor Flashwriter terminating ! It would be great if someone could help me out with the problem and guide me on how to go about the bootloader. Do we need to modify the Linker script?? Thanks, YashArticle: 117458
I'm using a EPCS4 to configure my CycloneII in AS mode. >From my design I'm trying to access the contents of the EPCS via the ALTASMI_PARALLEL megafunction. Doesn't seem to work. With the scope I can see my clock on the DCLK pin, but there is something iffy about the voltage. it has a peak of 0.5V. During configuration I can see the same signal is 3V peak. What am I doing wrong? NickArticle: 117459
Greetings, Would anyone happen to know where if could purchase an FPGA development board with the Xilinx Spartan-3A XC3S1400A FPGA on it (or a socketed board capable of accepting an XC3S1400A) please? I need the 32 multipliers on the 1400A, but the starter board Xilinx sells through Avnet only comes with the XC3S700A FPGA which only has 16 usable multipliers (yes, I know there are actually 20, but since I'm doing extended precision binary multiplication I can only use 16 of them. Why on earth Xilinix incorporated a number of multipliers that isn't a power of two is beyond me!). Incidentally, the FPGA doesn't necessarily have to be a Spartan or even a Xilinx part as long as it has fast hardware multipliers. My I/O needs are minimal. All I really need are 8 switches and 8 Leds (although a hexadecimal display would be great). Basically all I need is something to display a binary factor of the RSA-704 and RSA-768 challenge numbers. ;-) Any suggestions? Thanks, RonArticle: 117460
Ron wrote: > Greetings, > > Would anyone happen to know where if could purchase an FPGA development > board with the Xilinx Spartan-3A XC3S1400A FPGA on it (or a socketed > board capable of accepting an XC3S1400A) please? I need the 32 > multipliers on the 1400A, but the starter board Xilinx sells through > Avnet only comes with the XC3S700A FPGA which only has 16 usable > multipliers (yes, I know there are actually 20, but since I'm doing > extended precision binary multiplication I can only use 16 of them. Why > on earth Xilinix incorporated a number of multipliers that isn't a power > of two is beyond me!). Incidentally, the FPGA doesn't necessarily have > to be a Spartan or even a Xilinx part as long as it has fast hardware > multipliers. > > My I/O needs are minimal. All I really need are 8 switches and 8 Leds > (although a hexadecimal display would be great). Basically all I need is > something to display a binary factor of the RSA-704 and RSA-768 > challenge numbers. ;-) > > Any suggestions? > > Thanks, > > Ron You could get a MicroBlaze development kit from Xilinx authorized distributors for $595. The Spartan-3E has 36 multipliers (which presents, it appears, 32 for your needs) and isn't geared toward I/O optimized needs like the Spartan-3A but logic optimized (or at least that's their marketing pitch). http://www.xilinx.com/onlinestore/spartan_boards.htm Maybe you can use the MicroBlaze, maybe you can't. It's a shame the board isn't offered separately. - John_HArticle: 117461
On Sat, 31 Mar 2007 13:11:28 -0700, M E wrote: > I am running Fedora 6, and I am having trouble installing ISE WebPack. > When I run the setup program it tells me that I don't have the right > version of libstdc++, so I installed the compat-libstdc++ package. Now > when I run setup, the program just quits immediately, with no error > message at all. > > Anybody have any ideas? > > Thanks, > Matt The command line tools run fine on FC6 but the GUI tools don't. The Xilinx GUIs use Motif which is unsupported in FC6. The GPL Taliban in the Fedora Project had some petty dispute about the license in Open Motif so they replaced it with Lesstif, which doesn't work. I keep a Scientific Linux 4.4 (RHEL 4.4 clone) around to do my installs on and to use if I need the GUI (which is almost never, I do everything from scripts). Once you've installed the Xilinx tools on the SL box you can rsync the Xilinx directory to your FC6 box, that's what I do.Article: 117462
John_H wrote: > You could get a MicroBlaze development kit from Xilinx authorized > distributors for $595. The Spartan-3E has 36 multipliers (which > presents, it appears, 32 for your needs) and isn't geared toward I/O > optimized needs like the Spartan-3A but logic optimized (or at least > that's their marketing pitch). > > http://www.xilinx.com/onlinestore/spartan_boards.htm > > Maybe you can use the MicroBlaze, maybe you can't. It's a shame the > board isn't offered separately. > > - John_H Thanks for the tip John_H. I've bookmarked that board and will purchase it unless I can find something cheaper or faster with H/W multipliers in the next few days. I just hope the board doesn't *require* me to use all it's fancy MicroBlaze features which would be overkill for what I need. While browsing the page you provided a link to, I also found comparisons of the Spartan-3 XC3S4000, XC3S5000, the Spartan-3L XC3S4000L, and the "Spartan-3 EasyPath" XCE3S4000 and XCE3S5000. They all have me drooling. The 4000 series has 96 multipliers and the 5000 series has 104 multipliers!!! (Although in my case, there are only 64 usable multipliers in either one). Regards, RonArticle: 117463
On Mar 30, 8:09 pm, "Peter Alfke" <a...@sbcglobal.net> wrote: > Weng, I am glad you liked the paper. Here it is:http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf > > Both Cliff Cummins and I are deeply involved in the peculiarities of > asynchr. FIFOs. When we agreed to co-author this paper, Cliff was very > suspicious that my solution would not work properly, so I had to work > very hard to (almost) convince him. That definitely improved the > paper, which was then voted "best paper of the conference"(Synopsys > User Group, 2002) > Nice memories... > Thanks > Peter Alfke > > On Mar 27, 10:03 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > > > > > On Mar 27, 7:15 pm, "Peter Alfke" <a...@sbcglobal.net> wrote: > > > > Weng, you seem to believe that there is a one-to-one corresponcence > > > between the content of a patent and the Xilinx implementation. > > > That is not necessarily so. > > > If you want to learn what a certain company is interested in, then > > > looking at patents is meaningful, (but you still suffer from the 2- > > > to-4year delay in patent issuing.) > > > If you want to design an ASIC, intimate knowledge of the FPGA may be > > > more hindrance than help. The architecture and circuit trade-offs are > > > completely different. > > > Keep studying... > > > Peter Alfke > > > ========================== > > > > On Mar 27, 6:10 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote: > > > > > On Mar 27, 3:25 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > > > > > > Is page 158 of the Virtex-5 User Guide > > > > > > http://direct.xilinx.com/bvdocs/userguides/ug190.pdf > > > > > > just too darned simple for you? Are you trying to understand the operation > > > > > of the part from the detailed silicon level tricks that may or may not be > > > > > applicable for this part of the device? I tried looking at a DDR IOB cell > > > > > patent once and found it to be interestingly disconnected from my RTL and > > > > > chip level design experience. If you are into physical level design of CMOS > > > > > chips on advanced processes you have a chance of understanding how things > > > > > come together. If all you want to know is how that chip will work for you, > > > > > use the User's Guide! > > > > > > I don't have to know about the metal casting used for the alternator in my > > > > > car to understand how the alternator works. You don't need patents to > > > > > understand the SLICE_L. > > > > > > - John_H > > > > > > "Weng Tianxiang" <wtx...@gmail.com> wrote in message > > > > > >news:1175036266.831589.180920@b75g2000hsg.googlegroups.com... > > > > > > > Hi, > > > > > > When I am turning to Xilinx Virtex-5 new chips from Virtex-II, I would > > > > > > like to know which patents filed by Xilinx to disclose the contents of > > > > > > Slice L. > > > > > > > Slice M is too complex for me to fully understand at the moment and > > > > > > just knowledge of Slice L is good enough for me to start with Virtex-5 > > > > > > as basic knowledge for it. > > > > > > > Thank you. > > > > > > > Weng- Hide quoted text - > > > > > > - Show quoted text - > > > > > Hi John, > > > > Yes, I am interested in ASIC design of Slice L and want someone's help > > > > to locate the patent filed by Xilinx that contains the contents of > > > > Slice L. I am not interested in slice M that is too complex to me now. > > > > > I have already printed the user manual you indicated and carefully > > > > read it. But it doesn't meet my curiority. > > > > > Weng- Hide quoted text - > > > > - Show quoted text - > > > Hi Peter, > > Thank you for your advice. > > > I like reading and learning. Your paper about asynchronous FIFO > > cooperated with another engineer is the best article I have read in my > > life. > > > Weng- Hide quoted text - > > - Show quoted text - Hi Peter, Yes, I had printed the paper 5 years ago and read it very carefully and the paper teaches me how to understand and handle the asynchronous situation. The paper not only won the first prize of the conference, but also won my highest comment: it is the best paper I have read in my life !!! Thank you and Cliff Cummins for the excellent paper that really made contributions to the VHDL world. WengArticle: 117464
Weng Tianxiang wrote: > > Hi Daniel, > What I mentioned were coded without any trouble. > > The trouble is each time one needs it, he must write the code for > himself, That's why there are third-party packages/libraries out there... so people who do not want to make up their own stuff can search, download and use without having to reinvent. > A broad range same function can be written one time as a VHDL standard > and after that everybody doesn't have to write it again and again. Now > in any standard VHDL library, there are too many functions that are > useless, for example, XOR(a, b). Unary AND/OR/XOR requires updating the language parsers' grammar to accept unary operations with these traditionally binary keywords and recognize their unary overloads so they can be defined by packages and libraries. Anything else that does not require changes to the language's grammar mostly can and should be handled by packages and libraries: any such additions can be done by anyone who knows how to write packages, can be used immediately by anyone interested in those extensions once they get the package and promoted for inclusion in standard libraries by anyone who sees merit in the proposed extensions. It is not necessary for everyone to reinvent the wheel or wait after standard-setting bodies for these things. BTW, "xor(a,b)" is not useless: it is the functional form for "a xor b" and very necessary for the more common binary form to work. XOR may be a reserved language keyword but it is the libraries' responsibility (browse your tools' version of ieee.std_logic_1164) to define what these actually do. If you really wanted to, you could edit your libraries to have and/or/xor/nor/... do whatever obscure twisted thing you can think of within the language's grammatical boundaries. > More general functions with variable size of std_logic_vector or > unsigned without troube to introduce another signal definition for the > temparorily set is easier to use and will be widely used. I do not quite get what you meant here... in any case, those specialized "general functions" will be built upon other library primitives and functions by most vendors and third-parties anyhow, whether they are implemented as part of a standard library or some package, standard or otherwise. Once the language parser/compiler has expanded the constructs, the results will be the same.Article: 117465
My altera FPGA is connected to a SDRAM on the prototype board. Assume the clock frequency is 100MHz, how much margin should I give to the SDRAM? 3ns? 5ns?Article: 117466
news reader wrote: > My altera FPGA is connected to a SDRAM on the prototype board. > Assume the clock frequency is 100MHz, how much margin should I > give to the SDRAM? 3ns? 5ns? Huh? Read your DRAM's specs and arrange your FPGA's timings to meet your particular DRAM's setup and hold times just like you should already be doing for any other external IC... or any clocked component for that matter.Article: 117467
How do i initialize the ram value in test bench?
And how do i read back the value.
The following codes is what i have tried but i read back the signal as
undefined ("UUUUUUUU").
Can someone help me out?
Thanks in advance.
entity Memory_Unit is
Port ( .....);
end Memory_Unit;
architecture Behavioral of Memory_Unit is
type mem_type is array(0 to memory_size-1) of STD_LOGIC_VECTOR
(word_size-1 downto 0);
signal memory : mem_type;
begin
process(clk)
begin
if clk'event and clk = '1' then
if r_write = '1' then
memory(conv_integer(address))<=data_In;
end if;
end if;
end process;
data_out<=memory(conv_integer(address));
end Behavioral;
--TEST BENCH
ENTITY testram IS
END testram;
ARCHITECTURE behavior OF testram IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Memory_Unit
PORT(
.....
);
END COMPONENT;
--Inputs
signal word0 : std_logic_vector (7 downto 0);
signal word0a : std_logic_vector (7 downto 0) := "00000000";
signal enable_sig : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Memory_Unit PORT MAP(
.....
);
spy_process1 :process
begin
init_signal_driver("word0a","/testram/uut/memory(1)",open, open, 1);
init_signal_spy("/testram/uut/memory(1)","word0",1,1);
enable_signal_spy("/testram/uut/memory(1)","word0");
wait;
end process;
tb : PROCESS
begin
wait for 1 ns;
word0a <= "00000001";
end process;
end;
Article: 117468
Shela wrote:
> How do i initialize the ram value in test bench?
Write data to it.
> The following codes is what i have tried but i read back the signal as
> undefined ("UUUUUUUU").
That is normal for a RAM. There is no reset.
-- Mike Treseler
Article: 117469I was obliged to go back to Virtex-4 Stepping Level 1. So I'm now faced with the DCM problems. Should I use the DCM_STANDBY macro for each DCM on the FPGA or only for the instantiated ones? Thanks in advance MehdiArticle: 117470
"Shela" <shelai@gmail.com> wrote in message
news:1175443545.483875.286470@p15g2000hsd.googlegroups.com...
> How do i initialize the ram value in test bench?
> And how do i read back the value.
> The following codes is what i have tried but i read back the signal as
> undefined ("UUUUUUUU").
> Can someone help me out?
>
> Thanks in advance.
>
Hi Shela,
If you instantiate the RAM e.g. RAMB16 in a Xilinx part, you can initialise
its contents. There're examples in the library guide.
HTH, Syms.
Article: 117471Mehdi, The DCM Macro is to prevent the unlikely possibility of NBTI shift in the delay lines. If the macro is used, or is the DCM is used with a clock that is present, then the DCM will never experience NBTI shift. NBTI shift requires: circuit is static (does not toggle), and power is applied, and a long time. NBTI can be accelerated by very high temperature and high voltage. Since the delay line supplies are regulated, there is no way for a customer to apply a higher voltage to the delay lines. It was thought that in some cases, a pcb is inserted, and not provisioned (such as a card in a large network). The card might remain, powered up, at a fairly high ambient temperature for a few weeks before it is needed. The NBTI shift will cause the delay line to have duty cycle distortion, which means that the maximum frequency will drop from ~700 MHz (where it normally breaks) to ~500 MHz. In order to stay inside the +/-5% duty cycle specification for distortion, we placed the "autocal" macro in the software to automatically get placed. If you use, or don't use, the DCM's, and never plan to change, or use them all below 250 MHz, then it is pretty much a don't care. If you don't use a DCM, and need to use that DCM later, and it needs to work >250 MHz, then the autocal block is a good idea (guarantees operation to specification). If you use the DCM for awhile, then the shifts are equalized, and subsequent loss of clock doesn't do anything at all (eg a 168 hour active burn in would prevent any further issues). NBTI can be baked out by powering the device off, and annealing it at 125 C for ~72 hours. Or, you can just exercise the DCM, and the NBTI shifts will equalize, and it will (eventually) work. As annoying as the NBTI was, it was a terribly obscure and minor issue, one that has never occurred in any report from the field, and one that we only saw in our qualification tests where we intentionally run things at temperatures and voltages outside of the absolute maximum specifications. For V5, NBTI was accounted for, so you do not need to worry. AustinArticle: 117472
There are lots of models out there... Did you try here? http://www.freemodelfoundry.com/model_list.html <zahra.lak@gmail.com> wrote in message news:1175353969.812266.189290@p15g2000hsd.googlegroups.com... > Hi Dear all, > > I need an implementation of a STATIC RAM with VHDL; I need this RAM to > work with/without read buffer and with/without partitioning. > > Could you please help me? > > Thank you in advance. >Article: 117473
Hi,
I'm compiling this code for microblaze gcc
void uart1_printchar(unsigned char c)
{
while( (*(unsigned char *) UARTS_STATUS_REGISTER) &
UART1_TX_BUFFER_FULL );
*(char *) UART1_TXRX_DATA = c;
}
and when using no optimization the code works OK but when using -O2 to
improve code optimization, mb-gcc generates this:
uart1_printchar:
lbui r3,r0,UARTS_STATUS_REGISTER
andi r5,r5,0x00ff
andi r3,r3,UART1_TX_BUFFER_FULL #and1
$L2:
bnei r3,$L2
sbi r5,r0,UART1_TXRX_DATA
rtsd r15,8
nop
As you can see if the UART1_TX_BUFFER_FULL bit is 1 the program enters
in infinite loop $L2
May be this is a broken mb-gcc? mb-gcc --version shows:
mb-gcc (GCC) 3.4.1 ( Xilinx EDK 8.2 Build EDK_Im.14 120906 )
Copyright (C) 2004 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There
is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE.
Thanks for any help
Manuel
Article: 117474
On Apr 1, 4:45 pm, manuel-loz...@mixmail.com wrote:
> void uart1_printchar(unsigned char c)
> {
> while( (*(unsigned char *) UARTS_STATUS_REGISTER) &
> UART1_TX_BUFFER_FULL );
> *(char *) UART1_TXRX_DATA = c;
>
> }
You need to change (unsigned char *) above to (volatile unsigned char
*) or the compiler will correctly optimize this into an infinite loop.
volatile tells the compiler that the memory may change without the
compiler knowing about it.
Alan Nishioka
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