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Andreas Ehliar wrote: >> Can you point to where? :) > > Sure, either search for LD_PRELOAD on comp.arch.fpga or > look at > http://groups.google.se/group/comp.arch.fpga/browse_thread/thread/f149e5b6028e2c70/7757eaae87bd9ac9?lnk=gst&q=ld_preload&rnum=1#7757eaae87bd9ac9 Much appreciated, thanks. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 117401
"Patrick" <grabherp23@yahoo.de> wrote in message
news:1175218265.394682.242780@y66g2000hsf.googlegroups.com...
>
>> I am a little lost, but if you are saying the ALUs share register
>> resource, then yes, you will need protection aginst same-reg writes,
>> - but you will need that anyway, for normal operation ?
>> ie a NOP should usually be a simpler, special case subset of normal
>> operations ?.
>
> I am talking about the backend, the problem I have is quite simple.
> I have 2 execution units for arithmetic and logic, 1 memory access
> unit (Load/Store) and a mutliply unit.
> Obviously all of these 4 Units would like to write data at some point
> to the registers.
> So when i only have two write ports to the register file, then I have
> a problem if
> all 4 Units wanna write data into my regfile, right?
How many instructions do you issue in one cycle?
If you only issue one instruction per cycle, then you will only have one
result per cycle to write back.
If your execution units have variable latency, then you might end up with
multiple writes to arbitrate on one clock cycle. Otherwise, if the latencies
are uniform, the problem will never arise.
Cheers,
-Ben-
Article: 117402"Daniel S." <digitalmastrmind_no_spam@hotmail.com> writes: > Martin Thompson wrote: >> "Daniel S." <digitalmastrmind_no_spam@hotmail.com> writes: >> >>> Since I do not wish to spend much time on control logic during the >>> approximation phase, I simply connect the N control signals to an >>> N-bits PRNG with a few IOBs blended in to prevent synthesis from >>> simplifying the dummy control logic and everything else >>> thereafter. Once the data/processing pipeline is in place and looks >>> good, I can start implementing and optimizing the real control logic >>> using simulations - I usually try to save as much of the control logic >>> as possible for last since relatively minor data path refinements can >>> have a major impact on the control logic and optimization >>> opportunities... I am lazy so I try to avoid moving targets whenever >>> possible. >> >> That must be where we differ then - most of my designs, its the >> control logic that takes most of the effort, especially handling error >> cases. The actual "processing" isn't usually my problem... > > Re-read my paragraph... I think you misread it: I fully agree that > control logic is indeed the most complicated part of most > designs. What I said is that I keep control for late/last to avoid > having to recode it should any significant alterations in the pipeline > become necessary due to timing/area/other constraints. > OK, fair enough - I understand where you're coming from. >> Now, off to write code which will no doubt prove me wrong within an >> hour ;-) > > "Hey Martin, there's a new feature we added to the specs... you will > have six more control bits and two extra pipeline stages to > manage. Unfortunately for you, the extra stages and controls sit smack > in the middle of the two spots that gave you so many headaches over > the last week or two." That's be the difference then - most of my current FPGA is explicitly not data-path, so there are very few changes to the data-path that are likely to cause me headaches :-) I hope... > > Of course, waiting until the data path is completed only reduces the > likelihood of late changes ruining control efforts, it does not > immunize against late changes... and it still requires a "disposable" > (minimum effort) controller for preliminary data path testing. Indeed. How about we disallow late changes :-) That's go down well! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 117403
"morpheus" <saurster@gmail.com> wrote in message news:1175226348.769913.256740@r56g2000hsd.googlegroups.com... > > When I say its "working" in simulation, I mean that through LabView I > generated a FM modulated signal sampled at 50MSPS (same as my system) > and used that as the input test vector to my design. > I am doing functional verification using ModelSim and I can see that > I*I + Q*Q outputs being computed, but they don't seem to be present in > hardware. > I am thinking there is something weird going on system wise that is > leading to this anomaly, maybo some harmonics that are leading to > cancellations or something, because I just cannot understand why the > I*I multipliers are not working > Chipscope?Article: 117404
> How many instructions do you issue in one cycle? At most 2 instructions in one clock cycle. Obviously, if there is some kind of data dependency then the second instruction will be a NOP. > If your execution units have variable latency, then you might end up with > multiple writes to arbitrate on one clock cycle. Otherwise, if the latencies > are uniform, the problem will never arise. yeah that is exactly the thing I have to consider. A memory access takes two clock cycles (EA Calculation + fetch value from datacache) whereas the multiplication takes three clocks cycles. I know that I have to consider this different latencies when issuing the instructions. The simple question that I have is how the backend of the processor has to implemented properly. My questions are: 1) Am I right to use 2 write ports to the register file? If I would use 4 I would never have the problem of a structural hazard but such write ports should be quite expensive in cost. 2) How is this implemented in hardware? Obviously my writeback stage has 4 input values (2 outputs of the Execution units, 1 output of the memory access unit and 1 output of the multiplication unit). I was thinking of 2 approaches: Each unit outputs a wr_to_regfile signal to the writeback stage if it wants to writeback values into the registers. Obviously only 2 wr_to_regfile signal can be set in a clock cycle, otherwise I would have a structural hazard. The other way I was thinking of implementing this is using some kind of resolved signal for the write port and I have to make sure that in one clock cycle only one Unit is writing a value on this resolved signal. Doese this make any sense? Cheers, PArticle: 117405
> I need to chose between the Altera Stratix II GX or Stratix III GX and > some Xilinx Virtex5 FPGA for an implementation of gigabit interface > into a multi DSP system. > > Could you suggest pro and cons between Altera and Xilinx (or maybe > others) for such design ? > If I'm trying to compare Altera with Xilinx FPGA based on those > websites, both are telling is better than the other. > Maybe you know and independent comparison table between those two ? For Stratix III GX you would have to wait a while, but for Stratix II GX there are two nice development kits available that should help you with selecting the right gigabit interface pretty quick and easy. Altera Stratix II GX Transceiver Signal Integrity Development Kit Six with full-duplex transceiver channels, brought out to SMA connectors: http://www.altera.com/products/devkits/altera/kit-signal_integrity_s2gx.html PCI Express Development Kit with Altera=AE high-speed mezzanine connectors (HSMCs) for expansion: http://www.altera.com/products/devkits/altera/kit-pciexpress_s2gx.html Grt, Karl.Article: 117406
On 30 Mrz., 02:09, "morpheus" <saurs...@gmail.com> wrote: > p.s. I don't have access to Matlab and System generator, but I'm > buying them next week. I figured, doing digital radio design without > modeling tools is like digging your own grave!!! But you have access to Octave and Scilab. Both free and powerful. Kojla SulimmaArticle: 117407
I have some questions about xilinx ISE/EDK and modelsim simulation. I'm looking for advice/pointers. I'm an reformed software guy, and my perspective is from using a lot of open source tools like linux and gcc. I've done a lot of linux kernel work so I'm familiar with big project trees, makefiles, etc... I'm sort of suprised by the state of EDA tools. I've recently spent a little time working with ISE & EDK and trying to get model to simulate a virtex 4. [To me, it seems like all the tools have their fingers in all the files and things are spread all out and it's *really* difficult sometimes to debug when a flow does not work or modelsim gives you a cryptic messages like "need to recompile blah because foo has been updated".] I've spent a lot of time with iverilog (icarus) and cver, using gtkwave and makefiles. This is a simple flow which works very reliably. But when I plug the files into ISE I end up with a large tree of who knows what (well, I do know, but you get the point). And when you add modelsim, it just gets worse. Is there any place (a boot, website,etc...) which describes what happens when I "compile libraries" in ISE or EDK? what get produced? are the files in a standard form? why do they need to be compiled? (I'm guessing that somehow magic private behavior models are secretly passed in a machine readable form to modelsim) (and why on earth the "workspace" library called "work" on the disk, why not "workspace"? is it just me?) -bradArticle: 117408
You should consider clocking your register file at twice the cpu clock speed. I'm not sure how fast you're designing your processor, but it's usually safe to say the block RAMs on an FPGA can run twice that speed. In which cases you can do twice as many accesses per clock cycle. If you're issuing two instructions per clock then you normally pipeline the datapath so only those two instructions arrive at the writeback stage so one can write one on the sooner edge of the clock and the other on the next edge.Article: 117409
On Mar 29, 7:09 pm, "John McCaskill" <junkm...@fastertechnology.com> wrote: > On Mar 29, 5:50 pm, "Tom J" <t...@pallassystems.com> wrote: > > > > > I have a C program I'm developing for the Microblaze SOC processor. > > I'm using the Xilinx Platform Studio ver. 8.2.02. > > > I had included in the project a particular *.c source file, then > > removed it. The compiler/linker/application builder insists on trying > > to compile/link this file, giving the error: > > TestApp_Memory.c:10: error: `GPIO_DataReg' undeclared here (not > > in a function) > > > " TestApp_Memory.c" is the file I've removed. I've "cleaned" > > everything I can find, but the error persists. > > > Can anyone offer suggestions short of creating a clean app (which I've > > done twice now)? > > > Tom J > > Open the .xmp file for your project and see if it still list > "TestApp_Memory.c". If it does, remove it. I have not seen this > paticular problem, but I have seen other stuff left in the *.xmp file > after I removed it from the project. Specifically, when I removed a > peripheral that I had locked the memory address assignment on, the > fact that it was locked was still in the *.xmp file. If I then added > the peripheral back in, I could not assign it a memory address until I > edited the *.xmp file. > > I think that the EDK developers did the right thing by keeping almost > all of the EDK files plain text. Only the Base Sysem Builder file is > not plain text as far as I know. I keep all of my designs under > version control with CVS, and EDK is so much better than ISE in this > regard. The few sugestions I would have for EDK in this regard are to > change the BSB file to text, stop rewritting the *.xmp file if it has > not changed, and make sure you keep date stamps, gui settings etc > segregated from the real design files. > > Regards, > > John McCaskillwww.fastertechnology.com Thanks, that seems to have solved the problem. Tom JArticle: 117410
> You should consider clocking your register file at twice the cpu clock > speed. I'm not sure how fast you're designing your processor, but > it's usually safe to say the block RAMs on an FPGA can run twice that > speed. In which cases you can do twice as many accesses per clock > cycle. Good idea! At the moment I designed the architecture so that the register file is written in the first half half of the clock cycle, whereas then on the next edge of the clock the decode stage reads the register file. In doing so, I save the forwarding from the writeback stage to the ALU. So probably the best bet would be to add an addional forwarding path and implement the WR Stage as you suggested!Article: 117411
On Mar 30, 8:47 am, "Brad Parker" <b...@heeltoe.com> wrote: > I have some questions about xilinx ISE/EDK and modelsim simulation. > I'm looking for advice/pointers. > > I'm an reformed software guy, and my perspective is from using a lot > of open source tools > like linux and gcc. I've done a lot of linux kernel work so I'm > familiar with big project trees, makefiles, etc... > > I'm sort of suprised by the state of EDA tools. I've recently spent a > little time working with ISE & EDK > and trying to get model to simulate a virtex 4. > > [To me, it seems like all the tools have their fingers in all the > files and things are spread all out and > it's *really* difficult sometimes to debug when a flow does not work > or modelsim gives you a cryptic > messages like "need to recompile blah because foo has been updated".] > > I've spent a lot of time with iverilog (icarus) and cver, using > gtkwave and makefiles. This is a simple > flow which works very reliably. But when I plug the files into ISE I > end up with a large tree of who knows > what (well, I do know, but you get the point). And when you add > modelsim, it just gets worse. > > Is there any place (a boot, website,etc...) which describes what > happens when I "compile libraries" > in ISE or EDK? what get produced? are the files in a standard form? > why do they need to be compiled? > (I'm guessing that somehow magic private behavior models are secretly > passed in a machine readable form > to modelsim) > > (and why on earth the "workspace" library called "work" on the disk, > why not "workspace"? is it just me?) > > -brad Brad, Welcome to our world. The short answer is that the software guys that write C compilers and operating systems actually use their software and to some extent understand how others use it, at least as that relates to developing software. The guys who write EDA software have no clue what hardware design is all about for the most part. As for what compilation does, this is all Modelsim, not Xilinx. I doubt you'll get very far trying to decipher the compiled code unless you want a job at Mentor :) In my opinion the Modelsim simulator runs remarkably fast considering what has to happen under the hood in your serial execution processor. There is no way an interpreted (as opposed to compiled) simulation engine could keep up with this. Good Luck, GaborArticle: 117412
Hello,
I try to compile an Avnet example (PPC BOOT Loader Design) with my
FPGA card.
when i build the projet i get the following error message:
ERROR:MDT - xilkernel () - bash.exe: warning: could not find /tmp,
please
create!
while executing
"exec bash -c "$archiver -d ../../lib/libxil.a errno.o""
(procedure "::sw_xilkernel_v3_00_a::execs_generate" line 11)
invoked from within
"::sw_xilkernel_v3_00_a::execs_generate 41132360"
ERROR:MDT - Error while running "execs_generate" for processor
ppc405_0...
Could somebody help me here please?
thanks.
Olivier.
Article: 117413Jim, The reason why I said that, is that the IBM PPC does not have a NOP. (They use 'OR R0, R0' instead). AustinArticle: 117414
On Mar 30, 4:47 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > On 30 Mrz., 02:09, "morpheus" <saurs...@gmail.com> wrote: > > > p.s. I don't have access to Matlab and System generator, but I'm > > buying them next week. I figured, doing digital radio design without > > modeling tools is like digging your own grave!!! > > But you have access to Octave and Scilab. > Both free and powerful. > > Kojla Sulimma Well, honestly I didnt know about these tools, I don't have chipscope either. I did get an A/D board from LT which has a daughter board for data collection. This is a cool boar, it attaches to the A/D board and has a FPGA on it (with a big-ass heat sink on the FPGA). Anyways, they have software to log the A/D data and compute other parameters like SINAD/ SNR, etc. I am planning to use this board to collect data and use that as input to my simulation cheersArticle: 117415
On Mar 28, 12:46 pm, Jim Lewis <j...@synthworks.com> wrote: > Ben > > > > > > > "Jim Lewis" <j...@synthworks.com> wrote in message > >news:130it10cdc7ocbf@corp.supernews.com... > > >> Please also read my paper on Accellera VHDL standard 3.0. Read up > >> on the unary usage of operators such as XOR. > >> Unfortunately due to overloading it will need a type qualifier, but > >> you will be able to use it as: > > >>>> y_xor(0) <= XOR std_logic_vector'( x(1), x(2), x(3), x(5), x(8), > >>>> x(9), x(11), x(14), > >>>> x(17), x(18), x(19), x(21), x(24), x(25), x(27), > >>>> x(30), x(32), x(36), > >>>> x(38), x(39), x(42), x(44), x(45), x(47), x(48), > >>>> x(52), x(54), x(55), > >>>> x(58), x(60), x(61), x(63) ); > > > Or I think I'd prefer: > > > y_xor(0) <= xor (x and X"B4D1B4D14B2E4B2E"); > > > Because it's much less typing. > > I like it. Just if it was more readable. > > Jim- Hide quoted text - > > - Show quoted text - Hi Lewis, Can you tell me which Xilinx ISE version starts to support the new definition you described in the form of XOR((...))? Thank you. WengArticle: 117416
"morpheus" <saurster@gmail.com> wrote in message news:1175267526.611102.281320@p15g2000hsd.googlegroups.com... > > Well, honestly I didnt know about these tools, I don't have chipscope > either. I did get an A/D board from LT which has a daughter board for > data collection. This is a cool boar, it attaches to the A/D board and > has a FPGA on it (with a big-ass heat sink on the FPGA). Anyways, they > have software to log the A/D data and compute other parameters like > SINAD/ SNR, etc. > I am planning to use this board to collect data and use that as input > to my simulation > cheers > Dear Morpheus, http://www.xilinx.com/ise/optional_prod/cspro.htm Click on 'evaluate'. HTH, Syms. p.s. I've got one of those LT boards too. V.cool.Article: 117417
Hi All, In one of my VHDL designs I have a section of code that I want different versions for synthesis than for simulation. Currently I just comment out one section and uncomment the other, but I had a rather embarassing incident yesterday where I forgot to change the comments before beginning synthesis. Ooops. I searched around a bit, but haven't found a definitive solution other than using a preprocessor. I don't think that this is a satisfactory solution. Eliminating the simulation only code is simple, the -- synthesis translate_off/on pragmas works great. Is there an equivalent for modelsim? Thanks in advance for any ideas. --Peter KlempererArticle: 117418
morpheus wrote: > Howdy, > For FM/AM demod, you require a complex baseband. I am downconverting > the IF from 1MHz to baseband by multiplying the input stream (12 bits) > from the ADC with Sin and Cosine outputs of a DDS and therefore, > generating I, Q > I am using standard 18x18 signed multipliers in Xilinx to do the > mixing. Is this right or should I use a complex multiplier? > The reason why I am asking this question is because, I had implemented > the whole datapath (Downconversion, Rate decimation, Compensating FIR) > and verified it on the bench and then implemented CORDIC for getting > FM, which never worked. > So instead I tried to do AM demod by not using CORDIC but (Sq(I) + > Sq(Q)) using standard 18x18 signed multipliers and still no AM demod > which is supposed to be simple. > Then I took the CIC and CFIR filters out and tried to do demod > straight after the mixing, still nothing. > So I'm kinda stuck here, any help will be appreciated > Thanks > -M > p.s. I don't have access to Matlab and System generator, but I'm > buying them next week. I figured, doing digital radio design without > modeling tools is like digging your own grave!!! > If your IF is complex, then you'll need a complex multiplier to multiply your complex IF by the complex LO (cos + j*sin). If, on the other hand, your IF is real-only (which I suspect it is), then you multiply the real IF by the complex LO. That uses a pair of real-only multipliers (note, this is the same as using a complex multiplier and tying the Q part of the IF input to 0). Is your LO tuned properly to get a signal to baseband? And yes, you should have Matlab or another similar tool to let you work on the algorithmic implementation before you start the actual design, as well as to model the design for verification purposes. You don't need System Generator to turn out DSP designs for FPGAs, in fact I find it gets in the way more often than not for the high speed stuff I am usually involved with.Article: 117419
I have a design where I want to have 2 DCMs, each with there own clock source come up with some known phase. The two clock sources have a fixed phase relationship. I routed a single reset signal to both DCMs. If the DCMs are a 1:1 clock ratio, no problem. However, if they are 2:1 (CLKIN_DIVIDE_BY_2 => TRUE), then often out of reset I see the phase of the output clocks will change. Even though the reset is async, I sync'ed it to each of the DCM's input clocks. This seems to have an effect and does help. The part is a Virtex 4. I have not tried it on any other device. Any ideas?Article: 117420
Martin Thompson wrote: > "Daniel S." <digitalmastrmind_no_spam@hotmail.com> writes: > >> "Hey Martin, there's a new feature we added to the specs... you will >> have six more control bits and two extra pipeline stages to >> manage. Unfortunately for you, the extra stages and controls sit smack >> in the middle of the two spots that gave you so many headaches over >> the last week or two." > > That's be the difference then - most of my current FPGA is explicitly not > data-path, so there are very few changes to the data-path that are > likely to cause me headaches :-) I hope... > >> Of course, waiting until the data path is completed only reduces the >> likelihood of late changes ruining control efforts, it does not >> immunize against late changes... and it still requires a "disposable" >> (minimum effort) controller for preliminary data path testing. > > Indeed. How about we disallow late changes :-) That's go down well! Architecture/Feature freezes are usually a good thing... but changes can still be forced by external factors: peripheral chips can go obsolete, better options (updated parts, pricing changes, etc.) can come along, provisioning/IP contracts can fall through, FPGA sizing guesstimates can come out too tight or short, etc. I worked for a couple of post-docs on a software-defined radio project some years ago. They had XC2V4000 devices they thought would be sufficient for their design but they found out, about a year into the design phase, that even the TX pipeline would (barely) not fit on a single FPGA and they ended up halving their design goals to give the RX side a decent chance of fitting in its own 2V4000. About a year after my contract ended, one of them showed me one of the first commercial derivatives from this research project which ended up halved a second time to make everything (RX + TX + some previously external bits like CPU/PPC405 and SERDES/MGT) fit in a single XC2VP70. Today, I suspect they would be easily able to pull off the initial specs with a single XC5VSX95T, assuming they would not mind going back to off-chip CPUs. I remember the docs being really &%#%@'d about the largest 4VSX being undersized logic-wise, having such a ridiculous logic-to-DSP48 ratio and no PPC/MGT while even the largest devices in the 4VFX family had way too few DSP48s, rendering both families completely useless for their application. I am certain these folks would be really happy if Xilinx decided to include a SINGLE (and no more than one) PPC405 core in all LX/SX FPGAs... an XC5VSX95T with an on-chip PPC405 would be a dream platform for them: excellent logic-to-DSP48 ratio for their application, a couple of MGTs and one PPC405 in one package to reduce external parts count. When dealing with bleeding-edge projects, tables can turn in any direction at any time for all sorts of reasons. The docs planned their design with hopes that the V4 would meet their needs by providing resource balance similar to the V2P but the preliminary V4 specs they received thoroughly terminated all such expectations. You get to see lots of interesting things when riding with people who are at the edge of their respective domains.Article: 117421
On Mar 30, 3:16 pm, "lecroy7...@chek.com" <lecroy7...@chek.com> wrote: > I have a design where I want to have 2 DCMs, each with there own clock > source come up with some known phase. The two clock sources have a > fixed phase relationship. I routed a single reset signal to both > DCMs. If the DCMs are a 1:1 clock ratio, no problem. However, if > they are 2:1 (CLKIN_DIVIDE_BY_2 => TRUE), then often out of reset I > see the phase of the output clocks will change. Even though the reset > is async, I sync'ed it to each of the DCM's input clocks. This seems > to have an effect and does help. The part is a Virtex 4. I have not > tried it on any other device. > > Any ideas? 1) Build a circuit to detect the phase relationship and re-reset one of the DCM's until they match the phase you want? 2) Don't use the CLKIN_DIVIDE_BY_2.Article: 117422
Weng Tianxiang wrote: >>> Or I think I'd prefer: >>> y_xor(0) <= xor (x and X"B4D1B4D14B2E4B2E"); >>> Because it's much less typing. >> I like it. Just if it was more readable. >> >> Jim- Hide quoted text - >> >> - Show quoted text - > > Hi Lewis, > Can you tell me which Xilinx ISE version starts to support the new > definition you described in the form of XOR((...))? Since most of the new syntaxes from this thread come from VHDL 200X language extension drafts, chances are that none of these new extensions will be included/supported in/by standard Xilinx synthesis libraries/tools until the next ISE after (and probably only if) they become official. Until then, you will most likely have to wait for the next(next(next(...))) ISE revision and hope for "early" adoption. In the meantime, you can write your own package and define your own reduction functions, it takes only a minute or two to code your own xor_reduce function... assuming you do not already have one in your vendor's libraries that does the same job. No big deal.Article: 117423
On Mar 30, 12:00 pm, "Peter Klemperer" <ftpe...@gmail.com> wrote: > Hi All, > > In one of my VHDL designs I have a section of code that I want > different versions for synthesis than for simulation. Currently I > just comment out one section and uncomment the other, but I had a > rather embarassing incident yesterday where I forgot to change the > comments before beginning synthesis. Ooops. > > I searched around a bit, but haven't found a definitive solution other > than using a preprocessor. I don't think that this is a satisfactory > solution. Eliminating the simulation only code is simple, the -- > synthesis translate_off/on pragmas works great. Is there an > equivalent for modelsim? Generate statements? -aArticle: 117424
Ray, Your suggestion makes sense. I had implemented real only multiplier as my IF is real. Regarding the output of the envelope detector, I think, due to truncation at various stages, I have had to drive the ADC, DAC really high to get some sort of an output. I need to rethink my truncation strategy at each stage as I am losing tons of dynamic range and this would be helped if I have a system modeling tool. Bless the good people at MathWorks. Thanks for all the comments -M
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