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lzh08 wrote: > thanks, i am a beginner. Start here: http://janick.bergeron.com/wtb/ -aArticle: 109276
Antti wrote: > > JTAG is sufficient, it always is on all FPGAs that have internal JTAG > TAP access primitives > > FX2 can use the JTAG pins for synced serial comm with the cores in the > FPGA. peak transfer speed should be possible at few megabit/sec when > the transfer loop is fully optimized in the FX2 code > > Antti True, but... If one uses the nifty GPIF features of the FX2, transfer rates of up to 98 MB/s are possible. (Yup, faster than USB2 will do.) GHArticle: 109277
Thanks Subroto. I'm using Quartus with Byteblaster II to program the EPC2 using JTAG. I have the EPC2 configured (using the .pof file) to then configure the FLEX10K using Passive Serial mode. (I never use the .sof file and I can't talk to the FPGA directly anyways.) But this is the problem that I'm having now: The configuration cycle state machine seems to be getting stuck in the Configuration state thereby never getting to the user-mode. I suspect this because my CONF_DONE is low and nSTATUS is high. Also, all my output pins seem to be high (or tri-stated). The FPGAs were working fine and I hadn't programmed the EPC2 more than a handful of times, but one fine morning it just randomly stopped working. I have other spare boards running the same configuration and code and they've been working fine for over a year. Thanks again, Jim Subroto Datta wrote: > Hello Jim, > > ) Configuring refers to the loading information into the FPGA. > Programming refers to loading information into the EPC2 flash memory > device. > > 2) Quartus II software uses the SOF file to configure the FPGA with a > download cable. The POF file is used to program the EPC2 device. > > Hope this helps. > Subroto Datta > Altera Corp. > > > > jasimpson@gmail.com wrote: > > I want to configure/program an Altera FLEX EPF10K30ETC144-3 + EPC2LC20 > > using files I've generated using Quartus for the same devices. I want > > to use JTAG to interface to the devices using my ByteBlaster II. I have > > carefully followed all Altera directions in generating the files and > > designing the circuit with the devices on a PCB. My 2 questions are: > > > > 1) What is the difference between "configuring" and "programming" in > > this context? > > > > 2) What file should I use to configure/program? .sof or .pof or both? > > > > Any help would be greatly appreciated. I inherited the code and PCB > > from another team that were using everything successfully. All I'm > > trying to do is reprogram a new FPGA on the same PCB with the same > > files. Unfortunately I do not have any contact with that team any more > > for help. > > > > -JimArticle: 109278
Hi,
If you have strong verification skills and have used
a language such as SystemVerilog, e, Vera, or SystemC
for verification and would like to be able to use
VHDL, you should be participating in the Accellera
VHDL enhancments effort.
Some of the tasks on our list are adding OO, interfaces,
constrained random, functional coverage, verification
data structures, ...
You do not need to be an Accellera member to participate.
Go to the webpage
http://www.accellera.org/activities/vhdl/
Under join here, select the appropriate "click here"
link (Accellera member vs. non-member).
Non-Accellera members fill in your name and information
and send the request to Lynn Horobin, Administration & Marketing.
In the big text box, ask to join Accellera VHDL TSC,
VHDL Extensions subcommittee, and VHDL Requirements subcommittee.
Note that most decisions are made by consensus of all
participants. Only contentious items are decided by a
member based vote. In the last revision, I think there
were only 3 of over 100 items resolved this way.
Of course for those of you who belong to companies with
sufficient resources, membership in Accellera will help
fund the effort (mainly LRM editing task) and is greatly
appreciated.
Best Regards,
Jim Lewis
VHDL and VHDL Standards Evangalist
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 109279CBFalconer wrote: > Dennis wrote: >> Isaac Bosompem wrote: >> >>> You can get an IBM Thinkpad (I have a P3 1.13Ghz T23, very happy >>> with it). These laptops have very good reputations. The newer >>> models (T60) seems to have dropped the parallel port for the extra >>> vent. But if you don't mind a used/slightly older model you can >>> pick up the Thinkpad T42 which has a parallel port. Also >>> considering that my ol' T23 was released in like 2001 and is still >>> working without any defects is amazing! Built like tanks these >>> laptops are. >> Go to www.ibm.com and click on IBM Certified Used Equipment in the >> Shop for column. I picked up a T30 with serial and parallel ports >> that I am very happy with for about $500. It looked like new. > > I took a look there and none of the models seem to include a > floppy. Also, none describe the presence or absence of serial and > parallel ports. I have heard horror stories about the parallel > port compatibility in IBMs, which I need for my laser printer. Any > comments? > Interesting, it looks like they shortened the descriptions since I was there last. They also no longer list things like the monitor connector and PC card slots either. All the T30 series have a serial and parallel port. I think they dropped the serial port on the T40 series. It appears that most of the information has been moved over to the lenovo site now. A bit of a pain to find the model from the IBM site and then have to go over to the lenovo site to see what all is included on a particular model. On the bright side it looks like the hardware maintenance and service manuals are still available for download on the lenovo site. I have only used the parallel port to run an LCD display which worked fine. The Thinkpads dropped the internal floppy option a while back. I have an external USB floppy which is probably not worth the price any more.Article: 109280
I have a 25 mhz onboard clock. I need a 2.5mhz clock to be generated from it. I tried using DCM with CLk_DV value of 10. but it gives me the following error. Type of C_CLKDV_DIVIDE is incompatible with type of 10. I used a counter inside the fpga to generate the clock but it gives me too much skew problems. I tried searching for application notes to add DCM into the design but couldn find one or Virtex II pro. thanks, DArticle: 109281
Perhaps a bit off topic, but I use Google to access these newsgroups and this thread is not displaying properly. Instead of showing a post number beside each post in the tree to the left, it puts the number 1 beside each one. That makes it very hard to see just which post is which in the thread. Does anyone else see this or is it just me?Article: 109282
sorry guys its solved. The value just needed to be a real instead of integer . 10.0 thanks, D dhruvakshad@gmail.com wrote: > I have a 25 mhz onboard clock. I need a 2.5mhz clock to be generated > from it. I tried using DCM with CLk_DV value of 10. but it gives me the > following error. > Type of C_CLKDV_DIVIDE is incompatible with type of 10. > > I used a counter inside the fpga to generate the clock but it gives me > too much skew problems. > > I tried searching for application notes to add DCM into the design but > couldn find one or Virtex II pro. > > thanks, > DArticle: 109283
Dennis wrote: > CBFalconer wrote: >> Dennis wrote: >>> Isaac Bosompem wrote: >>> >>>> You can get an IBM Thinkpad (I have a P3 1.13Ghz T23, very happy >>>> with it). These laptops have very good reputations. The newer >>>> models (T60) seems to have dropped the parallel port for the extra >>>> vent. But if you don't mind a used/slightly older model you can >>>> pick up the Thinkpad T42 which has a parallel port. Also >>>> considering that my ol' T23 was released in like 2001 and is still >>>> working without any defects is amazing! Built like tanks these >>>> laptops are. >>> Go to www.ibm.com and click on IBM Certified Used Equipment in the >>> Shop for column. I picked up a T30 with serial and parallel ports >>> that I am very happy with for about $500. It looked like new. >> >> I took a look there and none of the models seem to include a >> floppy. Also, none describe the presence or absence of serial and >> parallel ports. I have heard horror stories about the parallel >> port compatibility in IBMs, which I need for my laser printer. Any >> comments? >> > Interesting, it looks like they shortened the descriptions since I was > there last. They also no longer list things like the monitor connector > and PC card slots either. All the T30 series have a serial and parallel > port. I think they dropped the serial port on the T40 series. It appears > that most of the information has been moved over to the lenovo site now. > A bit of a pain to find the model from the IBM site and then have to go > over to the lenovo site to see what all is included on a particular > model. On the bright side it looks like the hardware maintenance and > service manuals are still available for download on the lenovo site. > > I have only used the parallel port to run an LCD display which worked fine. > > The Thinkpads dropped the internal floppy option a while back. I have an > external USB floppy which is probably not worth the price any more. How reliable is the USB floppy, and what sort of price is involved? Do they come with a proper Windows installation CD, or is it a system restore nonsense. Does your parallel port usage mean bit banging? Is the USB 1 or 2? -- Some informative links: news:news.announce.newusers http://www.geocities.com/nnqweb/ http://www.catb.org/~esr/faqs/smart-questions.html http://www.caliburn.nl/topposting.html http://www.netmeister.org/news/learn2quote.html -- Posted via a free Usenet account from http://www.teranews.comArticle: 109284
rickman wrote: > Perhaps a bit off topic, but I use Google to access these newsgroups > and this thread is not displaying properly. Instead of showing a post > number beside each post in the tree to the left, it puts the number 1 > beside each one. That makes it very hard to see just which post is I see it too. A problem shared is a problem halved?Article: 109285
Anonymous wrote: > Has anyone been able to get montavista4.0.1 to build a 2.6 kernel for the > mini-module? I get a build but the kernel crashes trying to allocate kernel > cache memory: I took a look at these modules and I don't see the difference between the DS-KIT-3S400MM1-BASE and the DS-KIT-MM-BASE, other than the price. DS-KIT-3S400MM1-BASE $375.00 Xilinx Spartan-3 XC3S400 Mini-Module, Baseboard, Power Supply DS-KIT-MM-BASE $195.00 Xilinx Spartan-3 XC3S400 Mini-Module Baseboard and Power Supply Is the DS-KIT-MM-BASE just a base board without the minimodule? I guess that comma is very important! Maybe they should reword this page a bit to make this more clear?Article: 109286
larwe wrote: > rickman wrote: > > Perhaps a bit off topic, but I use Google to access these newsgroups > > and this thread is not displaying properly. Instead of showing a post > > number beside each post in the tree to the left, it puts the number 1 > > beside each one. That makes it very hard to see just which post is > > I see it too. A problem shared is a problem halved? Same here, weird.. -IsaacArticle: 109287
Alan Nishioka wrote:
> rickman wrote:
> > Currently I wanted to look at how fast it might run if I redid it for a
> > current FPGA architecture using synchronous memories. I compiled it
> > for a Spartan 3 and got the speed up to 77 MHz using less than 10% of
> > an XC3S400 (315 slices). I am not impressed with the speed. I
> > expected a much larger increase and had hoped for operation at over 100
> > MHz. I checked the timing analyzer output and the signal paths are
> > pretty much what I expected, no oddball logic generation and I got
> > carry chains where I wanted them. The slow paths have a few long route
> > times, so although it may approach 100 MHz with careful floorplanning,
> > I don't think this is worth the effort compared to the >> 100 MHz CPU
> > cores you can get from the FPGA vendors.
>
> This does not surprise me. Xilinx seems to have emphasized size over
> speed of Spartan as they update it. It is very difficult to get
> Microblaze to run at 100MHz in a Spartan 3E, so 77MHz without trying is
> about what I would expect.
I tried a couple of things, but I was not able to use the floorplanner.
I get a fatal error and it crashes. This may be due to it not being
able to phone home when it tries to reach out and touch someone. My
firewall blocks it and when I click the OK button the floorplanner
crashes.
I get different failing paths depending on some of the settings I make,
like the Starting Placer Cost Table setting. But the long path is
around 13 ns and has about the same amount of logic and routing delay.
Is that normal? These paths all start with a 2 ns clock to out from
the BRAM. Then there are typically two or three routes that are longer
than 1 ns, sometimes one is longer than 2 ns. I can't tell what is
weird about this since I can't really "see" it. This path is only 5
levels of logic with no carry chain. Others are 4 level of LUTs plus a
carry chain (although typically only the last few bits of a 16 bit
adder for some reason).
Timing constraint: TS_SysClk = PERIOD TIMEGRP "SysClk" 10 ns HIGH 50%;
24616 items analyzed, 84 timing errors detected. (84 setup errors, 0
hold errors)
Minimum period is 12.915ns.
--------------------------------------------------------------------------------
Slack: -2.915ns (requirement - (data path - clock path
skew + uncertainty))
Source: InstFtch/Mram_Inst_Ram1.B (RAM)
Destination: RegPsw/DebugIrqEn (FF)
Requirement: 10.000ns
Data Path Delay: 12.914ns (Levels of Logic = 5)
Clock Path Skew: -0.001ns
Source Clock: SysClk rising at 0.000ns
Destination Clock: SysClk rising at 10.000ns
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: InstFtch/Mram_Inst_Ram1.B to RegPsw/DebugIrqEn
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tbcko 2.394 InstFtch/Mram_Inst_Ram1.B
net (fanout=0) 1.792 InstFtch/InstReg<5>
Tilo 0.608 DecodeSlow/DatStkCntl<1>21
net (fanout=19) 0.758 DecodeSlow/N23
Tilo 0.608 DecodeSlow/FlagsEn<8>11
net (fanout=6) 0.369 DecodeSlow/N56
Tif5x 0.911 DecodeSlow/FlagsEn<8>_F
DecodeSlow/FlagsEn<8>
net (fanout=0) 1.241 DecodeSlow/FlagsEn<8>
Tilo 0.551 RegPsw/_not00141
net (fanout=5) 1.079 RegPsw/_not0014
Tilo 0.608 RegPsw/_not00211
net (fanout=1) 1.393 RegPsw/_not0021
Tceck 0.602 RegPsw/DebugIrqEn
---------------------------- ---------------------------
Total 12.914ns (6.282ns logic, 6.632ns route)
(48.6% logic, 51.4% route)
Is this normal for the routing delays to range so widly and total as
long as the logic delays?
This is with nothing else in the chip, so I can only imagine that the
path delays will get longer as I combine other logic inside the chip.
I'll give it a try in a Virtex4 part over the weekend and see if that
is faster.
Article: 109288I am building a data input board that will have 1000/100/10 Base Ethernet, USB 2.0, IEE 1394, SATA, and a high speed expansion connector for future use. I am using harware chips to take care of the physical and link layers of the respective protocols. Each of these chips speaks PCI-E on the back side. I will also have a raw MGT connection using a custom protocol that is connected to a larger network of computers that also speak this protocol. I want to connect all of the hardware chips to a Virtex II Pro that has 8 MGT ports. I noticed the similarity between PCI-E requirements/operation and those for the MGTs. It appears that Xilinx has a core for this, but when I try to use the core corgen says that it's only available for Virtex 4s. Any suggestions or problems that I should be on the look-out for. ---Matthew HicksArticle: 109289
I have a 25mhz clock which I have to convert to 2.5 mhz clock and 1.25 mhz clocks. I used DCM module but I get the following warnings. I use dplain counter method but it generates excessive skew on the signals. Is there a way to remove the warnings in the DCM or to remove the excessive skew. Thanks, DArticle: 109290
I get the following warnings when I use DCM module:
WARNING:Timing:3234 - Timing Constraint
"TS_dcm_module_0_dcm_module_0_CLKDV_BUF = PERIOD TIMEGRP
"dcm_module_0_dcm_module_0_CLKDV_BUF" TS_gmii_rx_clk * 10
HIGH 50%;"
fails the maximum period check for input clock dcm_module_0_CLKDV
to DCM
my_peripheral/gig/dcm1/DCM_INST because the period constraint
value (400000 ps) exceeds the maximum internal period limit of 41668
ps. Please reduce the period of the constraint
to remove this timing failure.
WARNING:Timing:3236 - Timing Constraint
"TS_dcm_module_0_dcm_module_0_CLKDV_BUF = PERIOD TIMEGRP
"dcm_module_0_dcm_module_0_CLKDV_BUF" TS_gmii_rx_clk * 10
HIGH 50%;"
fails the maximum period check for output clock
my_peripheral/gig/dcm1/CLKDV_BUF from DCM
my_peripheral/gig/dcm1/DCM_INST because the period constraint
value (800000 ps) exceeds the maximum internal period limit of
666670 ps. Please reduce the period of the
constraint to remove this timing failure.
Device Utilization Summary:
dhruvaks...@gmail.com wrote:
> I have a 25mhz clock which I have to convert to 2.5 mhz clock and 1.25
> mhz clocks.
> I used DCM module but I get the following warnings. I use dplain
> counter method but it generates excessive skew on the signals.
> Is there a way to remove the warnings in the DCM or to remove the
> excessive skew.
> Thanks,
> D
Article: 109291dhruvakshad@gmail.com schrieb: > I have a 25mhz clock which I have to convert to 2.5 mhz clock and 1.25 > mhz clocks. > I used DCM module but I get the following warnings. I use dplain > counter method but it generates excessive skew on the signals. > Is there a way to remove the warnings in the DCM or to remove the > excessive skew. Yes. Generate clock enables using counters and run everything at 25 MHz. Regards FalkArticle: 109292
Matthew, I suggest you have a look at Lattice a forget a while of the Xilinx solution. Lattice can offer a very nice PCIe solution in their ECP2M (low cost solution for x1 and x4), and in their LatticeSC (high end up to x8). The IP core is smaller than Xilinx', and on top more robust. Best regards, Luc On Fri, 22 Sep 2006 23:24:42 -0500, "Matthew Hicks" <mdhicks2@uiuc.edu> wrote: >I am building a data input board that will have 1000/100/10 Base Ethernet, >USB 2.0, IEE 1394, SATA, and a high speed expansion connector for future >use. I am using harware chips to take care of the physical and link layers >of the respective protocols. Each of these chips speaks PCI-E on the back >side. I will also have a raw MGT connection using a custom protocol that is >connected to a larger network of computers that also speak this protocol. I >want to connect all of the hardware chips to a Virtex II Pro that has 8 MGT >ports. I noticed the similarity between PCI-E requirements/operation and >those for the MGTs. It appears that Xilinx has a core for this, but when I >try to use the core corgen says that it's only available for Virtex 4s. Any >suggestions or problems that I should be on the look-out for. > > >---Matthew Hicks >Article: 109293
rickman schrieb: > Anonymous wrote: > > Has anyone been able to get montavista4.0.1 to build a 2.6 kernel for the > > mini-module? I get a build but the kernel crashes trying to allocate kernel > > cache memory: > > I took a look at these modules and I don't see the difference between > the DS-KIT-3S400MM1-BASE and the DS-KIT-MM-BASE, other than the price. > > > DS-KIT-3S400MM1-BASE > $375.00 > Xilinx Spartan-3 XC3S400 Mini-Module, Baseboard, Power Supply > > > DS-KIT-MM-BASE > $195.00 > Xilinx Spartan-3 XC3S400 Mini-Module Baseboard and Power Supply > > Is the DS-KIT-MM-BASE just a base board without the minimodule? I > guess that comma is very important! Maybe they should reword this page > a bit to make this more clear? LOL, yes its the comman issue one includes the module other doesnt AnttiArticle: 109294
lzh08 schrieb: > thanks, i am a beginner. A testbench is what how you decide to test. You are the designer of your circuit and you know what has to be done to test it. How do you achieve it depends on your ideas and the needs of you special circuit. Sometimes a testbench looks like another circuit and is indeed synthesizable! Sometimes it is clever to use functions / procedures to generate the stimuli. Sometimes it is elegant to generate the stimuli outside of your HDL environment (you may use whatever tool you are familiar (I use ANSI C)), generate text files and read these files into your testbench. So a testbench is something that simulates the real environment for your circuit more or less accurate (better more ;-)) and what could happen to your circuit there. YOU have to think about what could happen! RalfArticle: 109295
<ghelbig@lycos.com> schrieb im Newsbeitrag news:1158966364.572122.220780@d34g2000cwd.googlegroups.com... > Antti wrote: >> >> JTAG is sufficient, it always is on all FPGAs that have internal JTAG >> TAP access primitives >> >> FX2 can use the JTAG pins for synced serial comm with the cores in the >> FPGA. peak transfer speed should be possible at few megabit/sec when >> the transfer loop is fully optimized in the FX2 code >> >> Antti > > True, but... > > If one uses the nifty GPIF features of the FX2, transfer rates of up to > 98 MB/s are possible. (Yup, faster than USB2 will do.) > > GH > sure but as those pins are not connected on s3e starterkit so it cant be used. for boards that support GPIF transfers (like cesys s3e-500 board) the GPIF is the way to go of course. I got pretty damn high sustained bandwith results with the cesys board, at least 25Mbyte/s (maybe more dont recall so precise) continous sustained transfer rate with windows host AnttiArticle: 109296
Here are a couple more data points. I changed the part to an xc4vlx25-12 and it exceeded the 100 MHz timing requirement, in fact it ran at 110 MHz. But at -10 it failed only reaching 84 MHz. On the other hand the XC3S400-5 weighed in at almost 91 MHz. So speed grade can make a moderate difference. The thing that surprised me the most is that in the Spartan 3 parts the routing was about half the delay in the worst case paths. But in the V4 part routing was over 70% of the delay in the worst case paths! So the LUTs got faster between S3 and V4, but not the routing! In fact, the routing delays were longer in absolute terms, but I'm not sure this was a valid comparison as the longest delays were on different nets between the two parts. I also found a bug in the IDE. When you change parts to evaluate differences, the Summary Report does not change the Target Device. All the other info seems to be correct, but the target stayed the same no matter what I did.Article: 109297
hi i have a digilent spartan 3e board (rev. D) and i'm trying to get the ethernet going. i'm using microblaze/ethernetlite as hardware. xilkenerl an lwip as software. everything seems to initialize fine but when i try to connect via telnet it takes a long time to connect and when i ping the board i have a lot of packet loss. i read on the xilinx webpage that in edk version 8.2 it is possible to generate sample ethernet code. since i only have the version 8.1 i really would appriciate it if somebody could do this for me and send me the code / project if possible. does anybody have some other ideas what could be wrong perhaps? thanks urbanArticle: 109298
In article <1158822468.138975.247720@h48g2000cwc.googlegroups.com>, "Antti" <Antti.Lukats@xilant.com> wrote: > ziggy schrieb: > > > In article <1158770147.385889.73830@m73g2000cwd.googlegroups.com>, > > "Antti" <Antti.Lukats@xilant.com> wrote: > [snip] > > If so, people like me will need to stick to other 'free' cores. > > Hi ziggy, > > all people like you can stick to any cores of your liking when doing > HDL or FPGA designs as the MicroFpga can *NOT* be used with > any kind of HDL flow at all. No synthesis, no place and route! > > Just take an FPGA and GCC compiler. > No FPGA vendor tools involved in the process flow: > 1) write your C program > 2) compile with GCC > 3a) merge ELF or bin into BIT or > 3b) download over JTAG or serial > > 4) your C programs runs > > in any supported FPGA > on any board or hardware it is in. > > Antti Ah, i think i understand now.. its running c-code directly on the hardware..Article: 109299
u_stadler@yahoo.de schrieb: > hi > > i have a digilent spartan 3e board (rev. D) and i'm trying to get the > ethernet going. i'm using microblaze/ethernetlite as hardware. > xilkenerl an lwip as software. everything seems to initialize fine but > when i try to connect via telnet it takes a long time to connect and > when i ping the board i have a lot of packet loss. > > i read on the xilinx webpage that in edk version 8.2 it is possible to > generate sample ethernet code. since i only have the version 8.1 i > really would appriciate it if somebody could do this for me and send me > the code / project if possible. > > does anybody have some other ideas what could be wrong perhaps? > > thanks > urban you can test out the network on s3e starterkit by taking the demo reference design and linux images from www.petalogix.com verify that it works, then you have one golden edk system that is know to work, from there continue testing with your own software Antti http://www.microfpga.com FPGA programming without HDL
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