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Hi, I need some (2 to 3) different I2C Slave models from different companies (in verilog) to test my I2C Bus .I have verified with the model given in opencores site. Please point me in this direction. -Vits.Article: 109351
Hi, I'm trying to program a prom on an Avnet development board for a Virtex4 FPGA using iMPACT. Load up the mcs file ok and hit program.... and wait.... and wait.... and wait. Let it run to about 40% done but that took over an hour and half! I stopped it because i'm pretty sure it shouldn't take that long. What am I doing wrong here? Cheers, Ben.Article: 109352
fpga_toys@yahoo.com schrieb: > Antti wrote: > > MicroFpga makes an FPGA to look like an MCU, and makes it programmable > > as it would be a normal MCU without requiring any HDL knowledge or FPGA > > implementation tools. > > Cute idea Antti !! > > Pregenerated, placed, and routed FPGA MCU's with a tool to install the > program binary into the bitstream, editing the ROM image for the MCU. > > Hobby level access to cheap FPGA parts and boards, and even useful for > embedded HW designers gun shy about FPGA development. > > .... certainly Have Fun with this one!! Hi John, thanks for cute words! I also hope it to be fun for many useage scenarios as well. The hardware features that are available largely depend on a concept xxxxx (no name yet) that is currently being developed and tested. MicroFpga is fun without xxxxx also, but the useability of hard peripheral IP cores is very limited. xxxxx will allow funtions like pwm, deltasigma dac, VGA, etc to be assigned to any IO pin of the FPGA (yes any pin of given package) under pure software control. Here are of course also compromises and restrictions in place depending the package and device selection, but there is way more fun in. More details to follow soon. AnttiArticle: 109353
The Virtex-4 data sheet states that the BSCAN module can support 4
user-data registers.
However there is an Errata sheet which states that early (ES) parts only
supported one register.
The "Virtex-4 Libraries Guide for HDL Designs" shows a BSCAN_VIRTEX4
element supporting only one user register (although it mentions USER1 &
USER2 instructions, suggesting two registers).
The library unisim_VCOMP.vhd shows:
component BSCAN_VIRTEX -- This drives two user registers
port
(
DRCK1 : out std_ulogic := 'H';
DRCK2 : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
SEL1 : out std_ulogic := 'L';
SEL2 : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO1 : in std_ulogic := 'X';
TDO2 : in std_ulogic := 'X'
);
end component;
component BSCAN_VIRTEX4 -- This drives one user register
generic
(
JTAG_CHAIN : integer := 1
);
port
(
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
So I am confused :)
Can anyone tell me just how many JTAG user registers V4 does support?
Article: 109354
Zara wrote:
Either you tell the compiler to use the >correct libraries, or you provide
the new functions. I do the second, >but the first is easier.
mb-gcc will call mb-g++ when the input is >*.cpp, and the proof is that
it is telling you that operator new is not >found. If it had been compiled
as C (ant not C++), the problem >would be a simple syntax error.
zara
Hi zara. Thanks again for your answer. I think I have understood what you mean: in fact using a my own simple makefile to compile and generate .elf file no problem at all. Using XPS environment and also trying naming .cpp file linker report always same error related to new keyword.
So perhaps there is a bug for linker invoking? Or moreover perhaps I have to set new libraries for C++ (for XPS)? anyway I try create a makefile also because I want use application in DDR RAM (I'm using a spartan 3E avaluation Board) and so I have to set linking star address for .text section and so on... But I'm finding problem to do it...
Bye, Al.
Article: 109355David R Brooks schrieb: > The Virtex-4 data sheet states that the BSCAN module can support 4 > user-data registers. > > However there is an Errata sheet which states that early (ES) parts only > supported one register. > > The "Virtex-4 Libraries Guide for HDL Designs" shows a BSCAN_VIRTEX4 > element supporting only one user register (although it mentions USER1 & > USER2 instructions, suggesting two registers). > > The library unisim_VCOMP.vhd shows: > > component BSCAN_VIRTEX -- This drives two user registers > port > ( > DRCK1 : out std_ulogic := 'H'; > DRCK2 : out std_ulogic := 'H'; > RESET : out std_ulogic := 'H'; > SEL1 : out std_ulogic := 'L'; > SEL2 : out std_ulogic := 'L'; > SHIFT : out std_ulogic := 'L'; > TDI : out std_ulogic := 'L'; > UPDATE : out std_ulogic := 'L'; > TDO1 : in std_ulogic := 'X'; > TDO2 : in std_ulogic := 'X' > ); > end component; > > component BSCAN_VIRTEX4 -- This drives one user register > generic > ( > JTAG_CHAIN : integer := 1 > ); > port > ( > CAPTURE : out std_ulogic := 'H'; > DRCK : out std_ulogic := 'H'; > RESET : out std_ulogic := 'H'; > SEL : out std_ulogic := 'L'; > SHIFT : out std_ulogic := 'L'; > TDI : out std_ulogic := 'L'; > UPDATE : out std_ulogic := 'L'; > TDO : in std_ulogic := 'X' > ); > end component; > > > > So I am confused :) > Can anyone tell me just how many JTAG user registers V4 does support? there are 4 but the way of using them is different then other families if for others there was one BSCAN primitive that allowed access to two user instructions, then V4 has 1 primitive where > JTAG_CHAIN : integer := 1 chain number selects which USERx instruction the bscan is linked to so to access all 4 USERx you instantiate 4 times the same prim with different generic for chain num now as of some V4-ES, only chain 1 is useable, others dont work so they are probably there but can not be used. notice that on some V4-ES RESET output of the BSCAN has wrong polarity that also may need special handling. the 1 chain only issue caused most problems with MDM in the v4-lx25es where defautl MDM was using non-working chain 2, so there was special workaround to set MDM ip to use chain 1 and have matching XMD also Antti http://www.microfpga.comArticle: 109356
<james7uw@yahoo.ca> wrote in message news:1159160810.953243.94120@i3g2000cwc.googlegroups.com... > Handy link for this entire thread: > http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/6d594b2ab04beb4b/e39055a323c18cd6#e39055a323c18cd6 > > I tried adding a separate level of registering in my main > line VHDL code and was trying to test it when the ModelSim > simulator died. No clock; therefore no signal processing. The > transcript > (output window) looks normal and ends up with: > > # ** Failure: Simulation successful (not a failure). No problems > detected. > # Time: 1320 ns Iteration: 0 Process: /user_logic_tb/line__94 > File: user_logic_tb.vhw > # Break at user_logic_tb.vhw line 273 > # Simulation Breakpoint: Break at user_logic_tb.vhw line 273 > # MACRO ./user_logic_tb.fdo PAUSED at line 16 > > Both post-Map and behavioral simulation show no clock and no > signal processing; all flat lines all of a sudden. > I'm looking at reinstalling. I'm using the ModelSim XE III 6.1e starter > edition. Does anyone know how to fix this without reinstalling? While it's not impossible that your Modelsim install got corrupted, I highly doubt it and therefore suggest that reinstalling is likely going to be wasted time. I've yet to 'fix' anything by re-installing Modelsim. I'd suggest debugging as to why the clock signal is not running any more. > > Also in regards to my previous message: > Xilinx tech. support said to separately register each level of logic, > since I have some lines of up to four xor statements being assigned to > a signal. I tried that, but it didn't help. ...but > still cross-connects with or without the added registers when used as a > submodule of user_logic. It didn't work because that was just a random guess on Xilinx tech supports part to try to close the service request. Since the problem of why pre and post VHDL models are acting differently has absolutely nothing to do with your source code is there suggestion has 0% chance of solving the problem....which you confirmed. I don't know how you actually posed the question to Xilinx but the question that should have been posed to them is along the lines of: "I have a pre-route VHDL simulation design file and a post-route/map/whatever VHDL simulation file that is the output of ISE version X.X. Given the same input, they don't simulate the same. Signal 'X' at time 't' is a '1' using the original design file and it is '0' using the VHDL output from ISE. I've attached the original source VHDL files, the ISE project files which includes the post-map VHDL as well as the testbench VHDL that generates the stimulus and a Modelsim '.do' file which runs each design up until time 't' where you can see that the signal 'X' coming out is different between the two models. I've confirmed that my testbench generates input stimulus to both designs that meets the input setup/hold time requirements of the final routed design. My question is 'Why are the outputs different?" Is that anything close to how you worded it? When posed in that manner, any answer/suggestion from Xilinx that does not address the question of "Why are the outputs from the two simulations different?" is irrelevant. Letting them off the hook with the suggestion of changing your source code to add registers because you have "some lines of up to four xor statements being assigned to a signal" (whatever that really means) is just trying to make you go away without addressing your real problem....but if your service request did not ask that basic question and provide them with the two simulation models that demonstrate this difference in the first place, well, they can only deal with what you provide them. > > Would anyone have some suggestions about how to write the VHDL > so it won't do that? > Yes...as pointed out earlier in the thread... 1. Write (if you don't have one already) a testbench that instantiates the original design file. Make sure all input setup and hold times in the testbench meet the timing requirements listed by ISE in the timing analysis report. 2. Run the testbench with both the original design file and the post-map file and document where the two predict different results. 3a. Open a service request to Xilinx sending them this information and ask the question as I mentioned in the previous paragraph. 3b. Debug into the post-map design file and see if you can determine the cause for the difference while Xilinx is also chewing on it. Always keep in mind that the 'pre' and 'post' simulation models are ALWAYS supposed to produce the same result given the same stimulus that meets all input timing requirements and that this is ALWAYS TRUE NO MATTER WHAT the original source code is. When this is not the case (and it does happen), as I mentioned earlier in this thread the root cause of the discrepancy is generally... 1. Testbench not meeting input setup/hold time requirements (i.e. you need to fix your testbench). 2. Improper use of types other than 'std_logic/std_ulogic'. (From earlier in the thread I thought you said there were none in your code. But if there were than again, this would be yours to fix). 3. Bug in the tool, in this case ISE. In this case, you need to open a service request and have them explain to you why 'pre' and 'post' simulation is producing different results....and not let them off with anything that causes you to change your code except to fix something along the lines of #1 or #2 that you missed. Changing the design because "some lines of up to four xor statements being assigned to a signal" is not an acceptable reason...see the previous paragraph with the 'ALWAYS' in it for justification. KJArticle: 109357
zcsizmadia@gmail.com schrieb: > I think the concept is really simple. They provide you the precompiled > hw bit file, so you don't need any vhdl development (ISE or EDK). The > only thing you need is a free mb-gcc to generate the elf file and use > dat2mem to merge elf with the precompiled hw bit file. Of course you > can only use the predefined peripherials, and Antti must provide this > precompiled hw bit file for every single supported device. > > You save a bunch of money spent on EDK and time not to worry about > setting up the peripherials As Antti said this is a alternative to > people who wants to use the FPGA as a uC (and keep the option open to > implement hw related stuff in the FPGA later on). > > But maybe I'm wrong because I haven't tried it yet. :) > > Zoltan > Zoltan, you are absolutly right! it is really a simple concept. AnttiArticle: 109358
Thanks KJ. I looked over the VHDL block of code for the Master and you are correct that I do change the writedata in the next state. However, I have corrected the slave side as well not to assert the 'waitrequest' signal as I know for sure that the 'writedata' appears after one clock cycle, therefore it was redundant for me to do this and also created this issue. Regards Pino KJ wrote: > <pinod01@sympatico.ca> wrote in message > news:1159114942.865932.288610@i42g2000cwa.googlegroups.com... > > To all, > <snip> > > The Avalon Bus VHDL code generated by SOPC builder with produces a > > VHDL stop error called: "vosq0_fifo_logic_avalonM_writedata did not > > heed wait"; > > > > where vosq0_fifo_logic is the name of the Master peripheral. > > > It means that the master changed the state of the Avalon 'writedata' output > (even if only a glitch) while the 'waitrequest' input was still > active....can't do that, address, command (i.e. read and write) and > writedata must all remain stable if waitrequest coming in is active > > KJArticle: 109359
Antti wrote: > John McGrath schrieb: > > > Jon Beniston wrote: > > > > I don't understand the idea of using post syn timing. Is that at all > > > > accurate? > > > > > > Sometimes it is close, sometimes it is woefully inaccurate. > > > > > > > Why not let it do a PAR and see what kind of real results you get? > > > > > > It's the only way to know. > > > > > > Cheers, > > > Jon > > > > > > True - and as soon as I know you will know! - I left it PARing as I > > left the office, and won't see the result myself until I am back > > monday. However, from the post MAP timing, it looked good. I also put a > > clock constraint of 200MHz on it (just to see). I'm curious myself. I > > think the result would be more useful if I included a few more of the > > core features, like debug logic, jtag, multiplier support etc. I just > > left it with the defaults. > > > > Regarding the verilog2001 support - XST seems to have clogb2 support, > > but just there seemed to be some restrictions on where it can be used - > > it could be because the RTL code is using it in a way that violates the > > strict rules on the LRM, or it could be XST simply needs to allow the > > use of this function more liberally (like in a preprocessing function > > when reading the RTL, as its used as a constant), who knows. All I know > > is it was not much effort to make it work, so hardly makes XST unsable > > for synthesis of this core. This info mught help a few people out who > > do not have access to alternatives....but if you really want to knock > > synthesizers..check out design compiler in an asic context *shudder*. > > whah? it hasnt finished? you should have used relaxed timing > constraints. > > A microblaze design with all CPU options enabled and with Floating > Point unit included, targetting XC3S4000 using 489 IO's and having > 192KB used local memory runs within some minutes until bitstream done. > (takes 14% BTW from s3-4000) > > I bet your LM32 test desing is far less complex > > getting 200MHz in slowest speed V5 seems unlikely, OpenFire demo design > did pass 200MHz in fastest V5 after a few xplorer runs. > > so I bet the LatticeMico32 want pass timing on 200Mhz > > Antti Sorry to give the wrong impression about how long it took - PAR did not take that long, it was just the case that I started PARing right before leaving the office on Thursday evening, and was not due back in to see the result until today - The actual PAR time was 33mins with the 200MHz constraint. And now for the result: 182MHz post PAR timing. Again - this was just a bare-bones system - purely proof of concept that XST could do it! I did not use any techniques to improve the timing result, standard levels of all options, and no xplorer. It took 3% of a V5 LX50 device. It would be interesting to see what could be seqeezed out of this design and speed grade with the right options, or maybe using PlanAhead, but I'll leave that to others.Article: 109360
pinod01@sympatico.ca wrote: > Thanks KJ. I looked over the VHDL block of code for the Master and you > are correct that I do change the writedata in the next state. However, > I have corrected the slave side as well not to assert the 'waitrequest' > signal as I know for sure that the 'writedata' appears after one clock > cycle, therefore it was redundant for me to do this and also created > this issue. > > Regards > Pino I'm not quite sure but I take it that there is still a problem....and I'll repeat myself here by saying the error is reported when the master changes 'writedata' even though the input signal 'waitrequest' is asserted. Take a look at the waitrequest input at the master when the error is being reported. You seem to also be making some incorrect assumptions about how the Avalon bus is working when you say "I have corrected the slave side as well not to assert the 'waitrequest' signal as I know for sure that the 'writedata' appears after one clock cycle". Look at the Avalon specification, the only time that 'writedata' going into a slave (or out of a master for that matter) is when the write signal is active. There is no 'one clock cycle later' if by 'later' you mean one clock cycle after 'write' has been asserted. If a slave needs more than one clock cycle to complete the write (or read) it must set waitrequest active on the same clock cycle that it receives the write signal. If it does not then the write (or read cycle) completes and there are no guarantees about what the slave will see on writedata on the next clock cycle. Also, remember that the master and slave do not talk directly to each other. They talk to the 'Avalon fabric' which in turn is what talks to the master and slave. So even if the slave is not setting the 'waitrequest' output that does not imply that the 'waitrequest' input to the master is not set. Drill down into your master device at the point where you get the error and I think you'll see that the waitrequest input to the master is indeed set. If the slave device that you're talking to at that point does NOT have it's waitrequest output set at this time as well, then Avalon is generating the waitrequest input to the master...and it will do this based on PTF settings in the slave component. Take a look at the PTF file for the slave and see if how wait states are defined. If the slave has a waitrequest output then that setting should be set to something like 'peripheral_controlled' (or something to that effect). If the slave has a waitrequest output then what you should not see is some integer number (like '2') since this would mean that the slave device requires exactly 2 wait states and that there is no waitrequest output. If on the other hand the slave has no explicit waitrequest output then you would expect to see a fixed number in the PTF file for the number of wait states since that is what Avalon will use to generate the waitrequest input to the master. One last thing to keep in mind is that you make changes to the class.ptf file for a component you pretty much have to delete the component from the SOPC Builder design and re-instantiate it (and then of course re-connect everything). If you don't you'll run into the situation where the component's class.ptf file says one thing but the system.ptf file from SOPC Builder has something else Since the system.ptf file is what gets used to actually generate the final logic you'll be hosed. For a 'simple' change, and only if you're comfortable understanding the PTF file format, the other way is to simply edit both the component's class.ptf file and the system.ptf file. KJArticle: 109361
I answer to my own post, anyway the mismatch behavioral vs SynplifyPro was simply due to the initilzation reset (GSR) that is applied only on the post-Translate model (not on the behavioral model). The mismatch behavioral vs XST remains and is probably one more bug of XST that i have no time to identify. tullio tullio ha scritto: > We are designing a comunication system on a Spartan3 with a lot of data > processing and buffering. > We have several simulation mismatches: > behavioral simulation gives results identical to Post-translate (with > XST8.2.02 and option Keep Hierarchy: yes) > But simulation of Post-translate with XST and option Keep Hierarchy > off, gives different results; it's only a few different vectors over a > thousand, but still unexplicable to me. > We tried to compile with Synplify Pro, default settings; we did another > post-translate simulation and the results are still different from all > previous cases (again only a few vectors over a thousand). > > Any experience with that ? > We paid attention to signed logic issues (see thread "behavioral vs > post-P&R simulation mismatch" on Aug 30, 2006). > We paid attention to crossing the clock domains. The clock structure > is (in Verilog) > > ///////////////////////////////////////// > ... > input clk80, // 80 MHz clock. > ... > always @(posedge clk80) CE40 <= ~CE40; > BUFG BUFG_clk40 (.O(clk40), .I(CE40)); > > ////////////////////////////////////////////////////// > > the reason for doing that, is we need a 40 MHz signal (CE40) to be used > as an enable in the 80MHz domain. This signal must be in phase with > clk40, and must not creates setup/hold violations when clocked by clk80 > (this could happen using a DCM).Article: 109362
Hi Vits, I tested the I2C master with the testbench. The signals generated were correct. I also implemented the cores in an FPGA. I've managed to use the core to communicate with slave devices using FPGA as the master. So, I do believe that the I2C master is correct. I didn't use any microprocessor or microcontroller to control the I2C master. Instead, I created a state machine that takes in my instructions and decode it for the I2C master to process. The state machine also waits for the nack/ack signals that the I2C master receives from the slave (this, I noticed, took the longest in hardware). Hope this helps. -Markus vits wrote: > Hi markus, > O ya ,that has helped me a lot. actually i tried to test with a eeprom > slave. > But the test is not giving the correct results.may be there may be > something wrong with the > eeprom model.i got it from net. > vitsArticle: 109363
If I try to run the 'Implement Design' process in my project, the ISE errors out immediately. There is NO message in the console...no indication of what may have failed. The synthesis reports OK. The only warnings in that are for ignored delay values and one unconnected port at the top level. These are fine. I have checkd the command log and the only one the ISE invoked before the error was the xst stuff. It didn't even get to the translation phase. However, it reports 'Process "Synthesize" completed successfully'. Right after it says this, the error icons appear next to 'Implement Design' and the ISE stops. Any thoughts?Article: 109364
motty wrote: > If I try to run the 'Implement Design' process in my project, the ISE > errors out immediately. There is NO message in the console...no > indication of what may have failed. The synthesis reports OK. The > only warnings in that are for ignored delay values and one unconnected > port at the top level. These are fine. > > I have checkd the command log and the only one the ISE invoked before > the error was the xst stuff. It didn't even get to the translation > phase. However, it reports 'Process "Synthesize" completed > successfully'. Right after it says this, the error icons appear next > to 'Implement Design' and the ISE stops. > > Any thoughts? > Did your license expire? I seem to recall something similiar. I only figured out what was happening when I ran the command manually, and on the shell it printed out the error. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 109365
I tried using clock enables but still no luck . It still gives me warning indicating excessive skew on the clocks. I also get following warning : This design either uses more than 8 clock buffers or has clock buffers locked into primary and secondary sites. Since only one clock buffer output signal from a primary / secondary pair may enter any clock region it is necessary to partition the clock logic being driven by these clocks into different clock regions. Even some signal which are not clocks but just enables which drive state machines get slotted as clock signals. Why is that ? How can I prevent that from happening? Thanks, D Falk Brunner wrote: > dhruvakshad@gmail.com schrieb: > > I have a 25mhz clock which I have to convert to 2.5 mhz clock and 1.25 > > mhz clocks. > > I used DCM module but I get the following warnings. I use dplain > > counter method but it generates excessive skew on the signals. > > Is there a way to remove the warnings in the DCM or to remove the > > excessive skew. > > Yes. Generate clock enables using counters and run everything at 25 MHz. > > Regards > FalkArticle: 109366
Well, I should have tried this before, but I 'Cleaned the Project Files' and all is well. I am pretty conditioned to do that in the EDK anytime I see weird things, but have not had to do it in the ISE yet. No license issue. I was going to try a manual shell command too. I guess the full set of error messages isn't necessarily piped up to the ISE GUI. Thanks!Article: 109367
Hi All, Does anyone know what "SE" and "PE" stand for in ModelSim? "Standard Edition"? "Special Edition"? "Professional Edition"? "Plus Edition"? I know that "XE" stands for "Xilinx Edition". Thanks, -James From removethisthenleavejea@replacewithcompanyname.co.uk Mon Sep 25 11:24:08 2006 Path: newssvr29.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newsfeed.telusplanet.net!newsfeed.telus.net!news-east.rr.com!news.rr.com!peer01.cox.net!cox.net!border2.nntp.dca.giganews.com!nntp.giganews.com!newspeer1.nwr.nac.net!solnet.ch!solnet.ch!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!demeter.uk.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga References: <1159207850.731113.324130@b28g2000cwb.googlegroups.com> Subject: Re: Does anyone know what "SE" and "PE" stand for in ModelSim? Date: Mon, 25 Sep 2006 19:24:08 +0100 Lines: 21 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2869 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2962 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 10d225c833312bc56931093e772e509060103c08223e381823e1803245182162 NNTP-Posting-Date: Mon, 25 Sep 2006 19:35:14 +0100 Message-Id: <1159209314.47510.0@demeter.uk.clara.net> Xref: prodigy.net comp.arch.fpga:120278 Pe is Personal Edition I believe. Se might be System Edition. Se is a lot more expensive than Pe. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <james7uw@yahoo.ca> wrote in message news:1159207850.731113.324130@b28g2000cwb.googlegroups.com... > Hi All, > > Does anyone know what "SE" and "PE" stand for in ModelSim? "Standard > Edition"? "Special Edition"? "Professional Edition"? "Plus Edition"? > I know that "XE" stands for "Xilinx Edition". > > Thanks, > -James >Article: 109368
The section about "Language Dialect" (page 100) in the GNU Compiler Tools
chapter of the Embedded Systems Tools Reference Manual is probably of use to
you.
"Alfmyk" <alfmyk@hotmail.com> wrote in message
news:ee9f05b.2@webx.sUN8CHnE...
> Hi. Thanks Zara & Vasanth.
>
> Now I'm using EDK 8.1.02i and so I assume it's possible run C++ routines.
> Nevertheless using a very simple class: class Cliente { public: char
> name[20]; char surname[20]; void insert_name( ); };
>
> and generating an object with new keyword: Client *client; client = new
> Client( );
>
> I get this error: undefined reference to `operator new(unsigned long)'
> collect2: ld returned 1 exit status make: *** [Application/executable.elf]
> Error 1
>
> should I use the mb-g++ compiler instead of mb-gcc? What else?
>
> Thanks again.
>
> Regards, Al.
Article: 109369Adnan schrieb: > Hello experts, > > I am a final year student and working on my senior design project. I > need PCI Master core and unfortunately I cannot buy any licensed core > because of their high price. I have seen opencores.org PCI bridge but > it has few problems > 1. Its test bench is too complex to understand. I was expecting some > black box sort of interface. > 2. Its driver is written in linux, but I have developed my software > part in MS Visual C-6, soI need windows driver. > > If someone has cleaned and simple version of opencores PCI core or > someother PCI core please send me that at madnan.rashid@gmail.com. I > also need driver preferrably for windows. Your timely help will enable > me to solve my problems. And yes, I will acknowledge source of this PCI > core and driver in my project report. PCI drivers are completely independent of the PCI core used. You can use the free MEMACCESS library from zealsoft with any PCI core, including the one from open cores. Gaisler research has a GPLed PCI core. But I doubt that the test bench is simpler than the open cores testbench. http://www.gaisler.com/cms4_5_3/index.php?option=com_content&task=view&id=139&Itemid=51 But what do you need the testbench for? The core has been tested. As long as you do not modify it.... Kolja SulimmaArticle: 109370
Plenty Expensive and Super Expensive! One time I was being pitched by the local salesman and he made the mistake of trying to justify the added cost as being the expense of maintaining a second system with a higher degree of optimization. It occured to me that if I were going to sell a high priced and a low priced version of the same SW tool, the last thing I would want to do would be to have two different versions of the code! To keep my costs down I would do like the VCR vendors do, have one version of the system and with the flick of a switch (or a bit in this case) the system would be "dumbed" down. I pointed that out to him and he stopped talking about the added SW maintainance cost of the SUPER expensive version. John Adair wrote: > Pe is Personal Edition I believe. Se might be System Edition. Se is a lot > more expensive than Pe. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > <james7uw@yahoo.ca> wrote in message > news:1159207850.731113.324130@b28g2000cwb.googlegroups.com... > > Hi All, > > > > Does anyone know what "SE" and "PE" stand for in ModelSim? "Standard > > Edition"? "Special Edition"? "Professional Edition"? "Plus Edition"? > > I know that "XE" stands for "Xilinx Edition". > > > > Thanks, > > -James > >Article: 109371
The board that Lattice sells come with virtually no docs, so I don't even consider that a product. I found one from a European company MSC, but it is not clear if the docs are in English or not. They have web pages in both English and German, but the PDF advertisement is in German only - CPLD-Eval-Board. Anyone know if this product is documented in English? Are there any other eval boards out there for the ispMACH4000 parts?Article: 109372
http://www.freemodelfoundry.com/ has some models of i2c controlled devices. Not sure whether they are slave devices. Take a look. If you make it work with Xilinx Ise Simulator let me know. "vits" <vittal.patil@gmail.com> wrote in message news:1159176429.670095.279080@h48g2000cwc.googlegroups.com... > Hi, > I need some (2 to 3) different I2C Slave models from different > companies (in verilog) > to test my I2C Bus .I have verified with the model given in opencores > site. > Please point me in this direction. > -Vits. >Article: 109373
I am having a very stange problem with my state machine. The state machine turns dead after some uncertain time(20min ~ 2 days) and all outputs of the statemachine are 0. All other logics in the chips work properly at the same time. The state machine is very simple, only with 8 states. I tried with StateCAD and programming manually with VHDL and they behave the same. Anybody know what's possibly the problem? I have been working on this for a week and really cannot find a way out. Thanks.Article: 109374
motty wrote: > Well, I should have tried this before, but I 'Cleaned the Project > Files' and all is well. I am pretty conditioned to do that in the EDK > anytime I see weird things, but have not had to do it in the ISE yet. > > No license issue. I was going to try a manual shell command too. I > guess the full set of error messages isn't necessarily piped up to the > ISE GUI. > > Thanks! Doh! I spoke too soon. Somewhere along the way, the error ocurred again. I tried cleaning the project files and no joy. So I had to make a new project and pull all the files in again. This is really a pain in the arse. I have not had any problems before. Service packs are up to date as well. We just got our license for 8.2, but I am wary of upgrading. I saw a similar post where no process would run in ISE. It just errored out before doing anything. It too said making a new project was the workaround. Fark!
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