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Ray Andraka wrote: > I'm trying to understand what help you are seeking. After perusing this rather umm...well, let's just say after perusing this thread I would simply ask you (Ray that is) WHY? KJArticle: 109551
if you don't like PowerPC DDR controller generated by EDK, you have to use MIG tool to generate DDR controller which can interface with the rest of fpga. akcooper8@gmail.com wrote: > I need help on how to use the EDK DDR memory controller in ISE to write > to/from ram and fpga directly. I have implemented the FFT provided by > Xilinx Coregen but need a faster memory controller to streamline the > FFT process rather than the EDK-PowerPC DDR controller in C that is > provided. Any help is appreciated. > > Thanks > > AshwinArticle: 109552
I ran into this same dilema using a xilinx xup board. If you have a DDR core you can integrate with ISE, I would recomend adding a couple GPIO IP blocks to your EDK design and then exporting to ISE so you can connect the DDR core and whatever logic you need to support it. akcooper8@gmail.com wrote: > I need help on how to use the EDK DDR memory controller in ISE to write > to/from ram and fpga directly. I have implemented the FFT provided by > Xilinx Coregen but need a faster memory controller to streamline the > FFT process rather than the EDK-PowerPC DDR controller in C that is > provided. Any help is appreciated. > > Thanks > > AshwinArticle: 109553
It will be for NetFPGA : http://klamath.stanford.edu/netfpga/ -Greg Matthew Hicks wrote: > I looked at your Stanford page, what project is this going to be used for? > You said that the results will be open sourced, are there any parts of your > past projects open? > > > ---Matthew Hicks > > > "Greg Watson" <gwatson@stanford.edu> wrote in message > news:efecqi$1m8$1@news.Stanford.EDU... >> Hi >> >> We are planning to use MIG to generate a DDR2 interface for a V2Pro30 >> design, but I'd like to know if anyone has done this successfully already? >> The MIG tool doesn't seem to have the quality level of other Xilinx tools >> and that makes me a bit nervous for something as timing critical as a DDR2 >> controller. >> >> We are using MIG 007 Rel 6 (as it's the recommended version for V2P). So >> far the only irritations we have encountered is that it forces the use of >> specific DCMs and requires the user to reselect every option each time it >> is invoked (no saving of current design). >> >> We plan to run 1 32 bit controller at 200MHz (400 Mb/s/pin) with Micron >> MT47H16M16. >> >> We would like to hear of any experiences with MIG and DDR2 and V2P, if >> only to convince us that this is doable. Our final design should be open >> sourced and available to all, if that encourages you to be open about your >> experiences. >> >> If you would rather contact me directly I am at gwatson@stanford.edu >> >> Thanks >> >> Greg Watson > >Article: 109554
Dolphin wrote: > Hello, > > In my future design I could win a lot of pins if I could drive a bus at > 160MHz. Because of bank restrictions and because this bus is connected > to a CPLD, I will have to use LVTTL. > Has anybody tried driving a bus in LVTTL at 160MHz? > > I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has > LVDS CPLDs but only the large CPLDs support LVDS inputs. > > I am afraid that this bus will have a lot of EMI/EMC problems. What do > you think of it, should series termination be adequate to limit the > EMI/EMC problems? You mentioned speed, but forgot distance ? How far does this have to go - sounds like the CPLD is a (remote?) slave ? You can get small LVDS-LVTTL transcievers, plus you can also use dual data lines, to halve the clock rate. ( see winbond for dual-data SPI memory, they spec to 150MHz ) -jgArticle: 109555
Just to clarify the situation: Antti had ordered the evaluation board for Virtex-5, and Xilinx has acknowledged and I suppose has shipped the order on Sept 27. Now let's see how soon it reaches Antti in Munich, Germany, (Antti please report to the newsgroup when it arrives. It should not take weeks, the airplane hasn't that much fuel!) Also, the present version of EDK already supports that board (with minor wrinkles). Let's then listen to the continuation of this story... Peter ====================== Antti wrote: > Antti schrieb: > > > Peter Alfke schrieb: > > > > > You can order Virtex-5 devices from your distributor now, and he will > > > offer short delivery times. > > [...] > > > Peter Alfke, who has been working on and with these parts for over a > > > year. > > > [my own ***** snipped] > > until both the silicon AND tools are available there is no supprort. > > So no matter how ready we may be for Virtex-5, and belive me some > > of us really are - we are not really able todo any real work until > > tools support is also made available by Xilinx. > > > > EDK 8.1 SP1 has Virtex-5 MicroBlaze 5.00.a and 5.00.b in it > it is just labelled as "early access" but its readily available. > there is some minor mess with MPD files like FSL bus is not > supported (eg requires manual edit of the MPD) but otherwise > the Virtex-5 can be targetted ok on EDK 8.1 SP1, eg no need > to wait for SP2 > > here is the picture of the EDK system with Virtex-5 > > http://www.microfpga.com/joomla/index.php?page=shop.browse&category_id=12&option=com_virtuemart&Itemid=26 > > AnttiArticle: 109556
Dolphin wrote: >Hello, > >I am considering to use Spartan 3 devices on our new board. Xilinx >recommends XCF04S and XCF08P devices for configuration of a Spartan 3 >1000. Does anybody know other and cheaper configuration solutions for >this FPGA? > > Well, I'm always behind the curve on this stuff, but SST has some VERY cheap flash serial memories. I'm using their 1 Mbit serial flash to config a Spartan 2E chip. I had to make my own device programmer - basically a single CMOS chip used as a level translator and a page of C code to write/read it through a PC parallel port. And, I had to make up a minimal circuit to send a read from address zero command into the chip. That takes two SSOP packages on the board next to the FPGA. These chips can handle up to 25 MHz in their ordinary mode, and up to 32 MHz if you tolerate a one byte delay before output. Nice that Xilinx will waif for a byte of FF before starting to interpret the config bitstream. I think the 1 MBit chip is about $1.50 in small quantities, I get them from Mouser. They have larger, I don't remember how big they go. JonArticle: 109557
Is there a good reason to use 'std_logic' by default rather than 'bit'? I started off doing so, then thought it would be more thorough to define pure logic in terms of bits and save std_logic for stuff that would be anything other than 0 or 1. I then found my compiler complaining about all sorts of stuff. Problems trying to use a bit_vector as a counter, or using rising_edge() on a bit, and so on. I'm inclined to just use std_logic as my fundamental signal. Opinions?Article: 109558
Kryten wrote: > Is there a good reason to use 'std_logic' by default rather than 'bit'? > > I started off doing so, then thought it would be more thorough to define > pure logic in terms of bits and save std_logic for stuff that would be > anything other than 0 or 1. > > I then found my compiler complaining about all sorts of stuff. > > Problems trying to use a bit_vector as a counter, or using rising_edge() on > a bit, and so on. > > I'm inclined to just use std_logic as my fundamental signal. > > Opinions? > > One very good reason is for IO compatibility with other IP. The standard is to use std_logic,std_ulogic, std_logic_vector and std_ulogic_vector for the types on all I/O. That way, your component can be used in a larger design regardless of what library that design uses, and same for instantiating components within your design.Article: 109559
I have a code which has 3 state machines .The code works fine. But if I add any other hardware to the design like adder and enable the adder through a signal in the the state machine then the code doesnt work. Should I use buffer for all the the enable signals before giving it to the state machines? What could be the problem? thanks, DArticle: 109560
I think the FIFO16 is not the killer of the simulation. i saw the empty flag and full flag toggle. I run the the synthesis by xst and precision. and generate the time simulation model and see the difference. Here is the error send by the memory model. time simulation model create by using precision as synthesis, i got the following error: # ddr2_test_tb.X16_0_7.cmd_addr_timing_check: at time 208548390.0 ps ERROR: tIH violation on ADDR 10 by 304.0 ps # ddr2_test_tb.X16_0_0.main: at time 208548403.0 ps ERROR: tIS violation on ADDR 10 by 237.0 ps i got lots of them then it just stop the simulation. time simulation model create by using xst as synthesis, i got the following error: # ddr2_test_tb.X16_0_7.cmd_addr_timing_check: at time 208548373.0 ps ERROR: tIH violation on RAS_N by 319.0 ps # ddr2_test_tb.X16_0_6.cmd_addr_timing_check: at time 208548373.0 ps ERROR: tIH violation on RAS_N by 319.0 ps # ddr2_test_tb.X16_0_5.cmd_addr_timing_check: at time 208548373.0 ps ERROR: tIH violation on RAS_N by 319.0 ps # ddr2_test_tb.X16_0_4.cmd_addr_timing_check: at time 208548373.0 ps ERROR: tIH violation on RAS_N by 319.0 ps # ddr2_test_tb.X16_0_0.main: at time 208548399.0 ps ERROR: tIS violation on RAS_N by 224.0 ps i also try to look at internal signal. cinflict_detect, ctrl_dummy_wr_sel, ctrl_dummyread_start never went high. The init_count is 1. Do anyone have some idea that make the controller working. Thanks! Wai Shan Joseph Samson wrote: > waishanl@gmail.com wrote: > > Hi! i am having problem to communicate between virtex4 fx60 to 512 > > SODIMM. I use the MIG1.6 to generate a controller. I add one module > > into the design, change some names and run ModelSim. The simulation > > looks fine. So, i use the ICE tools to get my bit file. When i check > > all the report, I saw the map report have the follwoing message: > > > > WARNING:MapLib:851 - Your design is using FIFO16 primitives, Please > > note that > > there are additional requirements for the FIFO16 to guarantee full > > functionality. For more information regarding requirements for the > > FIFO16 > > primitive, please see Answer Record 22462. > > > > is that going to cause me fail on the design? I didn't fine any .edn or > > ngc file in the folder that MIG generate. > > > > I also run the time simulation, it didn't match with the funcational > > simulation. Seems like signal start fail in 200ns. Am i missing > > anything? > > > > In addition, I chipscope the signal. It seems like data did get in the > > fifo. But the controller never request a read. Any ideas? > > There has been quite a bit written lately about DDR2 and MIG in this > newsgroup. Search for ddr2 and MIG. I recommend replacing the FIFO16s > with FIFOs generated by CoreGen that don't use the FIFO16 primitive. I > had problems with the address/command FIFO. It would be empty, but still > indicate that it had data, so the same memory cycle would run forever. > > --- > Joe Samson > Pixel VelocityArticle: 109561
Al: I am also using an XUP (V2P) board and thought about what you are proposing. How would I go about accessing the EDK DDR controller from ISE without having to go through the PowerPC? Basically, I want one RAM controller that I can access from EDK and ISE. Al wrote: > I ran into this same dilema using a xilinx xup board. If you have a > DDR core you can integrate with ISE, I would recomend adding a couple > GPIO IP blocks to your EDK design and then exporting to ISE so you can > connect the DDR core and whatever logic you need to support it. > > akcooper8@gmail.com wrote: > > I need help on how to use the EDK DDR memory controller in ISE to write > > to/from ram and fpga directly. I have implemented the FFT provided by > > Xilinx Coregen but need a faster memory controller to streamline the > > FFT process rather than the EDK-PowerPC DDR controller in C that is > > provided. Any help is appreciated. > > > > Thanks > > > > AshwinArticle: 109562
I think the FIFO16 is not the killer of the simulation. i saw the empty flag and full flag toggle. I run the the synthesis by xst and precision. and generate the time simulation model and see the difference. Here is the error send by the memory model. time simulation model create by using precision as synthesis, i got the following error: # ddr2_test_tb.X16_0_7.cmd_addr_timing_check: at time 208548390.0 ps ERROR: tIH violation on ADDR 10 by 304.0 ps # ddr2_test_tb.X16_0_0.main: at time 208548403.0 ps ERROR: tIS violation on ADDR 10 by 237.0 ps i got lots of them then it just stop the simulation. time simulation model create by using xst as synthesis, i got the following error: # ddr2_test_tb.X16_0_7.cmd_addr_timing_check: at time 208548373.0 ps ERROR: tIH violation on RAS_N by 319.0 ps # ddr2_test_tb.X16_0_6.cmd_addr_timing_check: at time 208548373.0 ps ERROR: tIH violation on RAS_N by 319.0 ps # ddr2_test_tb.X16_0_5.cmd_addr_timing_check: at time 208548373.0 ps ERROR: tIH violation on RAS_N by 319.0 ps # ddr2_test_tb.X16_0_4.cmd_addr_timing_check: at time 208548373.0 ps ERROR: tIH violation on RAS_N by 319.0 ps # ddr2_test_tb.X16_0_0.main: at time 208548399.0 ps ERROR: tIS violation on RAS_N by 224.0 ps i also try to look at internal signal. cinflict_detect, ctrl_dummy_wr_sel, ctrl_dummyread_start never went high. The init_count is 1. Do anyone have some idea that make the controller working. Thanks! BerryArticle: 109563
"Ray Andraka" <ray@andraka.com> wrote in message news:BZYSg.617$XX2.166@dukeread04... > One very good reason is for IO compatibility with other IP. The standard > is to use std_logic, std_ulogic, std_logic_vector and std_ulogic_vector > for the types on all I/O. That way, your component can be used in a > larger design regardless of what library that design uses, and same for > instantiating components within your design. Thanks Ray, I thought it might be something like that. I shall mod the code somebody gave me so that if I do get type conflicts I shall convert the bit signal to std_logic.Article: 109564
Thanks for the extra info, guys. Am now stuck on a ModelSim path problem that has a plain user (me) stuck dead in his tracks. I am starting a new thread for that.Article: 109565
Hi all,
I am using ModelSim III XE 6.1e starter edition with ISE 8.2.03i and I
am trying to do post-par simulation having built everything
successfully. I have the checkmark in the green circle for "Generate
Post-Place & Route Simulation Model". In the Sources Window I select
"Post-Route Simulation" and get the ModelSim Simulator in the Processes
Window, with "Simulate Post-Place & Route Model" under it. I double-
click on that and get the following transcript after ModelSim comes up,
in the ModelSim transcript (output) window:
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do {user_logic_tbw.tdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vcom 6.1e Compiler 2006.03 Mar 8
2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity user_logic_tbw
# -- Compiling architecture testbench_arch of user_logic_tbw
# vsim -lib work -sdfmax /UUT=.sdf -t 1ps user_logic_tbw
# ** Error: (vsim-SDF-3196) Failed to find SDF file ".sdf".
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./user_logic_tbw.tdo PAUSED at line 7
VSIM(paused)>
I previously successfully simulated my design at Behavioral,
Post-Translate, and Post-Map stages.
Why can't it find the .sdf file? This should just work because
everything should be set up automatically.
I have the .sdf file in my project directory, called ppcaesh\, in
\ppcaesh\netgen\par\ . The full path I'm using is
C:\XilinxMe\ISE\AES01OC\ppcaesh\netgen\par\ . In that directory, I have
two files, user_logic_timesim.sdf and user_logic_timesim.nlf . This is
where ISE put them.
>From the manual (the ModelSim User Manual, from http://www.model.com),
-sdfmax /UUT=.sdf is telling ModelSim to use the sdf file, but why
can't it find it in the place that ISE put it? I don't really know that
/UUT=.sdf syntax. One would think that a filename before the .sdf
should be getting put in there automatically. Also I realize that "UUT"
stands for "Unit Under Test", but how is that significant to ModelSim?
What would I set in ISE or in ModelSim, to patch this problem?
I have searched the web to try to find answers on this, but can't find
anything understandable, only snatches. I have downloaded the ModelSim
manuals and tried to figure out what is going on from them, but this
seems to be some conglomeration of ISE syntax using ModelSim and I
couldn't find an explanation of that /UUT=.sdf syntax so that I could
figure out what to patch. Can anyone tell me?
Thanks in advance,
-James
Article: 109566(EDK 8.1.02i) I have instantiated an OPB Bus/Arbiter around a microblaze wtih the following parameters: BEGIN opb_v20 PARAMETER INSTANCE = opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 0.02i) PARAMETER C_DYNAM_PRIORITY = 1 PARAMETER C_PROC_INTRFCE = 1 PARAMETER C_BASEADDR = 0x004E0000 PARAMETER C_HIGHADDR = 0x004EFFFF PARAMETER C_PARK = 0 PARAMETER C_DEV_MIR_ENABLE = 0 PORT SYS_Rst = no_reset_sistema PORT OPB_Clk = reloj_sistema END Well, the problem is that I cannot access the arbiter registers at all. Where is the problem? Does anyone know? Or is it a Xilinx bug? Or what? I am really lost, and I am in urgent need of changing bus priorites. Specifically, I need to give higher priority to peripherals than to microblaze. Regards, ZaraArticle: 109567
Hi all, I'm working on a Virtex-4 FX Design with a custom logic fabric and a PowerPC Core containing a dual port BRAM block. The CPU with software application and BRAM block was created with XPS, then the XPS submodule is imported in my ISE Design as system_stub.vhd. The Top-Level is a Schematic, there i added the other user-specific vhdl-moduls as symbols and of course the system_stub symbol. With a simple C Application i get access to the bram and can read and write data to an from. The next step is to get access to the second port of this bram via my vhdl logic. How can i do this? How can i connect in XPS System Assembly the second BRAM port to external ports? Is it possible to get in ISE TopLevel a system_stub schematic with the additonal ports of BRAM like Adresses, Data, RST, Clk, WEN? Is there another usual way to solve my problems? Every response would be appreciated. MackArticle: 109568
Hi,
I've generated a MAC-FIR Filter, using Xilinx' Core Generator (MAC FIR
5.1) from the Web Pack. The coefficients have been determined via
Matlab and the filter has been simulated there, all fine. To verify my
implemented filter I compared the out put gains at different
frequencies, and obtained:
step input f=0 x=128,000 y=128,370
sinusodial input f=70kHz xmax=128,000 ymax=115,209
sinusodial input f=100kHz xmax=128,000 ymax= 9,780
which results in a stop band attenuation of about 23dB. However I
designed it for a stop band attenuation of 80dB! What I'm doing wrong?
What's your experience with the core generator?
filter characteristic low pass, fpass=70kHz, fstop=90kHz,
fsampling=720kHz, 8 channels, fclock = 92.16MHz, 122 taps, data and
coeff width 18 bits, output width 42 bits.
I've an open discussion to this topic in comp.dsp too, but more related
to signal processing.
http://groups.google.de/group/comp.dsp/browse_thread/thread/e6ffe2850b2e9d3e/c1c1a5e8e6bb7e59?hl=de#c1c1a5e8e6bb7e59
This is my coe file:
radix=10;
coefdata =
80, 233, 276, 336, 250, 77, -168, -372, -440, -302,
19, 403,
673, 668, 329, -243, -811, -1091, -887, -205, 704, 1432,
1585,
984, -204, -1493, -2263, -2050, -796, 1050, 2674, 3243, 2311,
101,
-2500, -4277, -4231, -2102, 1389, 4745, 6299, 5000, 1024, -4118,
-8099,
-8761, -5183, 1661, 9031, 13395, 11938, 4022,
-8061,-19461,-24283,-17740,
1813, 31799, 65789, 95295,112416,112416, 95295, 65789, 31799,
1813,-17740,
-24283,-19461, -8061, 4022, 11938, 13395, 9031, 1661, -5183, -8761,
-8099,
-4118, 1024, 5000, 6299, 4745, 1389, -2102, -4231, -4277, -2500,
101,
2311, 3243, 2674, 1050, -796, -2050, -2263, -1493, -204, 984,
1585,
1432, 704, -205, -887, -1091, -811, -243, 329, 668, 673,
403,
19, -302, -440, -372, -168, 77, 250, 336, 276, 233,
80;
Article: 109569Mack schrieb: > Hi all, > > I'm working on a Virtex-4 FX Design with a custom logic fabric and a > PowerPC Core containing a dual port BRAM block. The CPU with software > application and BRAM block was created with XPS, then the XPS submodule > is imported in my ISE Design as system_stub.vhd. The Top-Level is a > Schematic, there i added the other user-specific vhdl-moduls as symbols > and of course the system_stub symbol. > With a simple C Application i get access to the bram and can read and > write data to an from. > The next step is to get access to the second port of this bram via my > vhdl logic. How can i do this? > How can i connect in XPS System Assembly the second BRAM port to > external ports? Is it possible to get in ISE TopLevel a system_stub > schematic with the additonal ports of BRAM like Adresses, Data, RST, > Clk, WEN? > Is there another usual way to solve my problems? > > Every response would be appreciated. > Mack you need to create small simple wrapper-gateway IP core that connectst to BRAM and simply exports the BRAM signals then you can use the BRAM from ISE toplevel as well. there is no built in standard way of doing this ASFAIK AnttiArticle: 109570
<dhruvakshad@gmail.com> wrote in message news:1159487323.985611.120590@i42g2000cwa.googlegroups.com... >I have a code which has 3 state machines .The code works fine. I'm assuming "works fine" probably means in simulation and not necessarily on a real board but not sure. > But if I > add any other hardware to the design like adder and enable the adder > through a signal in the the state machine then the code doesnt work. > Should I use buffer for all the the enable signals before giving it to > the state machines? No. > What could be the problem? Not a clue. Just a tip, you'll get a better response from this newsgroup on this type of question if you post code and state more explicitly just what exactly you mean by "doesn't work" and "works fine". KJArticle: 109571
"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:hOZSg.48100$G72.27321@newsfe3-gui.ntli.net... > "Ray Andraka" <ray@andraka.com> wrote in message > news:BZYSg.617$XX2.166@dukeread04... > >> One very good reason is for IO compatibility with other IP. The standard >> is to use std_logic, std_ulogic, std_logic_vector and std_ulogic_vector >> for the types on all I/O. That way, your component can be used in a >> larger design regardless of what library that design uses, and same for >> instantiating components within your design. > > Thanks Ray, I thought it might be something like that. > > I shall mod the code somebody gave me so that if I do get type conflicts I > shall convert the bit signal to std_logic. > You should try to use std_ulogic and std_ulogic_vector for all signals that are not intended to be driven from multiple sources. Use std_logic and std_logic_vector only for signals that are going to be driven by multiple drivers (like shared data busses). That gives the compiler the info that it needs so that when you UNintentionally connect two drivers to the same signal it will get caught without having to simulate and debug to find that problem. KJArticle: 109572
Ray Andraka wrote: > Kryten wrote: >> Is there a good reason to use 'std_logic' by default rather than 'bit'? >> >> I started off doing so, then thought it would be more thorough to >> define pure logic in terms of bits and save std_logic for stuff that >> would be anything other than 0 or 1. >> >> I then found my compiler complaining about all sorts of stuff. >> >> Problems trying to use a bit_vector as a counter, or using >> rising_edge() on a bit, and so on. >> >> I'm inclined to just use std_logic as my fundamental signal. >> >> Opinions? >> >> > > One very good reason is for IO compatibility with other IP. The > standard is to use std_logic,std_ulogic, std_logic_vector and > std_ulogic_vector for the types on all I/O. That way, your component > can be used in a larger design regardless of what library that design > uses, and same for instantiating components within your design. Also, BIT is constrained to values 0 & 1. std_(u)logic also recognises 'X', 'Z' and more. These do have real-world meaning. The 'X' in particular, can reveal design faults such as not initialised & bus contention.Article: 109573
On 29 Sep 2006 01:45:03 -0700, "Mack" <disentis@gmx.li> wrote: >Hi all, > >I'm working on a Virtex-4 FX Design with a custom logic fabric and a >PowerPC Core containing a dual port BRAM block. The CPU with software >application and BRAM block was created with XPS, then the XPS submodule >is imported in my ISE Design as system_stub.vhd. The Top-Level is a >Schematic, there i added the other user-specific vhdl-moduls as symbols >and of course the system_stub symbol. >With a simple C Application i get access to the bram and can read and >write data to an from. >The next step is to get access to the second port of this bram via my >vhdl logic. How can i do this? >How can i connect in XPS System Assembly the second BRAM port to >external ports? Is it possible to get in ISE TopLevel a system_stub >schematic with the additonal ports of BRAM like Adresses, Data, RST, >Clk, WEN? >Is there another usual way to solve my problems? > >Every response would be appreciated. >Mack *Probably*, if you intantiate only an lmb_if_ram_controller, connected to (for instance) port A of a bram, then all you have to do is in "ports" view of System Assembly, click on "connectio-Filters", check "All". The, under your BRAM you will have access to all port B. Assign signal names to all signals, and them make them external. There you are. ZaraArticle: 109574
Zara schrieb: > On 29 Sep 2006 01:45:03 -0700, "Mack" <disentis@gmx.li> wrote: > > >Hi all, > > > >I'm working on a Virtex-4 FX Design with a custom logic fabric and a > >PowerPC Core containing a dual port BRAM block. The CPU with software > >application and BRAM block was created with XPS, then the XPS submodule > >is imported in my ISE Design as system_stub.vhd. The Top-Level is a > >Schematic, there i added the other user-specific vhdl-moduls as symbols > >and of course the system_stub symbol. > >With a simple C Application i get access to the bram and can read and > >write data to an from. > >The next step is to get access to the second port of this bram via my > >vhdl logic. How can i do this? > >How can i connect in XPS System Assembly the second BRAM port to > >external ports? Is it possible to get in ISE TopLevel a system_stub > >schematic with the additonal ports of BRAM like Adresses, Data, RST, > >Clk, WEN? > >Is there another usual way to solve my problems? > > > >Every response would be appreciated. > >Mack > > *Probably*, if you intantiate only an lmb_if_ram_controller, connected > to (for instance) port A of a bram, then all you have to do is in > "ports" view of System Assembly, click on "connectio-Filters", check > "All". The, under your BRAM you will have access to all port B. Assign > signal names to all signals, and them make them external. > There you are. > > Zara hi thanks! sometime easy things in EDK are not so easy, I never tried the port filter thing !!! Antti
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