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sutejok schrieb: > Just curious, > does Virtex4 has its own built-in configuration ROM? as in it will > automaticaly has the chip configured on power up? ALL Xilinx FPGA are RAM based and require ext ROM for config AnttiArticle: 108876
Hello John, thanks for the kudos. If you'd like to give any feedback or comments on the new family, Bertrand Leigh, Lattice's director of apps engineering, has posted a blog about the new LatticeECP2M FPGA here: http://latticeblogs.typepad.com/frontier/2006/09/lowcost_fpga_wi.html rgds, Bart Borosky, Lattice > The ECP2M parts, on the other hand, blow past the Brand A and Brand X > low-cost offerings on memory to logic ratios *and* are the first low-cost > devices to include SERDES functionality and at *very* attractive per-channel > power levels.Article: 108877
Jeff Johnson wrote: > so the question is........i think.......how do you reformat the output > of the NIOS IDE output files so they can be saved to flash and > successfuilly rebooted. In principle, this completely depends on the type of flash you use. If you look into the datasheet of the flash chips you're using, there should be a detailed section on how to erase a page of flash, how to bulk-erase the whole chip etc, and, most importantly, how to program an empty page of flash. Basically, there's two types of flash, namely Intel and AMD type flash. Both types use different programming algorithms. Newer flash devices offer something called CFI (Common Flash Interface), where you send a bunch of very specific write commands to the flash device, after which it can supply you with the algorithm, number of pages etc etc. Best to contact your local Altera or disti FAE for some suggestions. Best regards, BenArticle: 108878
Nico, OK, here it is: (for S3, V2, and V2 Pro) "It is likely that the delay will be marginally smaller if you tie the 2 LSB inputs and use the upper 16 inputs only. However, the software model is pretty simple and won't model that as far as I can remember. Also, since one of the inputs goes through the Booth encoder it might not be as substantial of an improvement as it would be with an "original recipe" multiplier." So, there you go. Looks like sign extension is the only 'official' way to go, but there will be some fat (overestimation of delay) in the set the lsb's to 0 solution, and the software will not model it, and yet it may be a small improvement over what is predicted. Sorry if this is just too slow, AustinArticle: 108879
David Ashley wrote: > Open Cores DDR controller uses 2 DCM's to generate the clocks. > > clk -> dcm0 -> clock used for fddr to produce true + negative ddr clocks > feedback comes from true ddr clock > fddr has hard wired 01 inputs for true clock, > 10 inputs for negative clock > > clk -> dcm1 -> (0 clock) bufg1 -> clock used for all ddr related > internal logic > -> (270 clock) bufg2 -> clock used for fddr's for > DDR's data in lines > feedback comes from the output of bufg1 > > > dcm0 has a tunable parameter, phase shift of 30 ps. I've moved this all > the way > to -530ps with no failure. It seems irrelevant. > > I want to get rid of one of the DCM's, 2 seems excessive. Is it common > to use > an fddr to get a clock to the outside this way? That is, an fddr has > fixed inputs > (input0 <= '0', input1 <= '1') and so the fddr output is really just a > data selector, > when the input clock is low you get input0, when high you get output1. Why > not route the clock through to the outside directly? > > I've tried hanging the DDR's clock off of bufg1 (still going through fddr) > but it doesn't work reliably, I get flaky data. > > Where can I find info about clock generation issues, specifically > related to ddr. > I never would have come up with the scheme that seems to actually work in > this case. Is it possible to do with just one DCM? > > Thanks-- > Dave > I found a xilinx app note xapp802.pdf which has a nice block diagram of an approach with just just one DCM on page 3. It is related to virtex but I'd hope spartan-3e would be the same... -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108880
Antti wrote: > sutejok schrieb: > >> Just curious, >> does Virtex4 has its own built-in configuration ROM? as in it will >> automaticaly has the chip configured on power up? > > ALL Xilinx FPGA are RAM based and require ext ROM for config > > Antti > Antti, So far, this is true. You never know what will happen next. AustinArticle: 108881
Mostly for xilinx people, xapp802 Xilinx XAPP802 Virtex Series Memory Interface Application Notes Available here: http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf#search=%22xilinx%20ddr%20fae%22 On page 3 is figure 2. There is an FDDR shown on the diagram that has left and right data going into the D0 and D1 inputs, but both clocks are coming from the same source (CLK0 from the DCM). Shouldn't C1 be coming from the CLK180? -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 108882
betterone11@gmail.com wrote: > fpgaman wrote: > >>"http://www.latticesemi.com/products/intellectualproperty/latticemico32" > > > The link to the store does not show the board directly. What is the > price? > Is there any low cost evaluation kit alternative and what kind of > debugger will work? Looks like the web store is a little slower in the loop... When you get a direct link like given above, it's normally a good idea to also find the related press release : http://www.latticesemi.com/corporate/newscenter/productnews/2006/r060918new32bitembeddedmi.cfm this mentions the prices of the EvalPCB's & toolchains. This core complements the Mico8, but is much larger. What would be nice is an intermediate core: along the lines of "smallest core that can run HLL" - with 16/18 bit opcodes ? -jgArticle: 108883
Hi Austin, Do you mean that next gen Virtex will come with a build in flash (no ROM please), or is it rather Spartan4 flash? Luc On Mon, 18 Sep 2006 14:41:12 -0700, Austin Lesea <austin@xilinx.com> wrote: >Antti wrote: >> sutejok schrieb: >> >>> Just curious, >>> does Virtex4 has its own built-in configuration ROM? as in it will >>> automaticaly has the chip configured on power up? >> >> ALL Xilinx FPGA are RAM based and require ext ROM for config >> >> Antti >> > > >Antti, > >So far, this is true. > >You never know what will happen next. > >AustinArticle: 108884
thanks for the heads up. i've notified the Lattice store. the mico32 development kit should be up on the store later today. rgds, bart, Lattice The LatticeMico32 Development Kit is available now and is priced at $995. The Kit includes both the ispLEVER design tools, regularly priced at $695, and the development board, which as a stand-alone is priced at $595. > Looks like the web store is a little slower in the loop...Article: 108885
lb.edc@telenet.be wrote: > Hi Austin, > > Do you mean that next gen Virtex will come with a build in flash (no > ROM please), or is it rather Spartan4 flash? Adding FLASH loader memory to the same package (not 1 die) is relatively easy to do, as also is adding large SRAM. Other industries already do this. Making a whole device on a flash process is more difficult, but others are doing that too. So yes, I am sure it will come from Xilinx. The question is when ? -jgArticle: 108886
You can order Virtex-5 devices from your distributor now, and he will
offer short delivery times.
Whether the distributor carries these parts on his shelves is entirely
his business decision, but he can always get them for you from Xilinx
at short notice. ("4 to 6 weeks" seems to be the standard answer, but
don't be surprised if it is much faster.)
Available from inventory here at Xilinx are nine part / package
combinations, eighteen if you count the leaded/lead-free versions:
XC5VLX30-1FF(G)324C and -676C
XC5VLX50-1FF(G)324C and -676C and -1153C
XC5VLX85-1FF(G)676C and -1153C
XC5VLX110-1FF(G)676C and -1153C
LX is the logic-oriented sub-family, with BlockRAMs and DSP slices, but
without multi-gigabit transceivers. See the data sheet on the Xilinx
website.
The 30 to 110 is a proportional indicator of logic density (thousands
of "equivalent Logic Cells")
The -1 stands for the slowest speed grade (the only one available this
early)
The FF stands for flip-chip ball-grid array, the one way we package all
Virtex-5 family devices
The G stands for "green" = lead-free packages which are all available
right now.
We have found over the years that small-volume users and consultants
often are the most enthusiastic early adopters, but they may not always
be sure about instant availability.
Now you know !
More parts to come very soon.
Peter Alfke, who has been working on and with these parts for over a
year.
Article: 108887
hi
i need information regarding 4 bit multiplier
Article: 108888John_H wrote: > "rickman" <gnuarm@gmail.com> wrote in message > news:1158605643.208484.113710@m7g2000cwm.googlegroups.com... > > > > The pricing I have gotten on the ECP2 line is attractive, but in the > > grand scheme of things I don't see where it is a significant difference > > with the other players in the field. I think that optimizing any given > > parameter in the FPGA market is a matter of timing. A couple of years > > ago Spartan 3s were the low cost chips, then when the Cyclone II parts > > came out they were a bit cheaper. Now that ECP2 parts are starting to > > show, they will be cheaper... until the Spartan 4/5 parts make it to > > the scene. > > > > If only there was something that actually distinguished the different > > families of parts! > > > The ECP2 line is nice but not terribly remarkable. > > The ECP2M parts, on the other hand, blow past the Brand A and Brand X > low-cost offerings on memory to logic ratios *and* are the first low-cost > devices to include SERDES functionality and at *very* attractive per-channel > power levels. > > My attention was attracted to the offering because of the memory. Adding > PCI express would be quite a bonus for me. Please don't get me wrong, I am not knocking any of these parts. But I don't see a serdes and being a valuable addition to a low cost FPGA. Normally the items you are interfacing to with a serdes are not so cheap, but maybe I am not current and serdes are more popular now. But I see it as similar to the conversation where someone was complaining about needing to use $0.09 FETs for a high current interface rather than the low cost $0.03 cent 7002 FETs because the 3.3 volt interface on the FPGA would not drive the FET fully. Even a cheap FPGA is around $20 in most designs, so what is the diff on a few cents on the FETs? LIkewise, what is the diff on a $40 FPGA rather than a $20 FPGA if it interfaced to a $200+ fiber interface? Personally what I want is a good $10 FPGA with 260 IOs. So far they are all about $20. If it has more memory to support an imbedded MCU, all the better!Article: 108889
Well thanks for the answer. I have been out looking for an eval board for the XPLA3 and I am having trouble finding a decent one. Digilent has one with a "solderless breadboard" which is pretty pointless these days. Otherwise, the only one I can find has to be ordered from India. I was hoping the one listed on the Xilinx web site as being from Avnet was available, but I can find neither hide nor hair yet. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sSecondaryNavPick=BOARDS&key=ADS-XLX-X3-EVL&sGlobalNavPick=PRODUCTS&BV_SessionID=@@@@2132332454.1158622903@@@@&BV_EngineID=cccjaddikmdkkjhcefeceihdffhdfkf.0 Peter Alfke wrote: > I checked with our CPLD folks in Xilinx, and here is their answer: > > "Absolutely no planned obsolescence for XPLA3. > We never made a widely circulated XPLA3 development board that > we sold. We had a few hundred that we gave away. > XPLA3 has gained significant volume, with design wins in > handheld computers etc. It has also been designed in at a major > consumer house. > It will be around for quite a while. > The single 3.3V power supply has been a big plus for it." > > Peter Alfke > =============================== > rickman wrote: > > I am looking at using the XPLA3 in a new design and am having trouble > > finding an evaluation board. So I started looking around and see that > > Xilinx seems to be severely curtailing support of these parts. There > > Xilinx no longer offers evaluation boards and I can't find many third > > party boards that are still offered. > > > > On the bright side, when I did a search at Nuhorizons for XCR3128, I > > got lots of hits. That alone would not give me confidence, but not > > only did I get the XCR3128XL that I need to use, I found the XCR3128 > > without the XL which is an even older part. If they are still selling > > those parts, I guess I can expect to see the XCR3128XL around for quite > > a while. > > > > The Coolrunner II may be a bit lower power, but the XPLA3 parts are > > nearly as low power for our application and only require a single power > > voltage. That makes them *more* power efficient. I just wish Xilinx > > provided as much support for the XPLA3 parts as they do for the > > Coolrunner II. > > > > Are there any advantages of the Coolrunner II parts that I am missing? > > I see they have input hysteresis, but otherwise they seem pretty much > > the same as the Coolrunner XPLA3.Article: 108890
I would implement such a small multiplier as a 256 x 8 RAM-based ROM. 4+4 address inputs, and 8 outputs. Brute force and simple. Peter Alfke, Xilinx kishoremi2@gmail.com wrote: > hi > i need information regarding 4 bit multiplierArticle: 108891
OOPS, I forgot to point out that the part number must have ES at the
end of its name, e.g.
XC5VLX30-1FFG324CES.
ES stands for "Early Silicon". The absence of these two letters would
declare it a "volume production" part (which is not available yet), and
the order would automatically be rejected.
One can never be too precise, especially with computerized order entry.
Peter Alfke
Peter Alfke wrote:
> You can order Virtex-5 devices from your distributor now, and he will
> offer short delivery times.
> Whether the distributor carries these parts on his shelves is entirely
> his business decision, but he can always get them for you from Xilinx
> at short notice. ("4 to 6 weeks" seems to be the standard answer, but
> don't be surprised if it is much faster.)
> Available from inventory here at Xilinx are nine part / package
> combinations, eighteen if you count the leaded/lead-free versions:
>
> XC5VLX30-1FF(G)324C and -676C
> XC5VLX50-1FF(G)324C and -676C and -1153C
> XC5VLX85-1FF(G)676C and -1153C
> XC5VLX110-1FF(G)676C and -1153C
>
> LX is the logic-oriented sub-family, with BlockRAMs and DSP slices, but
> without multi-gigabit transceivers. See the data sheet on the Xilinx
> website.
> The 30 to 110 is a proportional indicator of logic density (thousands
> of "equivalent Logic Cells")
> The -1 stands for the slowest speed grade (the only one available this
> early)
> The FF stands for flip-chip ball-grid array, the one way we package all
> Virtex-5 family devices
> The G stands for "green" = lead-free packages which are all available
> right now.
>
> We have found over the years that small-volume users and consultants
> often are the most enthusiastic early adopters, but they may not always
> be sure about instant availability.
> Now you know !
> More parts to come very soon.
>
> Peter Alfke, who has been working on and with these parts for over a
> year.
Article: 108892kishoremi2@gmail.com wrote: > i need information regarding 4 bit multiplier You should use the ROM lookup table, if you want speed, otherwise you could try this: http://groups.google.de/group/comp.lang.vhdl/msg/32a9a02c2b2b838d -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 108893
Hi all, Does any one used Open core FFT. I am trying to use it, but what my simulation results shows is that the performance of the FFT does not match with the other FFT cores available from other vendors(eg. xilinx). The magnitude of the result seems matching except the attenuation of the side lobs is not so good. But what i am afraid is that the phase response of the FFT result is very bad compared to FFT result from matlab or from other vendors. Can anybody help me if you have used open core FFT . Thanks in advance rgds bijoyArticle: 108894
Hi, I am designing a FIR filter using Xilinx block set in MatLab. Could you tell me how to change the coefficient word length in MatLab because I need to minimize coefficient word length. Thank you very much!Article: 108895
How does a BUF component increase the drive strength of a signal? ThanksArticle: 108896
Hi I'm planning to get the XtremeDSP kit with Virtex4 on it. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-DI-DSP-DK4 I'm not sure if i'm blind or what, but is there any platform flash on it so that i can have it configure the FPGA on power up?? I need the resulting product to be stand alone device. If there is, can someone point out where can i find the information on this? I didnt see in on the spec.. If there is NOT, is there a reason why would such advanced board not loaded with a flash memory on board so that user would not need to re-configure each time the device boot?? or am i expecting too much? Thx alot tejoArticle: 108897
Thanks for the rapid replies. You guys have been very helpfull. During my project phase I will use this forum frequently(without trying to ask to many stupid questions of course :) ). Cheers, Chris Hadland, Laerdal Medical ASArticle: 108898
please tell me which one core is more suitable fot digital implementation , which are available in ISE. DA or MAC. Regards J.RAmArticle: 108899
xilinx's coregen can generate FFT modules.. bijoy wrote: > Hi all, > > Does any one used Open core FFT. > > I am trying to use it, but what my simulation results shows is that the performance of the FFT does not match with the other FFT cores available from other vendors(eg. xilinx). > > The magnitude of the result seems matching except the attenuation of the side lobs is not so good. > > But what i am afraid is that the phase response of the FFT result is very bad compared to FFT result from matlab or from other vendors. > > Can anybody help me if you have used open core FFT . > > Thanks in advance > > rgds bijoy
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Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z