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Hello, We are looking for a consultant to validate a hardware design. The design is used to do some video processing and has SDR-SDRAM chips, DVI encoders and decoders and a spartan 3 device. Please contact skris0@engr.uky.edu for details. - Thanks SubhasriArticle: 108651
Patrick Dubois wrote: > Hello, > > As any user of Xilinx Chipscope Pro probably already noticed, the GUI > is not that great. Especially when it comes to handling buses. One has > to manually group each buses by hand and this is time consuming, > especially if you're like me and you have 3 FPGAs in the jtag chain, > each with 20 different buses. > > So I created a small perl script to automate this process, it's called > csptool. I'm releasing this small script as open-source on Google Code: > http://code.google.com/p/csptool/ > > Here is the help from the script: > -------------------------------------------------------------- > Features: > - Supports multiple FPGA devices and multiple ILA units per FPGA > - Supports Chipscope Pro v7.1.04i and v8.1.03i (Windows). Should > work with other OS and/or other Chipscope versions too. > - Supports regular buses, i.e. bus<0>, bus<1>, but also "state machine > style" buses such > as State_Fdd1, StateFdd2, etc. > > Usage: > - Create a new cpj projet with Chipscope Pro Analyzer (might not work > if project is not "fresh"). > - Import the .cdc files to get relevant signal names. > - For each unit and each FPGA, make the waveform appear by clicking > "Waveform" in the > left project tree. > - Save the project (you don't need to close Chipscope). > - Run the tool like this: csptool your_project.cpj (I suggest to > associate > .cpj files to csptool.exe, so that you can just double-click a .cpj > file) > - Reload your Chipscope projet. > -------------------------------------------------------------- > > To use it, you must install a perl interpreter such as the free > ActivePerl. Once this is done and you know that perl.exe is in your > path, juste type: > perl csptool.pl your_project.cpj > > You can make it even easier by compiling the perl script into a .exe > and associating .cpj files to that .exe. That way, you simply have to > double-click on your project in windows explorer and voil=E0. I'm sorry > that I can't release a .exe publicly, I don't have a license for a perl > compiler. > > If you want to contribute some features to the script (check the > comments in the script for a suggested todo list) feel free to send me > an e-mail and I'll gladly give you commit rights. > > I hope it can be useful to someone. > > > Patrick Dubois Hi Patrick, Thank you very much for your wonderful work. ChipScope is 1st class excellent tool, but its GUI is the 3rd class. Xilinx, why don't you put some money on the 1st clall tool to get its 1st class GUI? It is not difficult as ChipScope, but it is very helpful ans saving time to users. WengArticle: 108652
Thanks for your answer. I tried it that way alt_irq_init(ALT_IRQ_BASE); /* Register the interrupt handler. */ alt_irq_register( CodecIRQRegBase, context, AudioCodecInISR ); IOWR_ALTERA_AVALON_PIO_IRQ_MASK(CodecIRQRegBase, 0x3); /* Reset the Button's edge capture register. */ IOWR_ALTERA_AVALON_PIO_EDGE_CAP(CodecIRQRegBase, 0x0); but it isn't working. You're right the code doesn't have any effect. I shortened it to post it here. I set a Breakpoint inside the ISR but the breakpoint never breaks the running debugging execution, so I know that the interrupt newer gets triggered.Article: 108653
Daniel S. wrote: > Weng Tianxiang wrote: > >> Flexibility, scalability and routability are what makes ring buses so > >> popular in modern large-scale, high-bandwidth ASICs and systems. It is > >> all a matter of trading some up-front complexity and latency for > >> long-term gain. > >> > >> Since high-speed parallel buses end up needing pipelining to meet > >> high-speed timings, the complexity and area delta between multiple > >> parallel buses and ring-bus topologies is shrinking. > >> > > > > Hi Daniel, > > It is very interesting to learn there is a ring bus structure over > > there. > > > > "Flexibility, scalability and routability are what makes ring buses so > > popular in modern large-scale, high-bandwidth ASICs and systems" > > > > Can you please me some reference papers about ring bus applications in > > ASIC or FPGA? > > > > Normally what a designer is concerns most about is data latency in a > > bus structure > > Thank you. > > > > Weng > > Real-world ring-buses: > - IBM Power4 Multi-Chip-Module core-to-core interconnect > - IBM Power4 MCM-to-MCM interconnect > - IBM Power4 system-to-system interconnect > - ATI X1600/X1800 memory ring-bus > > IBM made lots of noise about its ring bus architecture a few years ago > but I am pretty sure I read about something similar many years earlier. > I am guessing Power5 must be using much of the same even though IBM did > not make as much noise about it. > > -- > Daniel Sauvageau > moc.xortam@egavuasd > Matrox Graphics Inc. > 1155 St-Regis, Dorval, Qc, Canada > 514-822-6000 Hi Daniel, 1. IBM uses ring buses in its core-to-core interconnect. It is a good option there, because time latency among cores are not urgent. That saves a fast switch design among multiple CPUs. You may imagine if there are 16 cores, how difficult it is to design a fastest switch among the 16 cores!!! And IBM has good experiences with ring net system. 2. I guess you cannot list a 2nd example to use ring buses in a CPU among its tens of registers. Why? Internally nodoby could afford the clock latency among any registers. 3. You option to use ring buses in your application is justified: you are not concerned about the latency. Thank you for ring bus information. WengArticle: 108654
hello,
I like to create some new blocks for Sysgen, how can I do this? I
couldn't find any information on how I can do this. Any help appreciated.
Best regards
Article: 108655eziggurat@gmail.com wrote: > Hi, > > I was wondering what is most fast and efficient intepolation algorithm > that easily adaptable in a Spartan 3 and able to process more than 60 > frames per seconds? > > I have read a paper about an adaptive Newton interpolation algorithm > that suppose to use less resources than the Bicubic and comparable with > the image quality of the Bicubic. > > The algorithm will be used to scale the output of a LCD driver IC that > outputs 18 to 24 bits RGB and FPGA will scale the image less than 18 > bits and use on a smaller LCD screen. > > Any tips will be very helpful. > > Regards > P > That is interesting, i will start with an interpolation algorithm next week ... where can i find that paper about the adaptive Newton interpolation algorithm? Thanks in advance, Kind regards, YArticle: 108656
Do You Mean: http://en.wikipedia.org/wiki/Newton's_method ? Austin yttrium wrote: > eziggurat@gmail.com wrote: >> Hi, >> >> I was wondering what is most fast and efficient intepolation algorithm >> that easily adaptable in a Spartan 3 and able to process more than 60 >> frames per seconds? >> >> I have read a paper about an adaptive Newton interpolation algorithm >> that suppose to use less resources than the Bicubic and comparable with >> the image quality of the Bicubic. >> >> The algorithm will be used to scale the output of a LCD driver IC that >> outputs 18 to 24 bits RGB and FPGA will scale the image less than 18 >> bits and use on a smaller LCD screen. >> >> Any tips will be very helpful. >> >> Regards >> P >> > > That is interesting, i will start with an interpolation algorithm next > week ... > > where can i find that paper about the adaptive Newton interpolation > algorithm? > > Thanks in advance, > > Kind regards, > > YArticle: 108657
eziggurat@gmail.com schreef: > Hi, > > I was wondering what is most fast and efficient intepolation algorithm > that easily adaptable in a Spartan 3 and able to process more than 60 > frames per seconds? > > I have read a paper about an adaptive Newton interpolation algorithm > that suppose to use less resources than the Bicubic and comparable with > the image quality of the Bicubic. > > The algorithm will be used to scale the output of a LCD driver IC that > outputs 18 to 24 bits RGB and FPGA will scale the image less than 18 > bits and use on a smaller LCD screen. > > Any tips will be very helpful. If you are going to 'resize' to a different number of pixels, then make sure you do a lowpass _before_ the rescaling, to avoid aliasing. Here, on my site you can see the difference: http://panteltje.com/panteltje/subtitles/lowpass.html I do not suggest you use fft and reverse fft, anyways that was a project that ended when DVD burners became available, and the math in rescaler-yuv is not correct.... not finished, purely experimental, will not be finished... But you will perhaps want the lowpass to avoid the aliasing effects. As for less bit depth.. what is against dropping the lsb[s]?Article: 108658
Hello everybody, In a design I'm working on I want to multiply two 16 bit 2's complement (signed) numbers using the mult18x18 multipliers. According to the Sparten 3 userguide, it is enough to use the lower bits and take the result from the output. However, when I do this, the result is not correct when negative numbers are multiplied, positive numbers are no problem. If I use the highest (MSB) bits of the multiplier, the results are correct. But... using the highest bits of the multiplier causes my design to fail timing constraints because the multipliers get slower when more bits are being used. What am I doing wrong here? -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 108659
Nico Coesel <nico@puntnl.niks> wrote: > Hello everybody, > In a design I'm working on I want to multiply two 16 bit 2's > complement (signed) numbers using the mult18x18 multipliers. According > to the Sparten 3 userguide, it is enough to use the lower bits and > take the result from the output. However, when I do this, the result > is not correct when negative numbers are multiplied, positive numbers > are no problem. > If I use the highest (MSB) bits of the multiplier, the results are > correct. But... using the highest bits of the multiplier causes my > design to fail timing constraints because the multipliers get slower > when more bits are being used. > What am I doing wrong here? Probably you need to sign-extend when stuffing the high bits... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 108660
Nico Coesel wrote: >Hello everybody, > >In a design I'm working on I want to multiply two 16 bit 2's >complement (signed) numbers using the mult18x18 multipliers. According >to the Sparten 3 userguide, it is enough to use the lower bits and >take the result from the output. However, when I do this, the result >is not correct when negative numbers are multiplied, positive numbers >are no problem. > >If I use the highest (MSB) bits of the multiplier, the results are >correct. But... using the highest bits of the multiplier causes my >design to fail timing constraints because the multipliers get slower >when more bits are being used. > >What am I doing wrong here? > > > Could you sign-extend the upper 2 bits, basically tie the bits 17, 16 and 15 together on both inputs? It really then is still a 16-bit multiply. On the other hand, if the 2 LSB's are always zero, the propagation time shouldn't get worse than if it was the 2 MSB's that are zero. JonArticle: 108661
Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: >Nico Coesel <nico@puntnl.niks> wrote: >> Hello everybody, > >> In a design I'm working on I want to multiply two 16 bit 2's >> complement (signed) numbers using the mult18x18 multipliers. According >> to the Sparten 3 userguide, it is enough to use the lower bits and >> take the result from the output. However, when I do this, the result >> is not correct when negative numbers are multiplied, positive numbers >> are no problem. > >> If I use the highest (MSB) bits of the multiplier, the results are >> correct. But... using the highest bits of the multiplier causes my >> design to fail timing constraints because the multipliers get slower >> when more bits are being used. > >> What am I doing wrong here? > >Probably you need to sign-extend when stuffing the high bits... I tried that, but that didn't solve the problem and made meeting the timing constrains even harder. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 108662
Hello, I wonder if anyone has a few Spartan XCS30-3TQ144C or compatible parts. I have ended the production run of a board that uses these, and am moving to Spartan 2E, but just need a couple parts to fix damaged units coming back from the field. I had to pick one off one of my test boards to fix a customer's unit that was blitzed by Lightning. I'll be glad to pay, say, $15 each for 5 - 10 pieces. Thanks, Jon ElsonArticle: 108663
Lattice is holding a webcast this Tuesday, September 19, "Optimizing Verilog Coding for More Efficient FPGA Synthesis." The presenter will be Troy Scott, from our software marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be able to view this webcast archive on-demand, at your convenience, starting a few hours after the live event takes place. You can register by clicking: http://www.latticesemi.com/corporate/webcasts/optimizingverilogcodingfo/index.cfm Bart Borosky, LatticeArticle: 108664
The link is http://doi.ieeecomputersociety.org/10.1109/ICICIC.2006.226#search=%22adaptive%20newton%20FPGA%22 for the algorithm. yttrium wrote: > eziggurat@gmail.com wrote: > > Hi, > > > > I was wondering what is most fast and efficient intepolation algorithm > > that easily adaptable in a Spartan 3 and able to process more than 60 > > frames per seconds? > > > > I have read a paper about an adaptive Newton interpolation algorithm > > that suppose to use less resources than the Bicubic and comparable with > > the image quality of the Bicubic. > > > > The algorithm will be used to scale the output of a LCD driver IC that > > outputs 18 to 24 bits RGB and FPGA will scale the image less than 18 > > bits and use on a smaller LCD screen. > > > > Any tips will be very helpful. > > > > Regards > > P > > > > That is interesting, i will start with an interpolation algorithm next > week ... > > where can i find that paper about the adaptive Newton interpolation > algorithm? > > Thanks in advance, > > Kind regards, > > YArticle: 108665
Ahh, http://en.wikipedia.org/wiki/Newton_polynomial Austin eziggurat@gmail.com wrote: > The link is > http://doi.ieeecomputersociety.org/10.1109/ICICIC.2006.226#search=%22adaptive%20newton%20FPGA%22 > for the algorithm. > > > > yttrium wrote: >> eziggurat@gmail.com wrote: >>> Hi, >>> >>> I was wondering what is most fast and efficient intepolation algorithm >>> that easily adaptable in a Spartan 3 and able to process more than 60 >>> frames per seconds? >>> >>> I have read a paper about an adaptive Newton interpolation algorithm >>> that suppose to use less resources than the Bicubic and comparable with >>> the image quality of the Bicubic. >>> >>> The algorithm will be used to scale the output of a LCD driver IC that >>> outputs 18 to 24 bits RGB and FPGA will scale the image less than 18 >>> bits and use on a smaller LCD screen. >>> >>> Any tips will be very helpful. >>> >>> Regards >>> P >>> >> That is interesting, i will start with an interpolation algorithm next >> week ... >> >> where can i find that paper about the adaptive Newton interpolation >> algorithm? >> >> Thanks in advance, >> >> Kind regards, >> >> Y >Article: 108666
Nico Coesel wrote: > Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: > > >>Nico Coesel <nico@puntnl.niks> wrote: >> >>>Hello everybody, >> >>>In a design I'm working on I want to multiply two 16 bit 2's >>>complement (signed) numbers using the mult18x18 multipliers. According >>>to the Sparten 3 userguide, it is enough to use the lower bits and >>>take the result from the output. However, when I do this, the result >>>is not correct when negative numbers are multiplied, positive numbers >>>are no problem. >> >>>If I use the highest (MSB) bits of the multiplier, the results are >>>correct. But... using the highest bits of the multiplier causes my >>>design to fail timing constraints because the multipliers get slower >>>when more bits are being used. >> >>>What am I doing wrong here? >> >>Probably you need to sign-extend when stuffing the high bits... > > > I tried that, but that didn't solve the problem and made meeting the > timing constrains even harder. > Sign extend the inputs to the uper bits, but keep your active 16 bits in the bottom. The timing analyzer doesn't figure out you have the bottom bits tied to zero, so it gives you timing for an 18x18 if you are taking outputs from the top bits of the product. You might also consider registering the multiplier output with flip-flops and place them immediately adjacent to the multiplier rather than letting the auto-placement do it. THe autoplace doesn't do so hot a job at placing registers around the multipliers, so you can fail timing due to a long route combined with the relatively slow clock to out of the multiplier. The output timing is the more critical for a pipelined multiply. You may also find you need to pipeline the inputs, in which case those should also be hand placed near the multiplier (but put the output registers closest) to get the peak performance.Article: 108667
panteltje@yahoo.com schrieb: > eziggurat@gmail.com schreef: > If you are going to 'resize' to a different number of pixels, then make > sure > you do a lowpass _before_ the rescaling, to avoid aliasing. > Here, on my site you can see the difference: > http://panteltje.com/panteltje/subtitles/lowpass.html > I do not suggest you use fft and reverse fft,[...] > But you will perhaps want the lowpass to avoid the aliasing effects. A few comments to your web page: 1. It is not uncommon that you get amplitudes after filtering that are higher than the original amplitude. That is no shortcoming of the implementation but inherent in the math. A square wave of amplitude 1 has a sine component of f with an amplitude way above 1. While you subtract energy from the signal the amplitude can rise. 2. Most image resampling algorithms actually are FIR filters, most of these are low order low pass filters. Even linear interpolation is a low pass, albeit not a very good one. A perfekt low pass equivalent to your fft approach would be sin(x)/x interpolation which is computationally quite expensive but a lot faster than the FFT and gives exactly the same results. 3. Scaling and filtering can folded and performed in one step. This is true for both approaches: FIR-filters and FFT. Kolja SulimmaArticle: 108668
jean-francois hasson wrote: > I work on a board with an Altera 7128S part (5V quite old but still used > ...). It seems the part is most of the time working just fine but > depending on when it is powered on it overheats a lot and does not seem > to be well configured : an input acts as an output, and the component is > not working fine at all. Does anyone havea clue as to what could be > going wrong ? It does not happen all the time. You get this behaviour too when the TCK pin is not properly pulled up (or down, whichever). But, as most suggest, this smells of a power-sequencing issue. Best regards, BenArticle: 108669
I've got some DACs that I'd like to switch gain ranges on, and it turns out I can do it nicely using a single 2N7002 (sot23 n-channel mosfet) to switch a resistor to ground in each reference circuit. So I'd like to turn each 7002 on and off from a pin on an XC3S400. But 3.3 volts is a marginal high for this fet... 4 volts looks safe. So, how about running Vccio a bit high, 3.5 maybe, and adding an external pullup resistor to +5. If I tristate the pin, I should forward-bias the upper esd diode and get 4.2 roughly, right? I'm thinking maybe a half milliampere or so pullup current. Doing this 8 times only dumps 4 mA into the Vccio rail, no hazard there. I could use a lower-threshold fet, I guess, but the 7002's are in stock and cost 3 cents each. JohnArticle: 108670
On 13 Sep 2006 17:25:18 -0700, Ben.Nader@gmail.com wrote: >Hi > >I am trying to programm a XC2S300E through a microcontroller using the >Slave p mode. >I make a ufp file ( which is just a hex file) of my program using >xilinx ISE 8.1 and then using the microcontroller and and slave mode >signals I send it to the fpga. >I have all this working for another design, which is exactly the same >micro but Xc2S150E FPGA. but I can not get this to work on XC2S300E. > >here is what happens: > >1. I pulsed the ~prog line low and then high. ( to start the clearing >configuration memory) >2. I see FPGA lowers INIT line ( it shows it is busy clearning the >memory) >3. INIT goes high >4. I am sending Clock along with 8bit data on D[7:0] and CCLK. >5. I see INIT stays high ( so I thought CRC check was okay) >6. DONE stays low, I never see it coming up. > >after extensive search on the Xilinx website I read something that I >could have a timing problem and I should keep sending CCLK till DONE >goes high. so I tried just running CCLK for like a full SECOND after I >was done sending my real data, and I still never saw DONE going high. > >I purposly changed my hex file to see if I the CRC error happens and >INIT goes low. but I never saw this. INIT was high the entire time >after the initial memory clearning process( FPGA pulled it low then) >so this means I am not as far as CRC test on the flow chart. I am >wondering If FPGA thinks that it is not at the end of the file yet or >if it is reading anything at all. >I also checked the number of bits on hex file and it matches the number >on the Xilinx Datasheet. so I know I build the correct hex file. > >I have 3 different boards with XC2S300E that I have this problem with. >so I doubt I have a connectivity issue or anything like that. > >I also double checked my pull up and downs like 100 times by now. they >all makes sense and match my board with XC2S150E( which I can configure >with no problem) > >Do you guys have any ideas where the problem coming from?.. what other >things I should look at? > >I appreciate you taking the time and reading my long email and helping >me > >Ben Check for ringing on the CCLK signal at the fpga... that has nailed us a couple of times. Try adding 33 pF to ground, just to see if that's the problem. Sometimes just probing CCLK at the chip will allow a config to complete. Rumor has it that some future Xilinx parts will add schmitt triggers to CCLK and maybe some other config pins. Lately, we're adding TinyLogic schmitt buffers right at the pin, unless the trace is *very* short. CCLK signal integrity requirements are right up there with all the other clocks on the board. JohnArticle: 108671
Austin Lesea wrote: > All, > > I was recently asked to do a course, which involves actually showing > folks real hardware, with real software. > > So, like a good teacher, I went and personally purchased the Digilent > pcb (this is not for work!), the USB programming cable, and went at it. > > I also downloaded 8.2 webpack, and the service pack. > > Actually trying to use your own product can be very educational. > > First, I was never able to use the small "boot" loader for webpack > (perhaps firewalls, virus checkers, etc. wouldn't let me). Instead, I > had to download the 900 Mb full file. Since at home is 144 Kb/sec, I > went somewhere where I had 100 Mb/sec access. My recommendation, get > the DVD. > > Then I had to download the service pack, which is 300 Mb. > > OK. Now I just install and go? YES! I am using Windoze XP, not Linux, > so I can't say how easy that route would be. > > Then I asked a few friends to send me links to projects that run on the > pcb. Building very simple (one VHDL module, one ucf file) to more > complex projects went well. As long as I did not try to move any files > around (never do that: project navigator believes it 'owns' the file > system), everything is just fine. Since the last time I actually had to > sit down and make bit streams (6.3), the tool (to me) is greatly improved. > > I also took a while to find FPGA_Editor, as most people don't care about > it anymore, it is relegated to a sub-bullet in the tree of tools. Most > of what I do at work involves FPGA_Editor, as I am usually verifying > hardware functions, and I do not want the software to "get in my way." > But, that is no way to do a real design. > > OK. So, I didn't make the pcb, and I didn't have to debug any hardware, > but I was able to modify vhdl, compile, place, route, and make bit > streams (and they worked). > > So, for those who don't know anything, or know a lot and want to know > more, I can personally suggest going the Digilent 3S200 $99 pcb route: > it is simple, easy, and works. The pcb has a 50 MHz clock, a socket for > another clock oscillator, SDRAM for soft processor apps, flash with > extra area in it, VGA interface, RS232C interface, pc keyboard > interface, and a slew of IOs brought out. Oh, and a 3S200. Which is > huge (to me). I usually always try to verify the smallest part (things > happen faster). I begin to have an appreciation for someone trying to > compile a xcv5lx330 design... > > Find the zipped projects for this board, and have at it. Start with > something small that already works (like the simple seconds/minutes > "clock" -- really a stopwatch), and play around and get more exotic. > > San Jose State University, and many other schools and colleges use this > platform, so there is a lot of 'underground' stuff there, along with > more hardware (if you need it) from Digilent (like A/D, D/A, IO, etc). > > It is also quite nostalgic for me, as the Spartan 3 is the old Virtex II > in a completely new 90nm cost reduced form (so it feels like an old > friend). For those who are reading this for the first time, Virtex II > was the part that I was personally involved in. Because I was in the > Virtex II DCM team, I also did some of the pre-tapeout verification for > the Spartan 3 DCM. > > http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=S3BOARD > > Austin I have this board at home (just for fun). It is well designed. Just add an old VGA monitor and PS2 keyboard and you can do lots of interesting projects. I bought the board from XIlinx online store last year. I think the Xilinx store is no longer selling it (only the S3E board now). Dose this mean that the S3 family is going to be discontinued soon? Mike G.Article: 108672
rickman wrote:
> Ben Jackson wrote:
>> On 2006-09-11, David Ashley <dash@nowhere.net.dont.email.me> wrote:
>>> I want to create a 1152 by 6 bit rom and I want to use
>>> a bram. It can be clocked or not clocked, but I'd prefer
>>> not clocked. Can someone point me to a template?
>> There's a whole PDF of them called "xst.pdf" which you can google.
>
> I was not aware of this document. It looks very useful, but it seems
> to be a bit out of date. It does not mention a number of newer
> families including Spartan 3. I guess the information applies as
> appropriate depending on the feature.
>
> Will Xilinx be updating this document anytime soon?
>
I was also suprised at the number and ages of this file on the web. Then I
looked in my webpack install, here:
.../Xilinx/doc/usenglish/books/docs/xst/xst.pdf
This one is much newer, and bigger.
Ed Coombs
Article: 108673John Larkin wrote: > I've got some DACs that I'd like to switch gain ranges on, and it > turns out I can do it nicely using a single 2N7002 (sot23 n-channel > mosfet) to switch a resistor to ground in each reference circuit. So > I'd like to turn each 7002 on and off from a pin on an XC3S400. But > 3.3 volts is a marginal high for this fet... 4 volts looks safe. > > So, how about running Vccio a bit high, 3.5 maybe, and adding an > external pullup resistor to +5. If I tristate the pin, I should > forward-bias the upper esd diode and get 4.2 roughly, right? I'm > thinking maybe a half milliampere or so pullup current. Doing this 8 > times only dumps 4 mA into the Vccio rail, no hazard there. > > I could use a lower-threshold fet, I guess, but the 7002's are in > stock and cost 3 cents each. You can also switch with NPN transistor + resistor, and a reverse connected one has lower saturation voltage ( and lower beta too ). What resistance do you expect of the on devices ? -jg From nobody@nowhere.com Thu Sep 14 18:18:57 2006 Path: newssvr21.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!news.giganews.com.POSTED!not-for-mail NNTP-Posting-Date: Thu, 14 Sep 2006 20:18:57 -0500 From: nobody <nobody@nowhere.com> Subject: Re: Problems with NIOS II PIO interrupt Date: Thu, 14 Sep 2006 20:18:57 -0500 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2006.09.15.01.18.57.168388@nowhere.com> Newsgroups: comp.arch.fpga References: <1158164612.233455.68550@e63g2000cwd.googlegroups.com> <pan.2006.09.14.00.27.48.598285@nowhere.com> <1158251227.361341.15620@i3g2000cwc.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 29 X-Trace: sv3-HWzIvuXkngVfAxVcXNvDOZH9PSLHgsNAsc7iHpSqWVfu5L0WMhHjJHWMf6bNiIOpofzFTWDP+HqBLAh!ZfA7CFTE69m3nHpPhqwKOvJaaoPnvo5vHcrzFOJoFzqgoGvBuaOTNcZaXuqn5RnsXho= X-Complaints-To: abuse@giganews.com X-DMCA-Notifications: http://www.giganews.com/info/dmca.html X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.32 Xref: prodigy.net comp.arch.fpga:119569 On Thu, 14 Sep 2006 09:27:07 -0700, horst wrote: > Thanks for your answer. > > I tried it that way > > alt_irq_init(ALT_IRQ_BASE); > /* Register the interrupt handler. */ > alt_irq_register( CodecIRQRegBase, context, AudioCodecInISR ); > IOWR_ALTERA_AVALON_PIO_IRQ_MASK(CodecIRQRegBase, 0x3); > /* Reset the Button's edge capture register. */ > IOWR_ALTERA_AVALON_PIO_EDGE_CAP(CodecIRQRegBase, 0x0); > > but it isn't working. > > You're right the code doesn't have any effect. I shortened it to post > it here. > I set a Breakpoint inside the ISR but the breakpoint never breaks the > running debugging execution, so I know that the interrupt newer gets > triggered. The next thing I'd try is to read the edge capture and data in registers in the while loop, printing the contents when they change. That way you can drive the IRQ inputs manually and see if the signals are actually getting to the PIO. Mark From spam1@emorrison.ca Thu Sep 14 18:32:58 2006 Path: newssvr21.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!news-out.readnews.com!news-xxxfer.readnews.com!border2.nntp.dca.giganews.com!nntp.giganews.com!novia!nf3.bellglobal.com!news.ca.mci.com!news.uunet.ca!nnrp.ca.mci.com!nnrp1.uunet.ca.POSTED!53ab2750!not-for-mail Newsgroups: comp.arch.fpga Subject: Re: Spartan3: Multiplier Madness From: James Morrison <spam1@emorrison.ca> In-Reply-To: <4509b5dd.1840491967@news.kpnplanet.nl> References: <4509b5dd.1840491967@news.kpnplanet.nl> Content-Type: text/plain Content-Transfer-Encoding: 7bit Message-Id: <1158283978.4061.39.camel@spice.emorrison.ca> Mime-Version: 1.0 X-Mailer: Evolution 2.2.3-10.1.20060mdk Lines: 23 Date: Thu, 14 Sep 2006 21:32:58 -0400 NNTP-Posting-Host: 216.46.143.247 X-Complaints-To: abuse@ca.mci.com X-Trace: nnrp.ca.mci.com!nnrp1.uunet.ca 1158283879 216.46.143.247 (Thu, 14 Sep 2006 21:31:19 EDT) NNTP-Posting-Date: Thu, 14 Sep 2006 21:31:19 EDT Organization: MCI Canada News Reader Service Xref: prodigy.net comp.arch.fpga:119570 On Thu, 2006-09-14 at 20:13 +0000, Nico Coesel wrote: > Hello everybody, > > In a design I'm working on I want to multiply two 16 bit 2's > complement (signed) numbers using the mult18x18 multipliers. According > to the Sparten 3 userguide, it is enough to use the lower bits and > take the result from the output. However, when I do this, the result > is not correct when negative numbers are multiplied, positive numbers > are no problem. Hi Nico, I recently had a very similar problem. The cause of my problem was that I cut and paste the vhdl template and didn't change the library it was uing. So it was using the unsigned library! Needless to say, that didn't work too well. I changed to using the signed library and it worked fine. Cheers, James.Article: 108674
I am using the ML401 board to build up some test logic. The 100MHz XO on the baord is fed into a DCM via a global buffer. I am using the FX output (x3) to bump the clock up to 300MHz. There is no feedback source on this DCM b/c I don't care about its input/output phase relationship. That FX output is fed to another DCM. The CLK0, CLK90, CLK180, CLK270, and CLKDIV outputs are all used. I am using a data generator to input an LVDS signal. The two signals (data_p and data_n) are fed into the FPGA and connected to an instantiated differential buffer with an LVDS_25 attibute. The output of the buffer is fed to both an external IO and internal logic. I just want to check to make sure the LVDS signal is being transmitted and buffered correctly. I am scoping the output IO (buffered LVDS - single-ended signal at this point) and see some odd behavior. With the LVDS signal ON, the output of the pin looks good. It is the single-ended data I would expect. However, if I turn the data generator off, I get a 300 MHz clock on the output. It is at the IO voltage too - 2.5V...and clean! Now, I can turn the OUTPUT channels of the data generator off. That removes the DC bias on the data_p and data_n signals. The output on the IO pin at that point is garbage...no signal, but it is ugly...not 0 output. If I reset the board...really just resets the DCM and internal logic of the FPGA, the output IO is a 100MHz clock! Remember, this is with the data generator output channels OFF. If I turn them ON (channles are DC biased but no activity on them) and THEN reset the board, I will get the 300MHz clock output. The weird thing is, is that I can HOLD the reset to the board and the 300MHz clock never goes away! I would think that the reset to the DCM's would disable all clock signals. I have checked the data generator to make sure that it wasn't introducing a rogue clock. It isn't. I have moved its output frequency around and never seen it on the output. I really haven't looked into this much, but wanted to throw it out here to see if I am missing something obvious. Thanks.
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